diff options
author | Antti Palosaari <crope@iki.fi> | 2012-09-11 21:27:04 -0400 |
---|---|---|
committer | Mauro Carvalho Chehab <mchehab@redhat.com> | 2012-09-23 16:31:57 -0400 |
commit | 832cc7cdfb8ba78e03cf5c8c0ad9701ed0e20fb6 (patch) | |
tree | a4c64c9fdf4096557ead4e655c1eb153cc555b61 /drivers/media/dvb-frontends/rtl2832_priv.h | |
parent | c2d246d1f0302fb4b390c06b73ca4f0ec6553bc6 (diff) |
[media] rtl2832: separate tuner specific init from general
It is first step closer to support multiple tuners.
Signed-off-by: Antti Palosaari <crope@iki.fi>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/dvb-frontends/rtl2832_priv.h')
-rw-r--r-- | drivers/media/dvb-frontends/rtl2832_priv.h | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/drivers/media/dvb-frontends/rtl2832_priv.h b/drivers/media/dvb-frontends/rtl2832_priv.h index 0ce9502da8ba..65dd62a65684 100644 --- a/drivers/media/dvb-frontends/rtl2832_priv.h +++ b/drivers/media/dvb-frontends/rtl2832_priv.h | |||
@@ -257,4 +257,37 @@ enum DVBT_REG_BIT_NAME { | |||
257 | DVBT_REG_BIT_NAME_ITEM_TERMINATOR, | 257 | DVBT_REG_BIT_NAME_ITEM_TERMINATOR, |
258 | }; | 258 | }; |
259 | 259 | ||
260 | static const struct rtl2832_reg_value rtl2832_tuner_init_fc0012[] = { | ||
261 | {DVBT_DAGC_TRG_VAL, 0x5a}, | ||
262 | {DVBT_AGC_TARG_VAL_0, 0x0}, | ||
263 | {DVBT_AGC_TARG_VAL_8_1, 0x5a}, | ||
264 | {DVBT_AAGC_LOOP_GAIN, 0x16}, | ||
265 | {DVBT_LOOP_GAIN2_3_0, 0x6}, | ||
266 | {DVBT_LOOP_GAIN2_4, 0x1}, | ||
267 | {DVBT_LOOP_GAIN3, 0x16}, | ||
268 | {DVBT_VTOP1, 0x35}, | ||
269 | {DVBT_VTOP2, 0x21}, | ||
270 | {DVBT_VTOP3, 0x21}, | ||
271 | {DVBT_KRF1, 0x0}, | ||
272 | {DVBT_KRF2, 0x40}, | ||
273 | {DVBT_KRF3, 0x10}, | ||
274 | {DVBT_KRF4, 0x10}, | ||
275 | {DVBT_IF_AGC_MIN, 0x80}, | ||
276 | {DVBT_IF_AGC_MAX, 0x7f}, | ||
277 | {DVBT_RF_AGC_MIN, 0x80}, | ||
278 | {DVBT_RF_AGC_MAX, 0x7f}, | ||
279 | {DVBT_POLAR_RF_AGC, 0x0}, | ||
280 | {DVBT_POLAR_IF_AGC, 0x0}, | ||
281 | {DVBT_AD7_SETTING, 0xe9bf}, | ||
282 | {DVBT_EN_GI_PGA, 0x0}, | ||
283 | {DVBT_THD_LOCK_UP, 0x0}, | ||
284 | {DVBT_THD_LOCK_DW, 0x0}, | ||
285 | {DVBT_THD_UP1, 0x11}, | ||
286 | {DVBT_THD_DW1, 0xef}, | ||
287 | {DVBT_INTER_CNT_LEN, 0xc}, | ||
288 | {DVBT_GI_PGA_STATE, 0x0}, | ||
289 | {DVBT_EN_AGC_PGA, 0x1}, | ||
290 | {DVBT_IF_AGC_MAN, 0x0}, | ||
291 | }; | ||
292 | |||
260 | #endif /* RTL2832_PRIV_H */ | 293 | #endif /* RTL2832_PRIV_H */ |