diff options
| author | Suzuki K Poulose <suzuki.poulose@arm.com> | 2016-11-08 08:56:20 -0500 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2016-11-16 12:50:51 -0500 |
| commit | a4023f682739439b434165b54af7cb3676a4766e (patch) | |
| tree | ef2638d37291c56d972f20b69c59a6dee9292c18 /drivers/irqchip | |
| parent | c02433dd6de32f042cf3ffe476746b1115b8c096 (diff) | |
arm64: Add hypervisor safe helper for checking constant capabilities
The hypervisor may not have full access to the kernel data structures
and hence cannot safely use cpus_have_cap() helper for checking the
system capability. Add a safe helper for hypervisors to check a constant
system capability, which *doesn't* fall back to checking the bitmap
maintained by the kernel. With this, make the cpus_have_cap() only
check the bitmask and force constant cap checks to use the new API
for quicker checks.
Cc: Robert Ritcher <rritcher@cavium.com>
Cc: Tirumalesh Chalamarla <tchalamarla@cavium.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'drivers/irqchip')
| -rw-r--r-- | drivers/irqchip/irq-gic-v3.c | 13 |
1 files changed, 1 insertions, 12 deletions
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index 19d642eae096..26e1d7fafb1e 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c | |||
| @@ -120,11 +120,10 @@ static void gic_redist_wait_for_rwp(void) | |||
| 120 | } | 120 | } |
| 121 | 121 | ||
| 122 | #ifdef CONFIG_ARM64 | 122 | #ifdef CONFIG_ARM64 |
| 123 | static DEFINE_STATIC_KEY_FALSE(is_cavium_thunderx); | ||
| 124 | 123 | ||
| 125 | static u64 __maybe_unused gic_read_iar(void) | 124 | static u64 __maybe_unused gic_read_iar(void) |
| 126 | { | 125 | { |
| 127 | if (static_branch_unlikely(&is_cavium_thunderx)) | 126 | if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_23154)) |
| 128 | return gic_read_iar_cavium_thunderx(); | 127 | return gic_read_iar_cavium_thunderx(); |
| 129 | else | 128 | else |
| 130 | return gic_read_iar_common(); | 129 | return gic_read_iar_common(); |
| @@ -905,14 +904,6 @@ static const struct irq_domain_ops partition_domain_ops = { | |||
| 905 | .select = gic_irq_domain_select, | 904 | .select = gic_irq_domain_select, |
| 906 | }; | 905 | }; |
| 907 | 906 | ||
| 908 | static void gicv3_enable_quirks(void) | ||
| 909 | { | ||
| 910 | #ifdef CONFIG_ARM64 | ||
| 911 | if (cpus_have_cap(ARM64_WORKAROUND_CAVIUM_23154)) | ||
| 912 | static_branch_enable(&is_cavium_thunderx); | ||
| 913 | #endif | ||
| 914 | } | ||
| 915 | |||
| 916 | static int __init gic_init_bases(void __iomem *dist_base, | 907 | static int __init gic_init_bases(void __iomem *dist_base, |
| 917 | struct redist_region *rdist_regs, | 908 | struct redist_region *rdist_regs, |
| 918 | u32 nr_redist_regions, | 909 | u32 nr_redist_regions, |
| @@ -935,8 +926,6 @@ static int __init gic_init_bases(void __iomem *dist_base, | |||
| 935 | gic_data.nr_redist_regions = nr_redist_regions; | 926 | gic_data.nr_redist_regions = nr_redist_regions; |
| 936 | gic_data.redist_stride = redist_stride; | 927 | gic_data.redist_stride = redist_stride; |
| 937 | 928 | ||
| 938 | gicv3_enable_quirks(); | ||
| 939 | |||
| 940 | /* | 929 | /* |
| 941 | * Find out how many interrupts are supported. | 930 | * Find out how many interrupts are supported. |
| 942 | * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) | 931 | * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) |
