aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/irqchip/irq-mmp.c
diff options
context:
space:
mode:
authorHaojian Zhuang <haojian.zhuang@gmail.com>2013-04-21 01:21:48 -0400
committerHaojian Zhuang <haojian.zhuang@gmail.com>2013-08-24 05:39:02 -0400
commitc052d13c08b793a13cf0158feca324417bf9ca4b (patch)
tree2659f784e80c6c9d265f322c1e041830479be1fc /drivers/irqchip/irq-mmp.c
parentad81f0545ef01ea651886dddac4bef6cec930092 (diff)
irqchip: move mmp irq driver
Move irq-mmp driver from mach-mmp directory into irqchip directory. It's used to support multiple platform. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Diffstat (limited to 'drivers/irqchip/irq-mmp.c')
-rw-r--r--drivers/irqchip/irq-mmp.c461
1 files changed, 461 insertions, 0 deletions
diff --git a/drivers/irqchip/irq-mmp.c b/drivers/irqchip/irq-mmp.c
new file mode 100644
index 000000000000..dab6def93190
--- /dev/null
+++ b/drivers/irqchip/irq-mmp.c
@@ -0,0 +1,461 @@
1/*
2 * linux/arch/arm/mach-mmp/irq.c
3 *
4 * Generic IRQ handling, GPIO IRQ demultiplexing, etc.
5 * Copyright (C) 2008 - 2012 Marvell Technology Group Ltd.
6 *
7 * Author: Bin Yang <bin.yang@marvell.com>
8 * Haojian Zhuang <haojian.zhuang@gmail.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/module.h>
16#include <linux/init.h>
17#include <linux/irq.h>
18#include <linux/irqdomain.h>
19#include <linux/io.h>
20#include <linux/ioport.h>
21#include <linux/of_address.h>
22#include <linux/of_irq.h>
23
24#include <mach/irqs.h>
25
26#ifdef CONFIG_CPU_MMP2
27#include <mach/pm-mmp2.h>
28#endif
29#ifdef CONFIG_CPU_PXA910
30#include <mach/pm-pxa910.h>
31#endif
32
33#define MAX_ICU_NR 16
34
35struct icu_chip_data {
36 int nr_irqs;
37 unsigned int virq_base;
38 unsigned int cascade_irq;
39 void __iomem *reg_status;
40 void __iomem *reg_mask;
41 unsigned int conf_enable;
42 unsigned int conf_disable;
43 unsigned int conf_mask;
44 unsigned int clr_mfp_irq_base;
45 unsigned int clr_mfp_hwirq;
46 struct irq_domain *domain;
47};
48
49struct mmp_intc_conf {
50 unsigned int conf_enable;
51 unsigned int conf_disable;
52 unsigned int conf_mask;
53};
54
55void __iomem *mmp_icu_base;
56static struct icu_chip_data icu_data[MAX_ICU_NR];
57static int max_icu_nr;
58
59extern void mmp2_clear_pmic_int(void);
60
61static void icu_mask_ack_irq(struct irq_data *d)
62{
63 struct irq_domain *domain = d->domain;
64 struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
65 int hwirq;
66 u32 r;
67
68 hwirq = d->irq - data->virq_base;
69 if (data == &icu_data[0]) {
70 r = readl_relaxed(mmp_icu_base + (hwirq << 2));
71 r &= ~data->conf_mask;
72 r |= data->conf_disable;
73 writel_relaxed(r, mmp_icu_base + (hwirq << 2));
74 } else {
75#ifdef CONFIG_CPU_MMP2
76 if ((data->virq_base == data->clr_mfp_irq_base)
77 && (hwirq == data->clr_mfp_hwirq))
78 mmp2_clear_pmic_int();
79#endif
80 r = readl_relaxed(data->reg_mask) | (1 << hwirq);
81 writel_relaxed(r, data->reg_mask);
82 }
83}
84
85static void icu_mask_irq(struct irq_data *d)
86{
87 struct irq_domain *domain = d->domain;
88 struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
89 int hwirq;
90 u32 r;
91
92 hwirq = d->irq - data->virq_base;
93 if (data == &icu_data[0]) {
94 r = readl_relaxed(mmp_icu_base + (hwirq << 2));
95 r &= ~data->conf_mask;
96 r |= data->conf_disable;
97 writel_relaxed(r, mmp_icu_base + (hwirq << 2));
98 } else {
99 r = readl_relaxed(data->reg_mask) | (1 << hwirq);
100 writel_relaxed(r, data->reg_mask);
101 }
102}
103
104static void icu_unmask_irq(struct irq_data *d)
105{
106 struct irq_domain *domain = d->domain;
107 struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
108 int hwirq;
109 u32 r;
110
111 hwirq = d->irq - data->virq_base;
112 if (data == &icu_data[0]) {
113 r = readl_relaxed(mmp_icu_base + (hwirq << 2));
114 r &= ~data->conf_mask;
115 r |= data->conf_enable;
116 writel_relaxed(r, mmp_icu_base + (hwirq << 2));
117 } else {
118 r = readl_relaxed(data->reg_mask) & ~(1 << hwirq);
119 writel_relaxed(r, data->reg_mask);
120 }
121}
122
123static struct irq_chip icu_irq_chip = {
124 .name = "icu_irq",
125 .irq_mask = icu_mask_irq,
126 .irq_mask_ack = icu_mask_ack_irq,
127 .irq_unmask = icu_unmask_irq,
128};
129
130static void icu_mux_irq_demux(unsigned int irq, struct irq_desc *desc)
131{
132 struct irq_domain *domain;
133 struct icu_chip_data *data;
134 int i;
135 unsigned long mask, status, n;
136
137 for (i = 1; i < max_icu_nr; i++) {
138 if (irq == icu_data[i].cascade_irq) {
139 domain = icu_data[i].domain;
140 data = (struct icu_chip_data *)domain->host_data;
141 break;
142 }
143 }
144 if (i >= max_icu_nr) {
145 pr_err("Spurious irq %d in MMP INTC\n", irq);
146 return;
147 }
148
149 mask = readl_relaxed(data->reg_mask);
150 while (1) {
151 status = readl_relaxed(data->reg_status) & ~mask;
152 if (status == 0)
153 break;
154 for_each_set_bit(n, &status, BITS_PER_LONG) {
155 generic_handle_irq(icu_data[i].virq_base + n);
156 }
157 }
158}
159
160static int mmp_irq_domain_map(struct irq_domain *d, unsigned int irq,
161 irq_hw_number_t hw)
162{
163 irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
164 set_irq_flags(irq, IRQF_VALID);
165 return 0;
166}
167
168static int mmp_irq_domain_xlate(struct irq_domain *d, struct device_node *node,
169 const u32 *intspec, unsigned int intsize,
170 unsigned long *out_hwirq,
171 unsigned int *out_type)
172{
173 *out_hwirq = intspec[0];
174 return 0;
175}
176
177const struct irq_domain_ops mmp_irq_domain_ops = {
178 .map = mmp_irq_domain_map,
179 .xlate = mmp_irq_domain_xlate,
180};
181
182static struct mmp_intc_conf mmp_conf = {
183 .conf_enable = 0x51,
184 .conf_disable = 0x0,
185 .conf_mask = 0x7f,
186};
187
188static struct mmp_intc_conf mmp2_conf = {
189 .conf_enable = 0x20,
190 .conf_disable = 0x0,
191 .conf_mask = 0x7f,
192};
193
194/* MMP (ARMv5) */
195void __init icu_init_irq(void)
196{
197 int irq;
198
199 max_icu_nr = 1;
200 mmp_icu_base = ioremap(0xd4282000, 0x1000);
201 icu_data[0].conf_enable = mmp_conf.conf_enable;
202 icu_data[0].conf_disable = mmp_conf.conf_disable;
203 icu_data[0].conf_mask = mmp_conf.conf_mask;
204 icu_data[0].nr_irqs = 64;
205 icu_data[0].virq_base = 0;
206 icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0,
207 &irq_domain_simple_ops,
208 &icu_data[0]);
209 for (irq = 0; irq < 64; irq++) {
210 icu_mask_irq(irq_get_irq_data(irq));
211 irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
212 set_irq_flags(irq, IRQF_VALID);
213 }
214 irq_set_default_host(icu_data[0].domain);
215#ifdef CONFIG_CPU_PXA910
216 icu_irq_chip.irq_set_wake = pxa910_set_wake;
217#endif
218}
219
220/* MMP2 (ARMv7) */
221void __init mmp2_init_icu(void)
222{
223 int irq;
224
225 max_icu_nr = 8;
226 mmp_icu_base = ioremap(0xd4282000, 0x1000);
227 icu_data[0].conf_enable = mmp2_conf.conf_enable;
228 icu_data[0].conf_disable = mmp2_conf.conf_disable;
229 icu_data[0].conf_mask = mmp2_conf.conf_mask;
230 icu_data[0].nr_irqs = 64;
231 icu_data[0].virq_base = 0;
232 icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0,
233 &irq_domain_simple_ops,
234 &icu_data[0]);
235 icu_data[1].reg_status = mmp_icu_base + 0x150;
236 icu_data[1].reg_mask = mmp_icu_base + 0x168;
237 icu_data[1].clr_mfp_irq_base = IRQ_MMP2_PMIC_BASE;
238 icu_data[1].clr_mfp_hwirq = IRQ_MMP2_PMIC - IRQ_MMP2_PMIC_BASE;
239 icu_data[1].nr_irqs = 2;
240 icu_data[1].cascade_irq = 4;
241 icu_data[1].virq_base = IRQ_MMP2_PMIC_BASE;
242 icu_data[1].domain = irq_domain_add_legacy(NULL, icu_data[1].nr_irqs,
243 icu_data[1].virq_base, 0,
244 &irq_domain_simple_ops,
245 &icu_data[1]);
246 icu_data[2].reg_status = mmp_icu_base + 0x154;
247 icu_data[2].reg_mask = mmp_icu_base + 0x16c;
248 icu_data[2].nr_irqs = 2;
249 icu_data[2].cascade_irq = 5;
250 icu_data[2].virq_base = IRQ_MMP2_RTC_BASE;
251 icu_data[2].domain = irq_domain_add_legacy(NULL, icu_data[2].nr_irqs,
252 icu_data[2].virq_base, 0,
253 &irq_domain_simple_ops,
254 &icu_data[2]);
255 icu_data[3].reg_status = mmp_icu_base + 0x180;
256 icu_data[3].reg_mask = mmp_icu_base + 0x17c;
257 icu_data[3].nr_irqs = 3;
258 icu_data[3].cascade_irq = 9;
259 icu_data[3].virq_base = IRQ_MMP2_KEYPAD_BASE;
260 icu_data[3].domain = irq_domain_add_legacy(NULL, icu_data[3].nr_irqs,
261 icu_data[3].virq_base, 0,
262 &irq_domain_simple_ops,
263 &icu_data[3]);
264 icu_data[4].reg_status = mmp_icu_base + 0x158;
265 icu_data[4].reg_mask = mmp_icu_base + 0x170;
266 icu_data[4].nr_irqs = 5;
267 icu_data[4].cascade_irq = 17;
268 icu_data[4].virq_base = IRQ_MMP2_TWSI_BASE;
269 icu_data[4].domain = irq_domain_add_legacy(NULL, icu_data[4].nr_irqs,
270 icu_data[4].virq_base, 0,
271 &irq_domain_simple_ops,
272 &icu_data[4]);
273 icu_data[5].reg_status = mmp_icu_base + 0x15c;
274 icu_data[5].reg_mask = mmp_icu_base + 0x174;
275 icu_data[5].nr_irqs = 15;
276 icu_data[5].cascade_irq = 35;
277 icu_data[5].virq_base = IRQ_MMP2_MISC_BASE;
278 icu_data[5].domain = irq_domain_add_legacy(NULL, icu_data[5].nr_irqs,
279 icu_data[5].virq_base, 0,
280 &irq_domain_simple_ops,
281 &icu_data[5]);
282 icu_data[6].reg_status = mmp_icu_base + 0x160;
283 icu_data[6].reg_mask = mmp_icu_base + 0x178;
284 icu_data[6].nr_irqs = 2;
285 icu_data[6].cascade_irq = 51;
286 icu_data[6].virq_base = IRQ_MMP2_MIPI_HSI1_BASE;
287 icu_data[6].domain = irq_domain_add_legacy(NULL, icu_data[6].nr_irqs,
288 icu_data[6].virq_base, 0,
289 &irq_domain_simple_ops,
290 &icu_data[6]);
291 icu_data[7].reg_status = mmp_icu_base + 0x188;
292 icu_data[7].reg_mask = mmp_icu_base + 0x184;
293 icu_data[7].nr_irqs = 2;
294 icu_data[7].cascade_irq = 55;
295 icu_data[7].virq_base = IRQ_MMP2_MIPI_HSI0_BASE;
296 icu_data[7].domain = irq_domain_add_legacy(NULL, icu_data[7].nr_irqs,
297 icu_data[7].virq_base, 0,
298 &irq_domain_simple_ops,
299 &icu_data[7]);
300 for (irq = 0; irq < IRQ_MMP2_MUX_END; irq++) {
301 icu_mask_irq(irq_get_irq_data(irq));
302 switch (irq) {
303 case IRQ_MMP2_PMIC_MUX:
304 case IRQ_MMP2_RTC_MUX:
305 case IRQ_MMP2_KEYPAD_MUX:
306 case IRQ_MMP2_TWSI_MUX:
307 case IRQ_MMP2_MISC_MUX:
308 case IRQ_MMP2_MIPI_HSI1_MUX:
309 case IRQ_MMP2_MIPI_HSI0_MUX:
310 irq_set_chip(irq, &icu_irq_chip);
311 irq_set_chained_handler(irq, icu_mux_irq_demux);
312 break;
313 default:
314 irq_set_chip_and_handler(irq, &icu_irq_chip,
315 handle_level_irq);
316 break;
317 }
318 set_irq_flags(irq, IRQF_VALID);
319 }
320 irq_set_default_host(icu_data[0].domain);
321#ifdef CONFIG_CPU_MMP2
322 icu_irq_chip.irq_set_wake = mmp2_set_wake;
323#endif
324}
325
326#ifdef CONFIG_OF
327static const struct of_device_id intc_ids[] __initconst = {
328 { .compatible = "mrvl,mmp-intc", .data = &mmp_conf },
329 { .compatible = "mrvl,mmp2-intc", .data = &mmp2_conf },
330 {}
331};
332
333static const struct of_device_id mmp_mux_irq_match[] __initconst = {
334 { .compatible = "mrvl,mmp2-mux-intc" },
335 {}
336};
337
338int __init mmp2_mux_init(struct device_node *parent)
339{
340 struct device_node *node;
341 const struct of_device_id *of_id;
342 struct resource res;
343 int i, irq_base, ret, irq;
344 u32 nr_irqs, mfp_irq;
345
346 node = parent;
347 max_icu_nr = 1;
348 for (i = 1; i < MAX_ICU_NR; i++) {
349 node = of_find_matching_node(node, mmp_mux_irq_match);
350 if (!node)
351 break;
352 of_id = of_match_node(&mmp_mux_irq_match[0], node);
353 ret = of_property_read_u32(node, "mrvl,intc-nr-irqs",
354 &nr_irqs);
355 if (ret) {
356 pr_err("Not found mrvl,intc-nr-irqs property\n");
357 ret = -EINVAL;
358 goto err;
359 }
360 ret = of_address_to_resource(node, 0, &res);
361 if (ret < 0) {
362 pr_err("Not found reg property\n");
363 ret = -EINVAL;
364 goto err;
365 }
366 icu_data[i].reg_status = mmp_icu_base + res.start;
367 ret = of_address_to_resource(node, 1, &res);
368 if (ret < 0) {
369 pr_err("Not found reg property\n");
370 ret = -EINVAL;
371 goto err;
372 }
373 icu_data[i].reg_mask = mmp_icu_base + res.start;
374 icu_data[i].cascade_irq = irq_of_parse_and_map(node, 0);
375 if (!icu_data[i].cascade_irq) {
376 ret = -EINVAL;
377 goto err;
378 }
379
380 irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
381 if (irq_base < 0) {
382 pr_err("Failed to allocate IRQ numbers for mux intc\n");
383 ret = irq_base;
384 goto err;
385 }
386 if (!of_property_read_u32(node, "mrvl,clr-mfp-irq",
387 &mfp_irq)) {
388 icu_data[i].clr_mfp_irq_base = irq_base;
389 icu_data[i].clr_mfp_hwirq = mfp_irq;
390 }
391 irq_set_chained_handler(icu_data[i].cascade_irq,
392 icu_mux_irq_demux);
393 icu_data[i].nr_irqs = nr_irqs;
394 icu_data[i].virq_base = irq_base;
395 icu_data[i].domain = irq_domain_add_legacy(node, nr_irqs,
396 irq_base, 0,
397 &mmp_irq_domain_ops,
398 &icu_data[i]);
399 for (irq = irq_base; irq < irq_base + nr_irqs; irq++)
400 icu_mask_irq(irq_get_irq_data(irq));
401 }
402 max_icu_nr = i;
403 return 0;
404err:
405 of_node_put(node);
406 max_icu_nr = i;
407 return ret;
408}
409
410void __init mmp_dt_irq_init(void)
411{
412 struct device_node *node;
413 const struct of_device_id *of_id;
414 struct mmp_intc_conf *conf;
415 int nr_irqs, irq_base, ret, irq;
416
417 node = of_find_matching_node(NULL, intc_ids);
418 if (!node) {
419 pr_err("Failed to find interrupt controller in arch-mmp\n");
420 return;
421 }
422 of_id = of_match_node(intc_ids, node);
423 conf = of_id->data;
424
425 ret = of_property_read_u32(node, "mrvl,intc-nr-irqs", &nr_irqs);
426 if (ret) {
427 pr_err("Not found mrvl,intc-nr-irqs property\n");
428 return;
429 }
430
431 mmp_icu_base = of_iomap(node, 0);
432 if (!mmp_icu_base) {
433 pr_err("Failed to get interrupt controller register\n");
434 return;
435 }
436
437 irq_base = irq_alloc_descs(-1, 0, nr_irqs - NR_IRQS_LEGACY, 0);
438 if (irq_base < 0) {
439 pr_err("Failed to allocate IRQ numbers\n");
440 goto err;
441 } else if (irq_base != NR_IRQS_LEGACY) {
442 pr_err("ICU's irqbase should be started from 0\n");
443 goto err;
444 }
445 icu_data[0].conf_enable = conf->conf_enable;
446 icu_data[0].conf_disable = conf->conf_disable;
447 icu_data[0].conf_mask = conf->conf_mask;
448 icu_data[0].nr_irqs = nr_irqs;
449 icu_data[0].virq_base = 0;
450 icu_data[0].domain = irq_domain_add_legacy(node, nr_irqs, 0, 0,
451 &mmp_irq_domain_ops,
452 &icu_data[0]);
453 irq_set_default_host(icu_data[0].domain);
454 for (irq = 0; irq < nr_irqs; irq++)
455 icu_mask_irq(irq_get_irq_data(irq));
456 mmp2_mux_init(node);
457 return;
458err:
459 iounmap(mmp_icu_base);
460}
461#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-19 06:58:26 -0500