diff options
| author | Ludovic Desroches <ludovic.desroches@atmel.com> | 2016-03-03 11:09:14 -0500 |
|---|---|---|
| committer | Jonathan Cameron <jic23@kernel.org> | 2016-03-05 10:02:59 -0500 |
| commit | f0fa15cce13d5987c50907eb98846d13e2b4d9ca (patch) | |
| tree | cd6873de47096dda19b5832d13086af1f4944ab6 /drivers/iio | |
| parent | 43d33f7458383ff6ce9838fca7b78b9b64fb988a (diff) | |
iio:adc:at91-sama5d2: fix identation
Remove some extra tabs.
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
Diffstat (limited to 'drivers/iio')
| -rw-r--r-- | drivers/iio/adc/at91-sama5d2_adc.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c index 33bacece325c..5bc038f23609 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c | |||
| @@ -92,13 +92,13 @@ | |||
| 92 | /* Last Converted Data Register */ | 92 | /* Last Converted Data Register */ |
| 93 | #define AT91_SAMA5D2_LCDR 0x20 | 93 | #define AT91_SAMA5D2_LCDR 0x20 |
| 94 | /* Interrupt Enable Register */ | 94 | /* Interrupt Enable Register */ |
| 95 | #define AT91_SAMA5D2_IER 0x24 | 95 | #define AT91_SAMA5D2_IER 0x24 |
| 96 | /* Interrupt Disable Register */ | 96 | /* Interrupt Disable Register */ |
| 97 | #define AT91_SAMA5D2_IDR 0x28 | 97 | #define AT91_SAMA5D2_IDR 0x28 |
| 98 | /* Interrupt Mask Register */ | 98 | /* Interrupt Mask Register */ |
| 99 | #define AT91_SAMA5D2_IMR 0x2c | 99 | #define AT91_SAMA5D2_IMR 0x2c |
| 100 | /* Interrupt Status Register */ | 100 | /* Interrupt Status Register */ |
| 101 | #define AT91_SAMA5D2_ISR 0x30 | 101 | #define AT91_SAMA5D2_ISR 0x30 |
| 102 | /* Last Channel Trigger Mode Register */ | 102 | /* Last Channel Trigger Mode Register */ |
| 103 | #define AT91_SAMA5D2_LCTMR 0x34 | 103 | #define AT91_SAMA5D2_LCTMR 0x34 |
| 104 | /* Last Channel Compare Window Register */ | 104 | /* Last Channel Compare Window Register */ |
| @@ -106,17 +106,17 @@ | |||
| 106 | /* Overrun Status Register */ | 106 | /* Overrun Status Register */ |
| 107 | #define AT91_SAMA5D2_OVER 0x3c | 107 | #define AT91_SAMA5D2_OVER 0x3c |
| 108 | /* Extended Mode Register */ | 108 | /* Extended Mode Register */ |
| 109 | #define AT91_SAMA5D2_EMR 0x40 | 109 | #define AT91_SAMA5D2_EMR 0x40 |
| 110 | /* Compare Window Register */ | 110 | /* Compare Window Register */ |
| 111 | #define AT91_SAMA5D2_CWR 0x44 | 111 | #define AT91_SAMA5D2_CWR 0x44 |
| 112 | /* Channel Gain Register */ | 112 | /* Channel Gain Register */ |
| 113 | #define AT91_SAMA5D2_CGR 0x48 | 113 | #define AT91_SAMA5D2_CGR 0x48 |
| 114 | /* Channel Offset Register */ | 114 | /* Channel Offset Register */ |
| 115 | #define AT91_SAMA5D2_COR 0x4c | 115 | #define AT91_SAMA5D2_COR 0x4c |
| 116 | /* Channel Data Register 0 */ | 116 | /* Channel Data Register 0 */ |
| 117 | #define AT91_SAMA5D2_CDR0 0x50 | 117 | #define AT91_SAMA5D2_CDR0 0x50 |
| 118 | /* Analog Control Register */ | 118 | /* Analog Control Register */ |
| 119 | #define AT91_SAMA5D2_ACR 0x94 | 119 | #define AT91_SAMA5D2_ACR 0x94 |
| 120 | /* Touchscreen Mode Register */ | 120 | /* Touchscreen Mode Register */ |
| 121 | #define AT91_SAMA5D2_TSMR 0xb0 | 121 | #define AT91_SAMA5D2_TSMR 0xb0 |
| 122 | /* Touchscreen X Position Register */ | 122 | /* Touchscreen X Position Register */ |
| @@ -130,7 +130,7 @@ | |||
| 130 | /* Correction Select Register */ | 130 | /* Correction Select Register */ |
| 131 | #define AT91_SAMA5D2_COSR 0xd0 | 131 | #define AT91_SAMA5D2_COSR 0xd0 |
| 132 | /* Correction Value Register */ | 132 | /* Correction Value Register */ |
| 133 | #define AT91_SAMA5D2_CVR 0xd4 | 133 | #define AT91_SAMA5D2_CVR 0xd4 |
| 134 | /* Channel Error Correction Register */ | 134 | /* Channel Error Correction Register */ |
| 135 | #define AT91_SAMA5D2_CECR 0xd8 | 135 | #define AT91_SAMA5D2_CECR 0xd8 |
| 136 | /* Write Protection Mode Register */ | 136 | /* Write Protection Mode Register */ |