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authorRafael J. Wysocki <rafael.j.wysocki@intel.com>2017-09-03 18:06:02 -0400
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2017-09-03 18:06:02 -0400
commit7b01463e51f6849d0787b24d06a62efcb243dd44 (patch)
treec084f9b5290fe4b6f279e711c0ada7be9dca8b32 /drivers/idle/intel_idle.c
parenta1b5fd8fa29fb2359f398ef17a706449d94de80d (diff)
parent726fb6b4f2a82a14a906f39bdabac4863b87c01a (diff)
Merge branch 'pm-sleep'
* pm-sleep: ACPI / PM: Check low power idle constraints for debug only PM / s2idle: Rename platform operations structure PM / s2idle: Rename ->enter_freeze to ->enter_s2idle PM / s2idle: Rename freeze_state enum and related items PM / s2idle: Rename PM_SUSPEND_FREEZE to PM_SUSPEND_TO_IDLE ACPI / PM: Prefer suspend-to-idle over S3 on some systems platform/x86: intel-hid: Wake up Dell Latitude 7275 from suspend-to-idle PM / suspend: Define pr_fmt() in suspend.c PM / suspend: Use mem_sleep_labels[] strings in messages PM / sleep: Put pm_test under CONFIG_PM_SLEEP_DEBUG PM / sleep: Check pm_wakeup_pending() in __device_suspend_noirq() PM / core: Add error argument to dpm_show_time() PM / core: Split dpm_suspend_noirq() and dpm_resume_noirq() PM / s2idle: Rearrange the main suspend-to-idle loop PM / timekeeping: Print debug messages when requested PM / sleep: Mark suspend/hibernation start and finish PM / sleep: Do not print debug messages by default PM / suspend: Export pm_suspend_target_state
Diffstat (limited to 'drivers/idle/intel_idle.c')
-rw-r--r--drivers/idle/intel_idle.c180
1 files changed, 90 insertions, 90 deletions
diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c
index 7bf8739e33bc..f0b06b14e782 100644
--- a/drivers/idle/intel_idle.c
+++ b/drivers/idle/intel_idle.c
@@ -97,7 +97,7 @@ static const struct idle_cpu *icpu;
97static struct cpuidle_device __percpu *intel_idle_cpuidle_devices; 97static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
98static int intel_idle(struct cpuidle_device *dev, 98static int intel_idle(struct cpuidle_device *dev,
99 struct cpuidle_driver *drv, int index); 99 struct cpuidle_driver *drv, int index);
100static void intel_idle_freeze(struct cpuidle_device *dev, 100static void intel_idle_s2idle(struct cpuidle_device *dev,
101 struct cpuidle_driver *drv, int index); 101 struct cpuidle_driver *drv, int index);
102static struct cpuidle_state *cpuidle_state_table; 102static struct cpuidle_state *cpuidle_state_table;
103 103
@@ -132,7 +132,7 @@ static struct cpuidle_state nehalem_cstates[] = {
132 .exit_latency = 3, 132 .exit_latency = 3,
133 .target_residency = 6, 133 .target_residency = 6,
134 .enter = &intel_idle, 134 .enter = &intel_idle,
135 .enter_freeze = intel_idle_freeze, }, 135 .enter_s2idle = intel_idle_s2idle, },
136 { 136 {
137 .name = "C1E", 137 .name = "C1E",
138 .desc = "MWAIT 0x01", 138 .desc = "MWAIT 0x01",
@@ -140,7 +140,7 @@ static struct cpuidle_state nehalem_cstates[] = {
140 .exit_latency = 10, 140 .exit_latency = 10,
141 .target_residency = 20, 141 .target_residency = 20,
142 .enter = &intel_idle, 142 .enter = &intel_idle,
143 .enter_freeze = intel_idle_freeze, }, 143 .enter_s2idle = intel_idle_s2idle, },
144 { 144 {
145 .name = "C3", 145 .name = "C3",
146 .desc = "MWAIT 0x10", 146 .desc = "MWAIT 0x10",
@@ -148,7 +148,7 @@ static struct cpuidle_state nehalem_cstates[] = {
148 .exit_latency = 20, 148 .exit_latency = 20,
149 .target_residency = 80, 149 .target_residency = 80,
150 .enter = &intel_idle, 150 .enter = &intel_idle,
151 .enter_freeze = intel_idle_freeze, }, 151 .enter_s2idle = intel_idle_s2idle, },
152 { 152 {
153 .name = "C6", 153 .name = "C6",
154 .desc = "MWAIT 0x20", 154 .desc = "MWAIT 0x20",
@@ -156,7 +156,7 @@ static struct cpuidle_state nehalem_cstates[] = {
156 .exit_latency = 200, 156 .exit_latency = 200,
157 .target_residency = 800, 157 .target_residency = 800,
158 .enter = &intel_idle, 158 .enter = &intel_idle,
159 .enter_freeze = intel_idle_freeze, }, 159 .enter_s2idle = intel_idle_s2idle, },
160 { 160 {
161 .enter = NULL } 161 .enter = NULL }
162}; 162};
@@ -169,7 +169,7 @@ static struct cpuidle_state snb_cstates[] = {
169 .exit_latency = 2, 169 .exit_latency = 2,
170 .target_residency = 2, 170 .target_residency = 2,
171 .enter = &intel_idle, 171 .enter = &intel_idle,
172 .enter_freeze = intel_idle_freeze, }, 172 .enter_s2idle = intel_idle_s2idle, },
173 { 173 {
174 .name = "C1E", 174 .name = "C1E",
175 .desc = "MWAIT 0x01", 175 .desc = "MWAIT 0x01",
@@ -177,7 +177,7 @@ static struct cpuidle_state snb_cstates[] = {
177 .exit_latency = 10, 177 .exit_latency = 10,
178 .target_residency = 20, 178 .target_residency = 20,
179 .enter = &intel_idle, 179 .enter = &intel_idle,
180 .enter_freeze = intel_idle_freeze, }, 180 .enter_s2idle = intel_idle_s2idle, },
181 { 181 {
182 .name = "C3", 182 .name = "C3",
183 .desc = "MWAIT 0x10", 183 .desc = "MWAIT 0x10",
@@ -185,7 +185,7 @@ static struct cpuidle_state snb_cstates[] = {
185 .exit_latency = 80, 185 .exit_latency = 80,
186 .target_residency = 211, 186 .target_residency = 211,
187 .enter = &intel_idle, 187 .enter = &intel_idle,
188 .enter_freeze = intel_idle_freeze, }, 188 .enter_s2idle = intel_idle_s2idle, },
189 { 189 {
190 .name = "C6", 190 .name = "C6",
191 .desc = "MWAIT 0x20", 191 .desc = "MWAIT 0x20",
@@ -193,7 +193,7 @@ static struct cpuidle_state snb_cstates[] = {
193 .exit_latency = 104, 193 .exit_latency = 104,
194 .target_residency = 345, 194 .target_residency = 345,
195 .enter = &intel_idle, 195 .enter = &intel_idle,
196 .enter_freeze = intel_idle_freeze, }, 196 .enter_s2idle = intel_idle_s2idle, },
197 { 197 {
198 .name = "C7", 198 .name = "C7",
199 .desc = "MWAIT 0x30", 199 .desc = "MWAIT 0x30",
@@ -201,7 +201,7 @@ static struct cpuidle_state snb_cstates[] = {
201 .exit_latency = 109, 201 .exit_latency = 109,
202 .target_residency = 345, 202 .target_residency = 345,
203 .enter = &intel_idle, 203 .enter = &intel_idle,
204 .enter_freeze = intel_idle_freeze, }, 204 .enter_s2idle = intel_idle_s2idle, },
205 { 205 {
206 .enter = NULL } 206 .enter = NULL }
207}; 207};
@@ -214,7 +214,7 @@ static struct cpuidle_state byt_cstates[] = {
214 .exit_latency = 1, 214 .exit_latency = 1,
215 .target_residency = 1, 215 .target_residency = 1,
216 .enter = &intel_idle, 216 .enter = &intel_idle,
217 .enter_freeze = intel_idle_freeze, }, 217 .enter_s2idle = intel_idle_s2idle, },
218 { 218 {
219 .name = "C6N", 219 .name = "C6N",
220 .desc = "MWAIT 0x58", 220 .desc = "MWAIT 0x58",
@@ -222,7 +222,7 @@ static struct cpuidle_state byt_cstates[] = {
222 .exit_latency = 300, 222 .exit_latency = 300,
223 .target_residency = 275, 223 .target_residency = 275,
224 .enter = &intel_idle, 224 .enter = &intel_idle,
225 .enter_freeze = intel_idle_freeze, }, 225 .enter_s2idle = intel_idle_s2idle, },
226 { 226 {
227 .name = "C6S", 227 .name = "C6S",
228 .desc = "MWAIT 0x52", 228 .desc = "MWAIT 0x52",
@@ -230,7 +230,7 @@ static struct cpuidle_state byt_cstates[] = {
230 .exit_latency = 500, 230 .exit_latency = 500,
231 .target_residency = 560, 231 .target_residency = 560,
232 .enter = &intel_idle, 232 .enter = &intel_idle,
233 .enter_freeze = intel_idle_freeze, }, 233 .enter_s2idle = intel_idle_s2idle, },
234 { 234 {
235 .name = "C7", 235 .name = "C7",
236 .desc = "MWAIT 0x60", 236 .desc = "MWAIT 0x60",
@@ -238,7 +238,7 @@ static struct cpuidle_state byt_cstates[] = {
238 .exit_latency = 1200, 238 .exit_latency = 1200,
239 .target_residency = 4000, 239 .target_residency = 4000,
240 .enter = &intel_idle, 240 .enter = &intel_idle,
241 .enter_freeze = intel_idle_freeze, }, 241 .enter_s2idle = intel_idle_s2idle, },
242 { 242 {
243 .name = "C7S", 243 .name = "C7S",
244 .desc = "MWAIT 0x64", 244 .desc = "MWAIT 0x64",
@@ -246,7 +246,7 @@ static struct cpuidle_state byt_cstates[] = {
246 .exit_latency = 10000, 246 .exit_latency = 10000,
247 .target_residency = 20000, 247 .target_residency = 20000,
248 .enter = &intel_idle, 248 .enter = &intel_idle,
249 .enter_freeze = intel_idle_freeze, }, 249 .enter_s2idle = intel_idle_s2idle, },
250 { 250 {
251 .enter = NULL } 251 .enter = NULL }
252}; 252};
@@ -259,7 +259,7 @@ static struct cpuidle_state cht_cstates[] = {
259 .exit_latency = 1, 259 .exit_latency = 1,
260 .target_residency = 1, 260 .target_residency = 1,
261 .enter = &intel_idle, 261 .enter = &intel_idle,
262 .enter_freeze = intel_idle_freeze, }, 262 .enter_s2idle = intel_idle_s2idle, },
263 { 263 {
264 .name = "C6N", 264 .name = "C6N",
265 .desc = "MWAIT 0x58", 265 .desc = "MWAIT 0x58",
@@ -267,7 +267,7 @@ static struct cpuidle_state cht_cstates[] = {
267 .exit_latency = 80, 267 .exit_latency = 80,
268 .target_residency = 275, 268 .target_residency = 275,
269 .enter = &intel_idle, 269 .enter = &intel_idle,
270 .enter_freeze = intel_idle_freeze, }, 270 .enter_s2idle = intel_idle_s2idle, },
271 { 271 {
272 .name = "C6S", 272 .name = "C6S",
273 .desc = "MWAIT 0x52", 273 .desc = "MWAIT 0x52",
@@ -275,7 +275,7 @@ static struct cpuidle_state cht_cstates[] = {
275 .exit_latency = 200, 275 .exit_latency = 200,
276 .target_residency = 560, 276 .target_residency = 560,
277 .enter = &intel_idle, 277 .enter = &intel_idle,
278 .enter_freeze = intel_idle_freeze, }, 278 .enter_s2idle = intel_idle_s2idle, },
279 { 279 {
280 .name = "C7", 280 .name = "C7",
281 .desc = "MWAIT 0x60", 281 .desc = "MWAIT 0x60",
@@ -283,7 +283,7 @@ static struct cpuidle_state cht_cstates[] = {
283 .exit_latency = 1200, 283 .exit_latency = 1200,
284 .target_residency = 4000, 284 .target_residency = 4000,
285 .enter = &intel_idle, 285 .enter = &intel_idle,
286 .enter_freeze = intel_idle_freeze, }, 286 .enter_s2idle = intel_idle_s2idle, },
287 { 287 {
288 .name = "C7S", 288 .name = "C7S",
289 .desc = "MWAIT 0x64", 289 .desc = "MWAIT 0x64",
@@ -291,7 +291,7 @@ static struct cpuidle_state cht_cstates[] = {
291 .exit_latency = 10000, 291 .exit_latency = 10000,
292 .target_residency = 20000, 292 .target_residency = 20000,
293 .enter = &intel_idle, 293 .enter = &intel_idle,
294 .enter_freeze = intel_idle_freeze, }, 294 .enter_s2idle = intel_idle_s2idle, },
295 { 295 {
296 .enter = NULL } 296 .enter = NULL }
297}; 297};
@@ -304,7 +304,7 @@ static struct cpuidle_state ivb_cstates[] = {
304 .exit_latency = 1, 304 .exit_latency = 1,
305 .target_residency = 1, 305 .target_residency = 1,
306 .enter = &intel_idle, 306 .enter = &intel_idle,
307 .enter_freeze = intel_idle_freeze, }, 307 .enter_s2idle = intel_idle_s2idle, },
308 { 308 {
309 .name = "C1E", 309 .name = "C1E",
310 .desc = "MWAIT 0x01", 310 .desc = "MWAIT 0x01",
@@ -312,7 +312,7 @@ static struct cpuidle_state ivb_cstates[] = {
312 .exit_latency = 10, 312 .exit_latency = 10,
313 .target_residency = 20, 313 .target_residency = 20,
314 .enter = &intel_idle, 314 .enter = &intel_idle,
315 .enter_freeze = intel_idle_freeze, }, 315 .enter_s2idle = intel_idle_s2idle, },
316 { 316 {
317 .name = "C3", 317 .name = "C3",
318 .desc = "MWAIT 0x10", 318 .desc = "MWAIT 0x10",
@@ -320,7 +320,7 @@ static struct cpuidle_state ivb_cstates[] = {
320 .exit_latency = 59, 320 .exit_latency = 59,
321 .target_residency = 156, 321 .target_residency = 156,
322 .enter = &intel_idle, 322 .enter = &intel_idle,
323 .enter_freeze = intel_idle_freeze, }, 323 .enter_s2idle = intel_idle_s2idle, },
324 { 324 {
325 .name = "C6", 325 .name = "C6",
326 .desc = "MWAIT 0x20", 326 .desc = "MWAIT 0x20",
@@ -328,7 +328,7 @@ static struct cpuidle_state ivb_cstates[] = {
328 .exit_latency = 80, 328 .exit_latency = 80,
329 .target_residency = 300, 329 .target_residency = 300,
330 .enter = &intel_idle, 330 .enter = &intel_idle,
331 .enter_freeze = intel_idle_freeze, }, 331 .enter_s2idle = intel_idle_s2idle, },
332 { 332 {
333 .name = "C7", 333 .name = "C7",
334 .desc = "MWAIT 0x30", 334 .desc = "MWAIT 0x30",
@@ -336,7 +336,7 @@ static struct cpuidle_state ivb_cstates[] = {
336 .exit_latency = 87, 336 .exit_latency = 87,
337 .target_residency = 300, 337 .target_residency = 300,
338 .enter = &intel_idle, 338 .enter = &intel_idle,
339 .enter_freeze = intel_idle_freeze, }, 339 .enter_s2idle = intel_idle_s2idle, },
340 { 340 {
341 .enter = NULL } 341 .enter = NULL }
342}; 342};
@@ -349,7 +349,7 @@ static struct cpuidle_state ivt_cstates[] = {
349 .exit_latency = 1, 349 .exit_latency = 1,
350 .target_residency = 1, 350 .target_residency = 1,
351 .enter = &intel_idle, 351 .enter = &intel_idle,
352 .enter_freeze = intel_idle_freeze, }, 352 .enter_s2idle = intel_idle_s2idle, },
353 { 353 {
354 .name = "C1E", 354 .name = "C1E",
355 .desc = "MWAIT 0x01", 355 .desc = "MWAIT 0x01",
@@ -357,7 +357,7 @@ static struct cpuidle_state ivt_cstates[] = {
357 .exit_latency = 10, 357 .exit_latency = 10,
358 .target_residency = 80, 358 .target_residency = 80,
359 .enter = &intel_idle, 359 .enter = &intel_idle,
360 .enter_freeze = intel_idle_freeze, }, 360 .enter_s2idle = intel_idle_s2idle, },
361 { 361 {
362 .name = "C3", 362 .name = "C3",
363 .desc = "MWAIT 0x10", 363 .desc = "MWAIT 0x10",
@@ -365,7 +365,7 @@ static struct cpuidle_state ivt_cstates[] = {
365 .exit_latency = 59, 365 .exit_latency = 59,
366 .target_residency = 156, 366 .target_residency = 156,
367 .enter = &intel_idle, 367 .enter = &intel_idle,
368 .enter_freeze = intel_idle_freeze, }, 368 .enter_s2idle = intel_idle_s2idle, },
369 { 369 {
370 .name = "C6", 370 .name = "C6",
371 .desc = "MWAIT 0x20", 371 .desc = "MWAIT 0x20",
@@ -373,7 +373,7 @@ static struct cpuidle_state ivt_cstates[] = {
373 .exit_latency = 82, 373 .exit_latency = 82,
374 .target_residency = 300, 374 .target_residency = 300,
375 .enter = &intel_idle, 375 .enter = &intel_idle,
376 .enter_freeze = intel_idle_freeze, }, 376 .enter_s2idle = intel_idle_s2idle, },
377 { 377 {
378 .enter = NULL } 378 .enter = NULL }
379}; 379};
@@ -386,7 +386,7 @@ static struct cpuidle_state ivt_cstates_4s[] = {
386 .exit_latency = 1, 386 .exit_latency = 1,
387 .target_residency = 1, 387 .target_residency = 1,
388 .enter = &intel_idle, 388 .enter = &intel_idle,
389 .enter_freeze = intel_idle_freeze, }, 389 .enter_s2idle = intel_idle_s2idle, },
390 { 390 {
391 .name = "C1E", 391 .name = "C1E",
392 .desc = "MWAIT 0x01", 392 .desc = "MWAIT 0x01",
@@ -394,7 +394,7 @@ static struct cpuidle_state ivt_cstates_4s[] = {
394 .exit_latency = 10, 394 .exit_latency = 10,
395 .target_residency = 250, 395 .target_residency = 250,
396 .enter = &intel_idle, 396 .enter = &intel_idle,
397 .enter_freeze = intel_idle_freeze, }, 397 .enter_s2idle = intel_idle_s2idle, },
398 { 398 {
399 .name = "C3", 399 .name = "C3",
400 .desc = "MWAIT 0x10", 400 .desc = "MWAIT 0x10",
@@ -402,7 +402,7 @@ static struct cpuidle_state ivt_cstates_4s[] = {
402 .exit_latency = 59, 402 .exit_latency = 59,
403 .target_residency = 300, 403 .target_residency = 300,
404 .enter = &intel_idle, 404 .enter = &intel_idle,
405 .enter_freeze = intel_idle_freeze, }, 405 .enter_s2idle = intel_idle_s2idle, },
406 { 406 {
407 .name = "C6", 407 .name = "C6",
408 .desc = "MWAIT 0x20", 408 .desc = "MWAIT 0x20",
@@ -410,7 +410,7 @@ static struct cpuidle_state ivt_cstates_4s[] = {
410 .exit_latency = 84, 410 .exit_latency = 84,
411 .target_residency = 400, 411 .target_residency = 400,
412 .enter = &intel_idle, 412 .enter = &intel_idle,
413 .enter_freeze = intel_idle_freeze, }, 413 .enter_s2idle = intel_idle_s2idle, },
414 { 414 {
415 .enter = NULL } 415 .enter = NULL }
416}; 416};
@@ -423,7 +423,7 @@ static struct cpuidle_state ivt_cstates_8s[] = {
423 .exit_latency = 1, 423 .exit_latency = 1,
424 .target_residency = 1, 424 .target_residency = 1,
425 .enter = &intel_idle, 425 .enter = &intel_idle,
426 .enter_freeze = intel_idle_freeze, }, 426 .enter_s2idle = intel_idle_s2idle, },
427 { 427 {
428 .name = "C1E", 428 .name = "C1E",
429 .desc = "MWAIT 0x01", 429 .desc = "MWAIT 0x01",
@@ -431,7 +431,7 @@ static struct cpuidle_state ivt_cstates_8s[] = {
431 .exit_latency = 10, 431 .exit_latency = 10,
432 .target_residency = 500, 432 .target_residency = 500,
433 .enter = &intel_idle, 433 .enter = &intel_idle,
434 .enter_freeze = intel_idle_freeze, }, 434 .enter_s2idle = intel_idle_s2idle, },
435 { 435 {
436 .name = "C3", 436 .name = "C3",
437 .desc = "MWAIT 0x10", 437 .desc = "MWAIT 0x10",
@@ -439,7 +439,7 @@ static struct cpuidle_state ivt_cstates_8s[] = {
439 .exit_latency = 59, 439 .exit_latency = 59,
440 .target_residency = 600, 440 .target_residency = 600,
441 .enter = &intel_idle, 441 .enter = &intel_idle,
442 .enter_freeze = intel_idle_freeze, }, 442 .enter_s2idle = intel_idle_s2idle, },
443 { 443 {
444 .name = "C6", 444 .name = "C6",
445 .desc = "MWAIT 0x20", 445 .desc = "MWAIT 0x20",
@@ -447,7 +447,7 @@ static struct cpuidle_state ivt_cstates_8s[] = {
447 .exit_latency = 88, 447 .exit_latency = 88,
448 .target_residency = 700, 448 .target_residency = 700,
449 .enter = &intel_idle, 449 .enter = &intel_idle,
450 .enter_freeze = intel_idle_freeze, }, 450 .enter_s2idle = intel_idle_s2idle, },
451 { 451 {
452 .enter = NULL } 452 .enter = NULL }
453}; 453};
@@ -460,7 +460,7 @@ static struct cpuidle_state hsw_cstates[] = {
460 .exit_latency = 2, 460 .exit_latency = 2,
461 .target_residency = 2, 461 .target_residency = 2,
462 .enter = &intel_idle, 462 .enter = &intel_idle,
463 .enter_freeze = intel_idle_freeze, }, 463 .enter_s2idle = intel_idle_s2idle, },
464 { 464 {
465 .name = "C1E", 465 .name = "C1E",
466 .desc = "MWAIT 0x01", 466 .desc = "MWAIT 0x01",
@@ -468,7 +468,7 @@ static struct cpuidle_state hsw_cstates[] = {
468 .exit_latency = 10, 468 .exit_latency = 10,
469 .target_residency = 20, 469 .target_residency = 20,
470 .enter = &intel_idle, 470 .enter = &intel_idle,
471 .enter_freeze = intel_idle_freeze, }, 471 .enter_s2idle = intel_idle_s2idle, },
472 { 472 {
473 .name = "C3", 473 .name = "C3",
474 .desc = "MWAIT 0x10", 474 .desc = "MWAIT 0x10",
@@ -476,7 +476,7 @@ static struct cpuidle_state hsw_cstates[] = {
476 .exit_latency = 33, 476 .exit_latency = 33,
477 .target_residency = 100, 477 .target_residency = 100,
478 .enter = &intel_idle, 478 .enter = &intel_idle,
479 .enter_freeze = intel_idle_freeze, }, 479 .enter_s2idle = intel_idle_s2idle, },
480 { 480 {
481 .name = "C6", 481 .name = "C6",
482 .desc = "MWAIT 0x20", 482 .desc = "MWAIT 0x20",
@@ -484,7 +484,7 @@ static struct cpuidle_state hsw_cstates[] = {
484 .exit_latency = 133, 484 .exit_latency = 133,
485 .target_residency = 400, 485 .target_residency = 400,
486 .enter = &intel_idle, 486 .enter = &intel_idle,
487 .enter_freeze = intel_idle_freeze, }, 487 .enter_s2idle = intel_idle_s2idle, },
488 { 488 {
489 .name = "C7s", 489 .name = "C7s",
490 .desc = "MWAIT 0x32", 490 .desc = "MWAIT 0x32",
@@ -492,7 +492,7 @@ static struct cpuidle_state hsw_cstates[] = {
492 .exit_latency = 166, 492 .exit_latency = 166,
493 .target_residency = 500, 493 .target_residency = 500,
494 .enter = &intel_idle, 494 .enter = &intel_idle,
495 .enter_freeze = intel_idle_freeze, }, 495 .enter_s2idle = intel_idle_s2idle, },
496 { 496 {
497 .name = "C8", 497 .name = "C8",
498 .desc = "MWAIT 0x40", 498 .desc = "MWAIT 0x40",
@@ -500,7 +500,7 @@ static struct cpuidle_state hsw_cstates[] = {
500 .exit_latency = 300, 500 .exit_latency = 300,
501 .target_residency = 900, 501 .target_residency = 900,
502 .enter = &intel_idle, 502 .enter = &intel_idle,
503 .enter_freeze = intel_idle_freeze, }, 503 .enter_s2idle = intel_idle_s2idle, },
504 { 504 {
505 .name = "C9", 505 .name = "C9",
506 .desc = "MWAIT 0x50", 506 .desc = "MWAIT 0x50",
@@ -508,7 +508,7 @@ static struct cpuidle_state hsw_cstates[] = {
508 .exit_latency = 600, 508 .exit_latency = 600,
509 .target_residency = 1800, 509 .target_residency = 1800,
510 .enter = &intel_idle, 510 .enter = &intel_idle,
511 .enter_freeze = intel_idle_freeze, }, 511 .enter_s2idle = intel_idle_s2idle, },
512 { 512 {
513 .name = "C10", 513 .name = "C10",
514 .desc = "MWAIT 0x60", 514 .desc = "MWAIT 0x60",
@@ -516,7 +516,7 @@ static struct cpuidle_state hsw_cstates[] = {
516 .exit_latency = 2600, 516 .exit_latency = 2600,
517 .target_residency = 7700, 517 .target_residency = 7700,
518 .enter = &intel_idle, 518 .enter = &intel_idle,
519 .enter_freeze = intel_idle_freeze, }, 519 .enter_s2idle = intel_idle_s2idle, },
520 { 520 {
521 .enter = NULL } 521 .enter = NULL }
522}; 522};
@@ -528,7 +528,7 @@ static struct cpuidle_state bdw_cstates[] = {
528 .exit_latency = 2, 528 .exit_latency = 2,
529 .target_residency = 2, 529 .target_residency = 2,
530 .enter = &intel_idle, 530 .enter = &intel_idle,
531 .enter_freeze = intel_idle_freeze, }, 531 .enter_s2idle = intel_idle_s2idle, },
532 { 532 {
533 .name = "C1E", 533 .name = "C1E",
534 .desc = "MWAIT 0x01", 534 .desc = "MWAIT 0x01",
@@ -536,7 +536,7 @@ static struct cpuidle_state bdw_cstates[] = {
536 .exit_latency = 10, 536 .exit_latency = 10,
537 .target_residency = 20, 537 .target_residency = 20,
538 .enter = &intel_idle, 538 .enter = &intel_idle,
539 .enter_freeze = intel_idle_freeze, }, 539 .enter_s2idle = intel_idle_s2idle, },
540 { 540 {
541 .name = "C3", 541 .name = "C3",
542 .desc = "MWAIT 0x10", 542 .desc = "MWAIT 0x10",
@@ -544,7 +544,7 @@ static struct cpuidle_state bdw_cstates[] = {
544 .exit_latency = 40, 544 .exit_latency = 40,
545 .target_residency = 100, 545 .target_residency = 100,
546 .enter = &intel_idle, 546 .enter = &intel_idle,
547 .enter_freeze = intel_idle_freeze, }, 547 .enter_s2idle = intel_idle_s2idle, },
548 { 548 {
549 .name = "C6", 549 .name = "C6",
550 .desc = "MWAIT 0x20", 550 .desc = "MWAIT 0x20",
@@ -552,7 +552,7 @@ static struct cpuidle_state bdw_cstates[] = {
552 .exit_latency = 133, 552 .exit_latency = 133,
553 .target_residency = 400, 553 .target_residency = 400,
554 .enter = &intel_idle, 554 .enter = &intel_idle,
555 .enter_freeze = intel_idle_freeze, }, 555 .enter_s2idle = intel_idle_s2idle, },
556 { 556 {
557 .name = "C7s", 557 .name = "C7s",
558 .desc = "MWAIT 0x32", 558 .desc = "MWAIT 0x32",
@@ -560,7 +560,7 @@ static struct cpuidle_state bdw_cstates[] = {
560 .exit_latency = 166, 560 .exit_latency = 166,
561 .target_residency = 500, 561 .target_residency = 500,
562 .enter = &intel_idle, 562 .enter = &intel_idle,
563 .enter_freeze = intel_idle_freeze, }, 563 .enter_s2idle = intel_idle_s2idle, },
564 { 564 {
565 .name = "C8", 565 .name = "C8",
566 .desc = "MWAIT 0x40", 566 .desc = "MWAIT 0x40",
@@ -568,7 +568,7 @@ static struct cpuidle_state bdw_cstates[] = {
568 .exit_latency = 300, 568 .exit_latency = 300,
569 .target_residency = 900, 569 .target_residency = 900,
570 .enter = &intel_idle, 570 .enter = &intel_idle,
571 .enter_freeze = intel_idle_freeze, }, 571 .enter_s2idle = intel_idle_s2idle, },
572 { 572 {
573 .name = "C9", 573 .name = "C9",
574 .desc = "MWAIT 0x50", 574 .desc = "MWAIT 0x50",
@@ -576,7 +576,7 @@ static struct cpuidle_state bdw_cstates[] = {
576 .exit_latency = 600, 576 .exit_latency = 600,
577 .target_residency = 1800, 577 .target_residency = 1800,
578 .enter = &intel_idle, 578 .enter = &intel_idle,
579 .enter_freeze = intel_idle_freeze, }, 579 .enter_s2idle = intel_idle_s2idle, },
580 { 580 {
581 .name = "C10", 581 .name = "C10",
582 .desc = "MWAIT 0x60", 582 .desc = "MWAIT 0x60",
@@ -584,7 +584,7 @@ static struct cpuidle_state bdw_cstates[] = {
584 .exit_latency = 2600, 584 .exit_latency = 2600,
585 .target_residency = 7700, 585 .target_residency = 7700,
586 .enter = &intel_idle, 586 .enter = &intel_idle,
587 .enter_freeze = intel_idle_freeze, }, 587 .enter_s2idle = intel_idle_s2idle, },
588 { 588 {
589 .enter = NULL } 589 .enter = NULL }
590}; 590};
@@ -597,7 +597,7 @@ static struct cpuidle_state skl_cstates[] = {
597 .exit_latency = 2, 597 .exit_latency = 2,
598 .target_residency = 2, 598 .target_residency = 2,
599 .enter = &intel_idle, 599 .enter = &intel_idle,
600 .enter_freeze = intel_idle_freeze, }, 600 .enter_s2idle = intel_idle_s2idle, },
601 { 601 {
602 .name = "C1E", 602 .name = "C1E",
603 .desc = "MWAIT 0x01", 603 .desc = "MWAIT 0x01",
@@ -605,7 +605,7 @@ static struct cpuidle_state skl_cstates[] = {
605 .exit_latency = 10, 605 .exit_latency = 10,
606 .target_residency = 20, 606 .target_residency = 20,
607 .enter = &intel_idle, 607 .enter = &intel_idle,
608 .enter_freeze = intel_idle_freeze, }, 608 .enter_s2idle = intel_idle_s2idle, },
609 { 609 {
610 .name = "C3", 610 .name = "C3",
611 .desc = "MWAIT 0x10", 611 .desc = "MWAIT 0x10",
@@ -613,7 +613,7 @@ static struct cpuidle_state skl_cstates[] = {
613 .exit_latency = 70, 613 .exit_latency = 70,
614 .target_residency = 100, 614 .target_residency = 100,
615 .enter = &intel_idle, 615 .enter = &intel_idle,
616 .enter_freeze = intel_idle_freeze, }, 616 .enter_s2idle = intel_idle_s2idle, },
617 { 617 {
618 .name = "C6", 618 .name = "C6",
619 .desc = "MWAIT 0x20", 619 .desc = "MWAIT 0x20",
@@ -621,7 +621,7 @@ static struct cpuidle_state skl_cstates[] = {
621 .exit_latency = 85, 621 .exit_latency = 85,
622 .target_residency = 200, 622 .target_residency = 200,
623 .enter = &intel_idle, 623 .enter = &intel_idle,
624 .enter_freeze = intel_idle_freeze, }, 624 .enter_s2idle = intel_idle_s2idle, },
625 { 625 {
626 .name = "C7s", 626 .name = "C7s",
627 .desc = "MWAIT 0x33", 627 .desc = "MWAIT 0x33",
@@ -629,7 +629,7 @@ static struct cpuidle_state skl_cstates[] = {
629 .exit_latency = 124, 629 .exit_latency = 124,
630 .target_residency = 800, 630 .target_residency = 800,
631 .enter = &intel_idle, 631 .enter = &intel_idle,
632 .enter_freeze = intel_idle_freeze, }, 632 .enter_s2idle = intel_idle_s2idle, },
633 { 633 {
634 .name = "C8", 634 .name = "C8",
635 .desc = "MWAIT 0x40", 635 .desc = "MWAIT 0x40",
@@ -637,7 +637,7 @@ static struct cpuidle_state skl_cstates[] = {
637 .exit_latency = 200, 637 .exit_latency = 200,
638 .target_residency = 800, 638 .target_residency = 800,
639 .enter = &intel_idle, 639 .enter = &intel_idle,
640 .enter_freeze = intel_idle_freeze, }, 640 .enter_s2idle = intel_idle_s2idle, },
641 { 641 {
642 .name = "C9", 642 .name = "C9",
643 .desc = "MWAIT 0x50", 643 .desc = "MWAIT 0x50",
@@ -645,7 +645,7 @@ static struct cpuidle_state skl_cstates[] = {
645 .exit_latency = 480, 645 .exit_latency = 480,
646 .target_residency = 5000, 646 .target_residency = 5000,
647 .enter = &intel_idle, 647 .enter = &intel_idle,
648 .enter_freeze = intel_idle_freeze, }, 648 .enter_s2idle = intel_idle_s2idle, },
649 { 649 {
650 .name = "C10", 650 .name = "C10",
651 .desc = "MWAIT 0x60", 651 .desc = "MWAIT 0x60",
@@ -653,7 +653,7 @@ static struct cpuidle_state skl_cstates[] = {
653 .exit_latency = 890, 653 .exit_latency = 890,
654 .target_residency = 5000, 654 .target_residency = 5000,
655 .enter = &intel_idle, 655 .enter = &intel_idle,
656 .enter_freeze = intel_idle_freeze, }, 656 .enter_s2idle = intel_idle_s2idle, },
657 { 657 {
658 .enter = NULL } 658 .enter = NULL }
659}; 659};
@@ -666,7 +666,7 @@ static struct cpuidle_state skx_cstates[] = {
666 .exit_latency = 2, 666 .exit_latency = 2,
667 .target_residency = 2, 667 .target_residency = 2,
668 .enter = &intel_idle, 668 .enter = &intel_idle,
669 .enter_freeze = intel_idle_freeze, }, 669 .enter_s2idle = intel_idle_s2idle, },
670 { 670 {
671 .name = "C1E", 671 .name = "C1E",
672 .desc = "MWAIT 0x01", 672 .desc = "MWAIT 0x01",
@@ -674,7 +674,7 @@ static struct cpuidle_state skx_cstates[] = {
674 .exit_latency = 10, 674 .exit_latency = 10,
675 .target_residency = 20, 675 .target_residency = 20,
676 .enter = &intel_idle, 676 .enter = &intel_idle,
677 .enter_freeze = intel_idle_freeze, }, 677 .enter_s2idle = intel_idle_s2idle, },
678 { 678 {
679 .name = "C6", 679 .name = "C6",
680 .desc = "MWAIT 0x20", 680 .desc = "MWAIT 0x20",
@@ -682,7 +682,7 @@ static struct cpuidle_state skx_cstates[] = {
682 .exit_latency = 133, 682 .exit_latency = 133,
683 .target_residency = 600, 683 .target_residency = 600,
684 .enter = &intel_idle, 684 .enter = &intel_idle,
685 .enter_freeze = intel_idle_freeze, }, 685 .enter_s2idle = intel_idle_s2idle, },
686 { 686 {
687 .enter = NULL } 687 .enter = NULL }
688}; 688};
@@ -695,7 +695,7 @@ static struct cpuidle_state atom_cstates[] = {
695 .exit_latency = 10, 695 .exit_latency = 10,
696 .target_residency = 20, 696 .target_residency = 20,
697 .enter = &intel_idle, 697 .enter = &intel_idle,
698 .enter_freeze = intel_idle_freeze, }, 698 .enter_s2idle = intel_idle_s2idle, },
699 { 699 {
700 .name = "C2", 700 .name = "C2",
701 .desc = "MWAIT 0x10", 701 .desc = "MWAIT 0x10",
@@ -703,7 +703,7 @@ static struct cpuidle_state atom_cstates[] = {
703 .exit_latency = 20, 703 .exit_latency = 20,
704 .target_residency = 80, 704 .target_residency = 80,
705 .enter = &intel_idle, 705 .enter = &intel_idle,
706 .enter_freeze = intel_idle_freeze, }, 706 .enter_s2idle = intel_idle_s2idle, },
707 { 707 {
708 .name = "C4", 708 .name = "C4",
709 .desc = "MWAIT 0x30", 709 .desc = "MWAIT 0x30",
@@ -711,7 +711,7 @@ static struct cpuidle_state atom_cstates[] = {
711 .exit_latency = 100, 711 .exit_latency = 100,
712 .target_residency = 400, 712 .target_residency = 400,
713 .enter = &intel_idle, 713 .enter = &intel_idle,
714 .enter_freeze = intel_idle_freeze, }, 714 .enter_s2idle = intel_idle_s2idle, },
715 { 715 {
716 .name = "C6", 716 .name = "C6",
717 .desc = "MWAIT 0x52", 717 .desc = "MWAIT 0x52",
@@ -719,7 +719,7 @@ static struct cpuidle_state atom_cstates[] = {
719 .exit_latency = 140, 719 .exit_latency = 140,
720 .target_residency = 560, 720 .target_residency = 560,
721 .enter = &intel_idle, 721 .enter = &intel_idle,
722 .enter_freeze = intel_idle_freeze, }, 722 .enter_s2idle = intel_idle_s2idle, },
723 { 723 {
724 .enter = NULL } 724 .enter = NULL }
725}; 725};
@@ -731,7 +731,7 @@ static struct cpuidle_state tangier_cstates[] = {
731 .exit_latency = 1, 731 .exit_latency = 1,
732 .target_residency = 4, 732 .target_residency = 4,
733 .enter = &intel_idle, 733 .enter = &intel_idle,
734 .enter_freeze = intel_idle_freeze, }, 734 .enter_s2idle = intel_idle_s2idle, },
735 { 735 {
736 .name = "C4", 736 .name = "C4",
737 .desc = "MWAIT 0x30", 737 .desc = "MWAIT 0x30",
@@ -739,7 +739,7 @@ static struct cpuidle_state tangier_cstates[] = {
739 .exit_latency = 100, 739 .exit_latency = 100,
740 .target_residency = 400, 740 .target_residency = 400,
741 .enter = &intel_idle, 741 .enter = &intel_idle,
742 .enter_freeze = intel_idle_freeze, }, 742 .enter_s2idle = intel_idle_s2idle, },
743 { 743 {
744 .name = "C6", 744 .name = "C6",
745 .desc = "MWAIT 0x52", 745 .desc = "MWAIT 0x52",
@@ -747,7 +747,7 @@ static struct cpuidle_state tangier_cstates[] = {
747 .exit_latency = 140, 747 .exit_latency = 140,
748 .target_residency = 560, 748 .target_residency = 560,
749 .enter = &intel_idle, 749 .enter = &intel_idle,
750 .enter_freeze = intel_idle_freeze, }, 750 .enter_s2idle = intel_idle_s2idle, },
751 { 751 {
752 .name = "C7", 752 .name = "C7",
753 .desc = "MWAIT 0x60", 753 .desc = "MWAIT 0x60",
@@ -755,7 +755,7 @@ static struct cpuidle_state tangier_cstates[] = {
755 .exit_latency = 1200, 755 .exit_latency = 1200,
756 .target_residency = 4000, 756 .target_residency = 4000,
757 .enter = &intel_idle, 757 .enter = &intel_idle,
758 .enter_freeze = intel_idle_freeze, }, 758 .enter_s2idle = intel_idle_s2idle, },
759 { 759 {
760 .name = "C9", 760 .name = "C9",
761 .desc = "MWAIT 0x64", 761 .desc = "MWAIT 0x64",
@@ -763,7 +763,7 @@ static struct cpuidle_state tangier_cstates[] = {
763 .exit_latency = 10000, 763 .exit_latency = 10000,
764 .target_residency = 20000, 764 .target_residency = 20000,
765 .enter = &intel_idle, 765 .enter = &intel_idle,
766 .enter_freeze = intel_idle_freeze, }, 766 .enter_s2idle = intel_idle_s2idle, },
767 { 767 {
768 .enter = NULL } 768 .enter = NULL }
769}; 769};
@@ -775,7 +775,7 @@ static struct cpuidle_state avn_cstates[] = {
775 .exit_latency = 2, 775 .exit_latency = 2,
776 .target_residency = 2, 776 .target_residency = 2,
777 .enter = &intel_idle, 777 .enter = &intel_idle,
778 .enter_freeze = intel_idle_freeze, }, 778 .enter_s2idle = intel_idle_s2idle, },
779 { 779 {
780 .name = "C6", 780 .name = "C6",
781 .desc = "MWAIT 0x51", 781 .desc = "MWAIT 0x51",
@@ -783,7 +783,7 @@ static struct cpuidle_state avn_cstates[] = {
783 .exit_latency = 15, 783 .exit_latency = 15,
784 .target_residency = 45, 784 .target_residency = 45,
785 .enter = &intel_idle, 785 .enter = &intel_idle,
786 .enter_freeze = intel_idle_freeze, }, 786 .enter_s2idle = intel_idle_s2idle, },
787 { 787 {
788 .enter = NULL } 788 .enter = NULL }
789}; 789};
@@ -795,7 +795,7 @@ static struct cpuidle_state knl_cstates[] = {
795 .exit_latency = 1, 795 .exit_latency = 1,
796 .target_residency = 2, 796 .target_residency = 2,
797 .enter = &intel_idle, 797 .enter = &intel_idle,
798 .enter_freeze = intel_idle_freeze }, 798 .enter_s2idle = intel_idle_s2idle },
799 { 799 {
800 .name = "C6", 800 .name = "C6",
801 .desc = "MWAIT 0x10", 801 .desc = "MWAIT 0x10",
@@ -803,7 +803,7 @@ static struct cpuidle_state knl_cstates[] = {
803 .exit_latency = 120, 803 .exit_latency = 120,
804 .target_residency = 500, 804 .target_residency = 500,
805 .enter = &intel_idle, 805 .enter = &intel_idle,
806 .enter_freeze = intel_idle_freeze }, 806 .enter_s2idle = intel_idle_s2idle },
807 { 807 {
808 .enter = NULL } 808 .enter = NULL }
809}; 809};
@@ -816,7 +816,7 @@ static struct cpuidle_state bxt_cstates[] = {
816 .exit_latency = 2, 816 .exit_latency = 2,
817 .target_residency = 2, 817 .target_residency = 2,
818 .enter = &intel_idle, 818 .enter = &intel_idle,
819 .enter_freeze = intel_idle_freeze, }, 819 .enter_s2idle = intel_idle_s2idle, },
820 { 820 {
821 .name = "C1E", 821 .name = "C1E",
822 .desc = "MWAIT 0x01", 822 .desc = "MWAIT 0x01",
@@ -824,7 +824,7 @@ static struct cpuidle_state bxt_cstates[] = {
824 .exit_latency = 10, 824 .exit_latency = 10,
825 .target_residency = 20, 825 .target_residency = 20,
826 .enter = &intel_idle, 826 .enter = &intel_idle,
827 .enter_freeze = intel_idle_freeze, }, 827 .enter_s2idle = intel_idle_s2idle, },
828 { 828 {
829 .name = "C6", 829 .name = "C6",
830 .desc = "MWAIT 0x20", 830 .desc = "MWAIT 0x20",
@@ -832,7 +832,7 @@ static struct cpuidle_state bxt_cstates[] = {
832 .exit_latency = 133, 832 .exit_latency = 133,
833 .target_residency = 133, 833 .target_residency = 133,
834 .enter = &intel_idle, 834 .enter = &intel_idle,
835 .enter_freeze = intel_idle_freeze, }, 835 .enter_s2idle = intel_idle_s2idle, },
836 { 836 {
837 .name = "C7s", 837 .name = "C7s",
838 .desc = "MWAIT 0x31", 838 .desc = "MWAIT 0x31",
@@ -840,7 +840,7 @@ static struct cpuidle_state bxt_cstates[] = {
840 .exit_latency = 155, 840 .exit_latency = 155,
841 .target_residency = 155, 841 .target_residency = 155,
842 .enter = &intel_idle, 842 .enter = &intel_idle,
843 .enter_freeze = intel_idle_freeze, }, 843 .enter_s2idle = intel_idle_s2idle, },
844 { 844 {
845 .name = "C8", 845 .name = "C8",
846 .desc = "MWAIT 0x40", 846 .desc = "MWAIT 0x40",
@@ -848,7 +848,7 @@ static struct cpuidle_state bxt_cstates[] = {
848 .exit_latency = 1000, 848 .exit_latency = 1000,
849 .target_residency = 1000, 849 .target_residency = 1000,
850 .enter = &intel_idle, 850 .enter = &intel_idle,
851 .enter_freeze = intel_idle_freeze, }, 851 .enter_s2idle = intel_idle_s2idle, },
852 { 852 {
853 .name = "C9", 853 .name = "C9",
854 .desc = "MWAIT 0x50", 854 .desc = "MWAIT 0x50",
@@ -856,7 +856,7 @@ static struct cpuidle_state bxt_cstates[] = {
856 .exit_latency = 2000, 856 .exit_latency = 2000,
857 .target_residency = 2000, 857 .target_residency = 2000,
858 .enter = &intel_idle, 858 .enter = &intel_idle,
859 .enter_freeze = intel_idle_freeze, }, 859 .enter_s2idle = intel_idle_s2idle, },
860 { 860 {
861 .name = "C10", 861 .name = "C10",
862 .desc = "MWAIT 0x60", 862 .desc = "MWAIT 0x60",
@@ -864,7 +864,7 @@ static struct cpuidle_state bxt_cstates[] = {
864 .exit_latency = 10000, 864 .exit_latency = 10000,
865 .target_residency = 10000, 865 .target_residency = 10000,
866 .enter = &intel_idle, 866 .enter = &intel_idle,
867 .enter_freeze = intel_idle_freeze, }, 867 .enter_s2idle = intel_idle_s2idle, },
868 { 868 {
869 .enter = NULL } 869 .enter = NULL }
870}; 870};
@@ -877,7 +877,7 @@ static struct cpuidle_state dnv_cstates[] = {
877 .exit_latency = 2, 877 .exit_latency = 2,
878 .target_residency = 2, 878 .target_residency = 2,
879 .enter = &intel_idle, 879 .enter = &intel_idle,
880 .enter_freeze = intel_idle_freeze, }, 880 .enter_s2idle = intel_idle_s2idle, },
881 { 881 {
882 .name = "C1E", 882 .name = "C1E",
883 .desc = "MWAIT 0x01", 883 .desc = "MWAIT 0x01",
@@ -885,7 +885,7 @@ static struct cpuidle_state dnv_cstates[] = {
885 .exit_latency = 10, 885 .exit_latency = 10,
886 .target_residency = 20, 886 .target_residency = 20,
887 .enter = &intel_idle, 887 .enter = &intel_idle,
888 .enter_freeze = intel_idle_freeze, }, 888 .enter_s2idle = intel_idle_s2idle, },
889 { 889 {
890 .name = "C6", 890 .name = "C6",
891 .desc = "MWAIT 0x20", 891 .desc = "MWAIT 0x20",
@@ -893,7 +893,7 @@ static struct cpuidle_state dnv_cstates[] = {
893 .exit_latency = 50, 893 .exit_latency = 50,
894 .target_residency = 500, 894 .target_residency = 500,
895 .enter = &intel_idle, 895 .enter = &intel_idle,
896 .enter_freeze = intel_idle_freeze, }, 896 .enter_s2idle = intel_idle_s2idle, },
897 { 897 {
898 .enter = NULL } 898 .enter = NULL }
899}; 899};
@@ -936,12 +936,12 @@ static __cpuidle int intel_idle(struct cpuidle_device *dev,
936} 936}
937 937
938/** 938/**
939 * intel_idle_freeze - simplified "enter" callback routine for suspend-to-idle 939 * intel_idle_s2idle - simplified "enter" callback routine for suspend-to-idle
940 * @dev: cpuidle_device 940 * @dev: cpuidle_device
941 * @drv: cpuidle driver 941 * @drv: cpuidle driver
942 * @index: state index 942 * @index: state index
943 */ 943 */
944static void intel_idle_freeze(struct cpuidle_device *dev, 944static void intel_idle_s2idle(struct cpuidle_device *dev,
945 struct cpuidle_driver *drv, int index) 945 struct cpuidle_driver *drv, int index)
946{ 946{
947 unsigned long ecx = 1; /* break on interrupt flag */ 947 unsigned long ecx = 1; /* break on interrupt flag */
@@ -1338,7 +1338,7 @@ static void __init intel_idle_cpuidle_driver_init(void)
1338 int num_substates, mwait_hint, mwait_cstate; 1338 int num_substates, mwait_hint, mwait_cstate;
1339 1339
1340 if ((cpuidle_state_table[cstate].enter == NULL) && 1340 if ((cpuidle_state_table[cstate].enter == NULL) &&
1341 (cpuidle_state_table[cstate].enter_freeze == NULL)) 1341 (cpuidle_state_table[cstate].enter_s2idle == NULL))
1342 break; 1342 break;
1343 1343
1344 if (cstate + 1 > max_cstate) { 1344 if (cstate + 1 > max_cstate) {
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-02 07:42:42 -0400