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authorJan Glauber <jglauber@cavium.com>2016-04-11 11:28:34 -0400
committerWolfram Sang <wsa@the-dreams.de>2016-04-14 04:54:25 -0400
commit9cb9480e473b910e226312574f997bec29f47ae4 (patch)
treede67690b95f9e0a30108ae42cea94c61639cdb96 /drivers/i2c
parentf541bb382fd6b4cd60c9f1fcc2afca1d1d8ab84c (diff)
i2c: octeon: Rename [read|write]_sw to reg_[read|write]
Rename the [read|write]_sw functions to make it clearer they access the TWSI registers. Signed-off-by: Jan Glauber <jglauber@cavium.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Diffstat (limited to 'drivers/i2c')
-rw-r--r--drivers/i2c/busses/i2c-octeon.c52
1 files changed, 26 insertions, 26 deletions
diff --git a/drivers/i2c/busses/i2c-octeon.c b/drivers/i2c/busses/i2c-octeon.c
index f647667a3a47..43498a427d16 100644
--- a/drivers/i2c/busses/i2c-octeon.c
+++ b/drivers/i2c/busses/i2c-octeon.c
@@ -80,14 +80,14 @@ struct octeon_i2c {
80}; 80};
81 81
82/** 82/**
83 * octeon_i2c_write_sw - write an I2C core register 83 * octeon_i2c_reg_write - write an I2C core register
84 * @i2c: The struct octeon_i2c 84 * @i2c: The struct octeon_i2c
85 * @eop_reg: Register selector 85 * @eop_reg: Register selector
86 * @data: Value to be written 86 * @data: Value to be written
87 * 87 *
88 * The I2C core registers are accessed indirectly via the SW_TWSI CSR. 88 * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
89 */ 89 */
90static void octeon_i2c_write_sw(struct octeon_i2c *i2c, u64 eop_reg, u8 data) 90static void octeon_i2c_reg_write(struct octeon_i2c *i2c, u64 eop_reg, u8 data)
91{ 91{
92 u64 tmp; 92 u64 tmp;
93 93
@@ -98,7 +98,7 @@ static void octeon_i2c_write_sw(struct octeon_i2c *i2c, u64 eop_reg, u8 data)
98} 98}
99 99
100/** 100/**
101 * octeon_i2c_read_sw - read lower bits of an I2C core register 101 * octeon_i2c_reg_read - read lower bits of an I2C core register
102 * @i2c: The struct octeon_i2c 102 * @i2c: The struct octeon_i2c
103 * @eop_reg: Register selector 103 * @eop_reg: Register selector
104 * 104 *
@@ -106,7 +106,7 @@ static void octeon_i2c_write_sw(struct octeon_i2c *i2c, u64 eop_reg, u8 data)
106 * 106 *
107 * The I2C core registers are accessed indirectly via the SW_TWSI CSR. 107 * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
108 */ 108 */
109static u8 octeon_i2c_read_sw(struct octeon_i2c *i2c, u64 eop_reg) 109static u8 octeon_i2c_reg_read(struct octeon_i2c *i2c, u64 eop_reg)
110{ 110{
111 u64 tmp; 111 u64 tmp;
112 112
@@ -189,7 +189,7 @@ static irqreturn_t octeon_i2c_isr(int irq, void *dev_id)
189 189
190static int octeon_i2c_test_iflg(struct octeon_i2c *i2c) 190static int octeon_i2c_test_iflg(struct octeon_i2c *i2c)
191{ 191{
192 return (octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_CTL) & TWSI_CTL_IFLG) != 0; 192 return (octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_CTL) & TWSI_CTL_IFLG) != 0;
193} 193}
194 194
195/** 195/**
@@ -252,8 +252,8 @@ static void octeon_i2c_set_clock(struct octeon_i2c *i2c)
252 } 252 }
253 } 253 }
254 } 254 }
255 octeon_i2c_write_sw(i2c, SW_TWSI_OP_TWSI_CLK, thp); 255 octeon_i2c_reg_write(i2c, SW_TWSI_OP_TWSI_CLK, thp);
256 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv); 256 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv);
257} 257}
258 258
259static int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c) 259static int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c)
@@ -262,14 +262,14 @@ static int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c)
262 int tries; 262 int tries;
263 263
264 /* disable high level controller, enable bus access */ 264 /* disable high level controller, enable bus access */
265 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB); 265 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
266 266
267 /* reset controller */ 267 /* reset controller */
268 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_RST, 0); 268 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_RST, 0);
269 269
270 for (tries = 10; tries; tries--) { 270 for (tries = 10; tries; tries--) {
271 udelay(1); 271 udelay(1);
272 status = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT); 272 status = octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT);
273 if (status == STAT_IDLE) 273 if (status == STAT_IDLE)
274 return 0; 274 return 0;
275 } 275 }
@@ -288,19 +288,19 @@ static int octeon_i2c_start(struct octeon_i2c *i2c)
288 int result; 288 int result;
289 u8 data; 289 u8 data;
290 290
291 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, 291 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL,
292 TWSI_CTL_ENAB | TWSI_CTL_STA); 292 TWSI_CTL_ENAB | TWSI_CTL_STA);
293 293
294 result = octeon_i2c_wait(i2c); 294 result = octeon_i2c_wait(i2c);
295 if (result) { 295 if (result) {
296 if (octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT) == STAT_IDLE) { 296 if (octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT) == STAT_IDLE) {
297 /* 297 /*
298 * Controller refused to send start flag May 298 * Controller refused to send start flag May
299 * be a client is holding SDA low - let's try 299 * be a client is holding SDA low - let's try
300 * to free it. 300 * to free it.
301 */ 301 */
302 octeon_i2c_unblock(i2c); 302 octeon_i2c_unblock(i2c);
303 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, 303 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL,
304 TWSI_CTL_ENAB | TWSI_CTL_STA); 304 TWSI_CTL_ENAB | TWSI_CTL_STA);
305 result = octeon_i2c_wait(i2c); 305 result = octeon_i2c_wait(i2c);
306 } 306 }
@@ -308,7 +308,7 @@ static int octeon_i2c_start(struct octeon_i2c *i2c)
308 return result; 308 return result;
309 } 309 }
310 310
311 data = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT); 311 data = octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT);
312 if ((data != STAT_START) && (data != STAT_RSTART)) { 312 if ((data != STAT_START) && (data != STAT_RSTART)) {
313 dev_err(i2c->dev, "%s: bad status (0x%x)\n", __func__, data); 313 dev_err(i2c->dev, "%s: bad status (0x%x)\n", __func__, data);
314 return -EIO; 314 return -EIO;
@@ -320,7 +320,7 @@ static int octeon_i2c_start(struct octeon_i2c *i2c)
320/* send STOP to the bus */ 320/* send STOP to the bus */
321static void octeon_i2c_stop(struct octeon_i2c *i2c) 321static void octeon_i2c_stop(struct octeon_i2c *i2c)
322{ 322{
323 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, 323 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL,
324 TWSI_CTL_ENAB | TWSI_CTL_STP); 324 TWSI_CTL_ENAB | TWSI_CTL_STP);
325} 325}
326 326
@@ -345,15 +345,15 @@ static int octeon_i2c_write(struct octeon_i2c *i2c, int target,
345 if (result) 345 if (result)
346 return result; 346 return result;
347 347
348 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, target << 1); 348 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_DATA, target << 1);
349 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB); 349 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
350 350
351 result = octeon_i2c_wait(i2c); 351 result = octeon_i2c_wait(i2c);
352 if (result) 352 if (result)
353 return result; 353 return result;
354 354
355 for (i = 0; i < length; i++) { 355 for (i = 0; i < length; i++) {
356 tmp = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT); 356 tmp = octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT);
357 357
358 if ((tmp != STAT_TXADDR_ACK) && (tmp != STAT_TXDATA_ACK)) { 358 if ((tmp != STAT_TXADDR_ACK) && (tmp != STAT_TXDATA_ACK)) {
359 dev_err(i2c->dev, 359 dev_err(i2c->dev,
@@ -362,8 +362,8 @@ static int octeon_i2c_write(struct octeon_i2c *i2c, int target,
362 return -EIO; 362 return -EIO;
363 } 363 }
364 364
365 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, data[i]); 365 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_DATA, data[i]);
366 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB); 366 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
367 367
368 result = octeon_i2c_wait(i2c); 368 result = octeon_i2c_wait(i2c);
369 if (result) 369 if (result)
@@ -398,15 +398,15 @@ static int octeon_i2c_read(struct octeon_i2c *i2c, int target,
398 if (result) 398 if (result)
399 return result; 399 return result;
400 400
401 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, (target << 1) | 1); 401 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_DATA, (target << 1) | 1);
402 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB); 402 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
403 403
404 result = octeon_i2c_wait(i2c); 404 result = octeon_i2c_wait(i2c);
405 if (result) 405 if (result)
406 return result; 406 return result;
407 407
408 for (i = 0; i < length; i++) { 408 for (i = 0; i < length; i++) {
409 tmp = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT); 409 tmp = octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT);
410 410
411 if ((tmp != STAT_RXDATA_ACK) && (tmp != STAT_RXADDR_ACK)) { 411 if ((tmp != STAT_RXDATA_ACK) && (tmp != STAT_RXADDR_ACK)) {
412 dev_err(i2c->dev, 412 dev_err(i2c->dev,
@@ -416,17 +416,17 @@ static int octeon_i2c_read(struct octeon_i2c *i2c, int target,
416 } 416 }
417 417
418 if (i + 1 < length) 418 if (i + 1 < length)
419 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, 419 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL,
420 TWSI_CTL_ENAB | TWSI_CTL_AAK); 420 TWSI_CTL_ENAB | TWSI_CTL_AAK);
421 else 421 else
422 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, 422 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL,
423 TWSI_CTL_ENAB); 423 TWSI_CTL_ENAB);
424 424
425 result = octeon_i2c_wait(i2c); 425 result = octeon_i2c_wait(i2c);
426 if (result) 426 if (result)
427 return result; 427 return result;
428 428
429 data[i] = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_DATA); 429 data[i] = octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_DATA);
430 if (recv_len && i == 0) { 430 if (recv_len && i == 0) {
431 if (data[i] > I2C_SMBUS_BLOCK_MAX + 1) { 431 if (data[i] > I2C_SMBUS_BLOCK_MAX + 1) {
432 dev_err(i2c->dev, 432 dev_err(i2c->dev,
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-22 07:55:51 -0400