diff options
| author | Wolfram Sang <wsa+renesas@sang-engineering.com> | 2019-02-05 08:37:25 -0500 |
|---|---|---|
| committer | Wolfram Sang <wsa@the-dreams.de> | 2019-02-08 16:30:46 -0500 |
| commit | 18769445ca55c2277d29e35ffda7e9a206b1758f (patch) | |
| tree | e03145351230eb7f48733731600e91f90666c7b5 /drivers/i2c | |
| parent | 60c1d5605b67218cc600588af59260c0d1144495 (diff) | |
i2c: rcar: refactor TCYC handling
The latest documentation made it clear that we need to initialize the
TCYC value independently of DMA. The old code used TCYC06 (wrongly) for
non-DMA transfers. The new code sets TCYC up independently from DMA.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Diffstat (limited to 'drivers/i2c')
| -rw-r--r-- | drivers/i2c/busses/i2c-rcar.c | 15 |
1 files changed, 6 insertions, 9 deletions
diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c index 498ba4b87833..dd52a068b140 100644 --- a/drivers/i2c/busses/i2c-rcar.c +++ b/drivers/i2c/busses/i2c-rcar.c | |||
| @@ -39,8 +39,8 @@ | |||
| 39 | #define ICSAR 0x1C /* slave address */ | 39 | #define ICSAR 0x1C /* slave address */ |
| 40 | #define ICMAR 0x20 /* master address */ | 40 | #define ICMAR 0x20 /* master address */ |
| 41 | #define ICRXTX 0x24 /* data port */ | 41 | #define ICRXTX 0x24 /* data port */ |
| 42 | #define ICDMAER 0x3c /* DMA enable */ | 42 | #define ICFBSCR 0x38 /* first bit setup cycle (Gen3) */ |
| 43 | #define ICFBSCR 0x38 /* first bit setup cycle */ | 43 | #define ICDMAER 0x3c /* DMA enable (Gen3) */ |
| 44 | 44 | ||
| 45 | /* ICSCR */ | 45 | /* ICSCR */ |
| 46 | #define SDBS (1 << 3) /* slave data buffer select */ | 46 | #define SDBS (1 << 3) /* slave data buffer select */ |
| @@ -83,7 +83,6 @@ | |||
| 83 | #define TMDMAE (1 << 0) /* DMA Master Transmitted Enable */ | 83 | #define TMDMAE (1 << 0) /* DMA Master Transmitted Enable */ |
| 84 | 84 | ||
| 85 | /* ICFBSCR */ | 85 | /* ICFBSCR */ |
| 86 | #define TCYC06 0x04 /* 6*Tcyc delay 1st bit between SDA and SCL */ | ||
| 87 | #define TCYC17 0x0f /* 17*Tcyc delay 1st bit between SDA and SCL */ | 86 | #define TCYC17 0x0f /* 17*Tcyc delay 1st bit between SDA and SCL */ |
| 88 | 87 | ||
| 89 | 88 | ||
| @@ -212,6 +211,10 @@ static void rcar_i2c_init(struct rcar_i2c_priv *priv) | |||
| 212 | rcar_i2c_write(priv, ICMSR, 0); | 211 | rcar_i2c_write(priv, ICMSR, 0); |
| 213 | /* start clock */ | 212 | /* start clock */ |
| 214 | rcar_i2c_write(priv, ICCCR, priv->icccr); | 213 | rcar_i2c_write(priv, ICCCR, priv->icccr); |
| 214 | |||
| 215 | if (priv->devtype == I2C_RCAR_GEN3) | ||
| 216 | rcar_i2c_write(priv, ICFBSCR, TCYC17); | ||
| 217 | |||
| 215 | } | 218 | } |
| 216 | 219 | ||
| 217 | static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv) | 220 | static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv) |
| @@ -363,9 +366,6 @@ static void rcar_i2c_dma_unmap(struct rcar_i2c_priv *priv) | |||
| 363 | /* Disable DMA Master Received/Transmitted */ | 366 | /* Disable DMA Master Received/Transmitted */ |
| 364 | rcar_i2c_write(priv, ICDMAER, 0); | 367 | rcar_i2c_write(priv, ICDMAER, 0); |
| 365 | 368 | ||
| 366 | /* Reset default delay */ | ||
| 367 | rcar_i2c_write(priv, ICFBSCR, TCYC06); | ||
| 368 | |||
| 369 | dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg), | 369 | dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg), |
| 370 | sg_dma_len(&priv->sg), priv->dma_direction); | 370 | sg_dma_len(&priv->sg), priv->dma_direction); |
| 371 | 371 | ||
| @@ -461,9 +461,6 @@ static void rcar_i2c_dma(struct rcar_i2c_priv *priv) | |||
| 461 | return; | 461 | return; |
| 462 | } | 462 | } |
| 463 | 463 | ||
| 464 | /* Set delay for DMA operations */ | ||
| 465 | rcar_i2c_write(priv, ICFBSCR, TCYC17); | ||
| 466 | |||
| 467 | /* Enable DMA Master Received/Transmitted */ | 464 | /* Enable DMA Master Received/Transmitted */ |
| 468 | if (read) | 465 | if (read) |
| 469 | rcar_i2c_write(priv, ICDMAER, RMDMAE); | 466 | rcar_i2c_write(priv, ICDMAER, RMDMAE); |
