Merge tag 'v4.6-rc6' into locking/core, to pick up fixes

Signed-off-by: Ingo Molnar <mingo@kernel.org>

83 files changed, 920 insertions, 354 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index c4a21c6428f5..1bcbade479dc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1591,6 +1591,8 @@ struct amdgpu_uvd {
         struct amdgpu_bo        *vcpu_bo;
         void                    *cpu_addr;
         uint64_t                gpu_addr;
+        unsigned                fw_version;
+        void                    *saved_bo;
         atomic_t                handles[AMDGPU_MAX_UVD_HANDLES];
         struct drm_file         *filp[AMDGPU_MAX_UVD_HANDLES];
         struct delayed_work     idle_work;
@@ -2033,6 +2035,7 @@ struct amdgpu_device {
 
         /* tracking pinned memory */
         u64 vram_pin_size;
+        u64 invisible_pin_size;
         u64 gart_pin_size;
 
         /* amdkfd interface */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index d6b0bff510aa..b7b583c42ea8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -425,6 +425,10 @@ static int acp_resume(void *handle)
         struct acp_pm_domain *apd;
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
+        /* return early if no ACP */
+        if (!adev->acp.acp_genpd)
+                return 0;
+
         /* SMU block will power on ACP irrespective of ACP runtime status.
          * Power off explicitly based on genpd ACP runtime status so that ACP
          * hw and ACP-genpd status are in sync.
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
index 0020a0ea43ff..35a1248aaa77 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
@@ -63,10 +63,6 @@ bool amdgpu_has_atpx(void) {
         return amdgpu_atpx_priv.atpx_detected;
 }
 
-bool amdgpu_has_atpx_dgpu_power_cntl(void) {
-        return amdgpu_atpx_priv.atpx.functions.power_cntl;
-}
-
 /**
  * amdgpu_atpx_call - call an ATPX method
  *
@@ -146,6 +142,13 @@ static void amdgpu_atpx_parse_functions(struct amdgpu_atpx_functions *f, u32 mas
  */
 static int amdgpu_atpx_validate(struct amdgpu_atpx *atpx)
 {
+        /* make sure required functions are enabled */
+        /* dGPU power control is required */
+        if (atpx->functions.power_cntl == false) {
+                printk("ATPX dGPU power cntl not present, forcing\n");
+                atpx->functions.power_cntl = true;
+        }
+
         if (atpx->functions.px_params) {
                 union acpi_object *info;
                 struct atpx_px_params output;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index 7a4b101e10c6..6043dc7c3a94 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -816,10 +816,13 @@ static int amdgpu_cgs_get_active_displays_info(void *cgs_device,
         struct drm_device *ddev = adev->ddev;
         struct drm_crtc *crtc;
         uint32_t line_time_us, vblank_lines;
+        struct cgs_mode_info *mode_info;
 
         if (info == NULL)
                 return -EINVAL;
 
+        mode_info = info->mode_info;
+
         if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
                 list_for_each_entry(crtc,
                                 &ddev->mode_config.crtc_list, head) {
@@ -828,7 +831,7 @@ static int amdgpu_cgs_get_active_displays_info(void *cgs_device,
                                 info->active_display_mask |= (1 << amdgpu_crtc->crtc_id);
                                 info->display_count++;
                         }
-                        if (info->mode_info != NULL &&
+                        if (mode_info != NULL &&
                                 crtc->enabled && amdgpu_crtc->enabled &&
                                 amdgpu_crtc->hw_mode.clock) {
                                 line_time_us = (amdgpu_crtc->hw_mode.crtc_htotal * 1000) /
@@ -836,10 +839,10 @@ static int amdgpu_cgs_get_active_displays_info(void *cgs_device,
                                 vblank_lines = amdgpu_crtc->hw_mode.crtc_vblank_end -
                                                         amdgpu_crtc->hw_mode.crtc_vdisplay +
                                                         (amdgpu_crtc->v_border * 2);
-                                info->mode_info->vblank_time_us = vblank_lines * line_time_us;
-                                info->mode_info->refresh_rate = drm_mode_vrefresh(&amdgpu_crtc->hw_mode);
-                                info->mode_info->ref_clock = adev->clock.spll.reference_freq;
-                                info->mode_info++;
+                                mode_info->vblank_time_us = vblank_lines * line_time_us;
+                                mode_info->refresh_rate = drm_mode_vrefresh(&amdgpu_crtc->hw_mode);
+                                mode_info->ref_clock = adev->clock.spll.reference_freq;
+                                mode_info = NULL;
                         }
                 }
         }
@@ -847,6 +850,16 @@ static int amdgpu_cgs_get_active_displays_info(void *cgs_device,
         return 0;
 }
 
+
+static int amdgpu_cgs_notify_dpm_enabled(void *cgs_device, bool enabled)
+{
+        CGS_FUNC_ADEV;
+
+        adev->pm.dpm_enabled = enabled;
+
+        return 0;
+}
+
 /** \brief evaluate acpi namespace object, handle or pathname must be valid
  *  \param cgs_device
  *  \param info input/output arguments for the control method
@@ -1097,6 +1110,7 @@ static const struct cgs_ops amdgpu_cgs_ops = {
         amdgpu_cgs_set_powergating_state,
         amdgpu_cgs_set_clockgating_state,
         amdgpu_cgs_get_active_displays_info,
+        amdgpu_cgs_notify_dpm_enabled,
         amdgpu_cgs_call_acpi_method,
         amdgpu_cgs_query_system_info,
 };
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 612117478b57..2139da773da6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -62,12 +62,6 @@ static const char *amdgpu_asic_name[] = {
         "LAST",
 };
 
-#if defined(CONFIG_VGA_SWITCHEROO)
-bool amdgpu_has_atpx_dgpu_power_cntl(void);
-#else
-static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
-#endif
-
 bool amdgpu_device_is_px(struct drm_device *dev)
 {
         struct amdgpu_device *adev = dev->dev_private;
@@ -1485,7 +1479,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
 
         if (amdgpu_runtime_pm == 1)
                 runtime = true;
-        if (amdgpu_device_is_px(ddev) && amdgpu_has_atpx_dgpu_power_cntl())
+        if (amdgpu_device_is_px(ddev))
                 runtime = true;
         vga_switcheroo_register_client(adev->pdev, &amdgpu_switcheroo_ops, runtime);
         if (runtime)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index f0ed974bd4e0..3fb405b3a614 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -57,7 +57,7 @@ static bool amdgpu_flip_handle_fence(struct amdgpu_flip_work *work,
         if (!fence_add_callback(fence, &work->cb, amdgpu_flip_callback))
                 return true;
 
-        fence_put(*f);
+        fence_put(fence);
         return false;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index 4303b447efe8..d81f1f4883a6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -121,7 +121,7 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **f)
 {
         struct amdgpu_device *adev = ring->adev;
         struct amdgpu_fence *fence;
-        struct fence **ptr;
+        struct fence *old, **ptr;
         uint32_t seq;
 
         fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL);
@@ -141,7 +141,11 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **f)
         /* This function can't be called concurrently anyway, otherwise
          * emitting the fence would mess up the hardware ring buffer.
          */
-        BUG_ON(rcu_dereference_protected(*ptr, 1));
+        old = rcu_dereference_protected(*ptr, 1);
+        if (old && !fence_is_signaled(old)) {
+                DRM_INFO("rcu slot is busy\n");
+                fence_wait(old, false);
+        }
 
         rcu_assign_pointer(*ptr, fence_get(&fence->base));
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index f594cfaa97e5..762cfdb85147 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -219,6 +219,8 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
         if (r) {
                 return r;
         }
+        adev->ddev->vblank_disable_allowed = true;
+
         /* enable msi */
         adev->irq.msi_enabled = false;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 7805a8706af7..b04337de65d1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -303,7 +303,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
                         fw_info.feature = adev->vce.fb_version;
                         break;
                 case AMDGPU_INFO_FW_UVD:
-                        fw_info.ver = 0;
+                        fw_info.ver = adev->uvd.fw_version;
                         fw_info.feature = 0;
                         break;
                 case AMDGPU_INFO_FW_GMC:
@@ -382,8 +382,9 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
                 struct drm_amdgpu_info_vram_gtt vram_gtt;
 
                 vram_gtt.vram_size = adev->mc.real_vram_size;
+                vram_gtt.vram_size -= adev->vram_pin_size;
                 vram_gtt.vram_cpu_accessible_size = adev->mc.visible_vram_size;
-                vram_gtt.vram_cpu_accessible_size -= adev->vram_pin_size;
+                vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - adev->invisible_pin_size);
                 vram_gtt.gtt_size  = adev->mc.gtt_size;
                 vram_gtt.gtt_size -= adev->gart_pin_size;
                 return copy_to_user(out, &vram_gtt,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
index 8d432e6901af..81bd964d3dfc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
@@ -53,7 +53,7 @@ struct amdgpu_hpd;
 
 #define AMDGPU_MAX_HPD_PINS 6
 #define AMDGPU_MAX_CRTCS 6
-#define AMDGPU_MAX_AFMT_BLOCKS 7
+#define AMDGPU_MAX_AFMT_BLOCKS 9
 
 enum amdgpu_rmx_type {
         RMX_OFF,
@@ -309,8 +309,8 @@ struct amdgpu_mode_info {
         struct atom_context *atom_context;
         struct card_info *atom_card_info;
         bool mode_config_initialized;
-        struct amdgpu_crtc *crtcs[6];
-        struct amdgpu_afmt *afmt[7];
+        struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS];
+        struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS];
         /* DVI-I properties */
         struct drm_property *coherent_mode_property;
         /* DAC enable load detect */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 56d1458393cc..e557fc1f17c8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -424,9 +424,11 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
                 bo->pin_count = 1;
                 if (gpu_addr != NULL)
                         *gpu_addr = amdgpu_bo_gpu_offset(bo);
-                if (domain == AMDGPU_GEM_DOMAIN_VRAM)
+                if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
                         bo->adev->vram_pin_size += amdgpu_bo_size(bo);
-                else
+                        if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
+                                bo->adev->invisible_pin_size += amdgpu_bo_size(bo);
+                } else
                         bo->adev->gart_pin_size += amdgpu_bo_size(bo);
         } else {
                 dev_err(bo->adev->dev, "%p pin failed\n", bo);
@@ -456,9 +458,11 @@ int amdgpu_bo_unpin(struct amdgpu_bo *bo)
         }
         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
         if (likely(r == 0)) {
-                if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
+                if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {
                         bo->adev->vram_pin_size -= amdgpu_bo_size(bo);
-                else
+                        if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
+                                bo->adev->invisible_pin_size -= amdgpu_bo_size(bo);
+                } else
                         bo->adev->gart_pin_size -= amdgpu_bo_size(bo);
         } else {
                 dev_err(bo->adev->dev, "%p validate failed for unpin\n", bo);
@@ -476,6 +480,17 @@ int amdgpu_bo_evict_vram(struct amdgpu_device *adev)
         return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM);
 }
 
+static const char *amdgpu_vram_names[] = {
+        "UNKNOWN",
+        "GDDR1",
+        "DDR2",
+        "GDDR3",
+        "GDDR4",
+        "GDDR5",
+        "HBM",
+        "DDR3"
+};
+
 int amdgpu_bo_init(struct amdgpu_device *adev)
 {
         /* Add an MTRR for the VRAM */
@@ -484,8 +499,8 @@ int amdgpu_bo_init(struct amdgpu_device *adev)
         DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
                 adev->mc.mc_vram_size >> 20,
                 (unsigned long long)adev->mc.aper_size >> 20);
-        DRM_INFO("RAM width %dbits DDR\n",
-                        adev->mc.vram_width);
+        DRM_INFO("RAM width %dbits %s\n",
+                 adev->mc.vram_width, amdgpu_vram_names[adev->mc.vram_type]);
         return amdgpu_ttm_init(adev);
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
index 3cb6d6c413c7..e9c6ae6ed2f7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
@@ -143,7 +143,7 @@ static int amdgpu_pp_late_init(void *handle)
                                         adev->powerplay.pp_handle);
 
 #ifdef CONFIG_DRM_AMD_POWERPLAY
-        if (adev->pp_enabled) {
+        if (adev->pp_enabled && adev->pm.dpm_enabled) {
                 amdgpu_pm_sysfs_init(adev);
                 amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_COMPLETE_INIT, NULL, NULL);
         }
@@ -161,12 +161,8 @@ static int amdgpu_pp_sw_init(void *handle)
                                         adev->powerplay.pp_handle);
 
 #ifdef CONFIG_DRM_AMD_POWERPLAY
-        if (adev->pp_enabled) {
-                if (amdgpu_dpm == 0)
-                        adev->pm.dpm_enabled = false;
-                else
-                        adev->pm.dpm_enabled = true;
-        }
+        if (adev->pp_enabled)
+                adev->pm.dpm_enabled = true;
 #endif
 
         return ret;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index f1a55d1888cb..11af4492b4be 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -223,6 +223,8 @@ static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 {
         struct amdgpu_bo *rbo = container_of(bo, struct amdgpu_bo, tbo);
 
+        if (amdgpu_ttm_tt_get_usermm(bo->ttm))
+                return -EPERM;
         return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp);
 }
 
@@ -622,7 +624,7 @@ static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
                         set_page_dirty(page);
 
                 mark_page_accessed(page);
-                page_cache_release(page);
+                put_page(page);
         }
 
         sg_free_table(ttm->sg);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index c1a581044417..871018c634e0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -158,6 +158,9 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
         DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n",
                 version_major, version_minor, family_id);
 
+        adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) |
+                                (family_id << 8));
+
         bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)
                  +  AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE;
         r = amdgpu_bo_create(adev, bo_size, PAGE_SIZE, true,
@@ -241,32 +244,30 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
 
 int amdgpu_uvd_suspend(struct amdgpu_device *adev)
 {
-        struct amdgpu_ring *ring = &adev->uvd.ring;
-        int i, r;
+        unsigned size;
+        void *ptr;
+        int i;
 
         if (adev->uvd.vcpu_bo == NULL)
                 return 0;
 
-        for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
-                uint32_t handle = atomic_read(&adev->uvd.handles[i]);
-                if (handle != 0) {
-                        struct fence *fence;
+        for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i)
+                if (atomic_read(&adev->uvd.handles[i]))
+                        break;
 
-                        amdgpu_uvd_note_usage(adev);
+        if (i == AMDGPU_MAX_UVD_HANDLES)
+                return 0;
 
-                        r = amdgpu_uvd_get_destroy_msg(ring, handle, false, &fence);
-                        if (r) {
-                                DRM_ERROR("Error destroying UVD (%d)!\n", r);
-                                continue;
-                        }
+        cancel_delayed_work_sync(&adev->uvd.idle_work);
 
-                        fence_wait(fence, false);
-                        fence_put(fence);
+        size = amdgpu_bo_size(adev->uvd.vcpu_bo);
+        ptr = adev->uvd.cpu_addr;
 
-                        adev->uvd.filp[i] = NULL;
-                        atomic_set(&adev->uvd.handles[i], 0);
-                }
-        }
+        adev->uvd.saved_bo = kmalloc(size, GFP_KERNEL);
+        if (!adev->uvd.saved_bo)
+                return -ENOMEM;
+
+        memcpy(adev->uvd.saved_bo, ptr, size);
 
         return 0;
 }
@@ -275,23 +276,29 @@ int amdgpu_uvd_resume(struct amdgpu_device *adev)
 {
         unsigned size;
         void *ptr;
-        const struct common_firmware_header *hdr;
-        unsigned offset;
 
         if (adev->uvd.vcpu_bo == NULL)
                 return -EINVAL;
 
-        hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
-        offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
-        memcpy(adev->uvd.cpu_addr, (adev->uvd.fw->data) + offset,
-                (adev->uvd.fw->size) - offset);
-
         size = amdgpu_bo_size(adev->uvd.vcpu_bo);
-        size -= le32_to_cpu(hdr->ucode_size_bytes);
         ptr = adev->uvd.cpu_addr;
-        ptr += le32_to_cpu(hdr->ucode_size_bytes);
 
-        memset(ptr, 0, size);
+        if (adev->uvd.saved_bo != NULL) {
+                memcpy(ptr, adev->uvd.saved_bo, size);
+                kfree(adev->uvd.saved_bo);
+                adev->uvd.saved_bo = NULL;
+        } else {
+                const struct common_firmware_header *hdr;
+                unsigned offset;
+
+                hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
+                offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
+                memcpy(adev->uvd.cpu_addr, (adev->uvd.fw->data) + offset,
+                        (adev->uvd.fw->size) - offset);
+                size -= le32_to_cpu(hdr->ucode_size_bytes);
+                ptr += le32_to_cpu(hdr->ucode_size_bytes);
+                memset(ptr, 0, size);
+        }
 
         return 0;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index 4bec0c108cea..481a64fa9b47 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -234,6 +234,7 @@ int amdgpu_vce_suspend(struct amdgpu_device *adev)
         if (i == AMDGPU_MAX_VCE_HANDLES)
                 return 0;
 
+        cancel_delayed_work_sync(&adev->vce.idle_work);
         /* TODO: suspending running encoding sessions isn't supported */
         return -EINVAL;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 82ce7d943884..a4a2e6cc61bb 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -903,14 +903,6 @@ static int gmc_v7_0_early_init(void *handle)
         gmc_v7_0_set_gart_funcs(adev);
         gmc_v7_0_set_irq_funcs(adev);
 
-        if (adev->flags & AMD_IS_APU) {
-                adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
-        } else {
-                u32 tmp = RREG32(mmMC_SEQ_MISC0);
-                tmp &= MC_SEQ_MISC0__MT__MASK;
-                adev->mc.vram_type = gmc_v7_0_convert_vram_type(tmp);
-        }
-
         return 0;
 }
 
@@ -918,7 +910,10 @@ static int gmc_v7_0_late_init(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-        return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
+        if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
+                return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
+        else
+                return 0;
 }
 
 static int gmc_v7_0_sw_init(void *handle)
@@ -927,6 +922,14 @@ static int gmc_v7_0_sw_init(void *handle)
         int dma_bits;
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
+        if (adev->flags & AMD_IS_APU) {
+                adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
+        } else {
+                u32 tmp = RREG32(mmMC_SEQ_MISC0);
+                tmp &= MC_SEQ_MISC0__MT__MASK;
+                adev->mc.vram_type = gmc_v7_0_convert_vram_type(tmp);
+        }
+
         r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
         if (r)
                 return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 29bd7b57dc91..7a9db2c72c89 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -863,14 +863,6 @@ static int gmc_v8_0_early_init(void *handle)
         gmc_v8_0_set_gart_funcs(adev);
         gmc_v8_0_set_irq_funcs(adev);
 
-        if (adev->flags & AMD_IS_APU) {
-                adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
-        } else {
-                u32 tmp = RREG32(mmMC_SEQ_MISC0);
-                tmp &= MC_SEQ_MISC0__MT__MASK;
-                adev->mc.vram_type = gmc_v8_0_convert_vram_type(tmp);
-        }
-
         return 0;
 }
 
@@ -878,15 +870,33 @@ static int gmc_v8_0_late_init(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-        return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
+        if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
+                return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
+        else
+                return 0;
 }
 
+#define mmMC_SEQ_MISC0_FIJI 0xA71
+
 static int gmc_v8_0_sw_init(void *handle)
 {
         int r;
         int dma_bits;
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
+        if (adev->flags & AMD_IS_APU) {
+                adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
+        } else {
+                u32 tmp;
+
+                if (adev->asic_type == CHIP_FIJI)
+                        tmp = RREG32(mmMC_SEQ_MISC0_FIJI);
+                else
+                        tmp = RREG32(mmMC_SEQ_MISC0);
+                tmp &= MC_SEQ_MISC0__MT__MASK;
+                adev->mc.vram_type = gmc_v8_0_convert_vram_type(tmp);
+        }
+
         r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
         if (r)
                 return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
index b6f7d7bff929..0f14199cf716 100644
--- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
@@ -307,7 +307,7 @@ static int tonga_ih_sw_fini(void *handle)
 
         amdgpu_irq_fini(adev);
         amdgpu_ih_ring_fini(adev);
-        amdgpu_irq_add_domain(adev);
+        amdgpu_irq_remove_domain(adev);
 
         return 0;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
index c606ccb38d8b..cb463753115b 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
@@ -224,11 +224,11 @@ static int uvd_v4_2_suspend(void *handle)
         int r;
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-        r = amdgpu_uvd_suspend(adev);
+        r = uvd_v4_2_hw_fini(adev);
         if (r)
                 return r;
 
-        r = uvd_v4_2_hw_fini(adev);
+        r = amdgpu_uvd_suspend(adev);
         if (r)
                 return r;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
index e3c852d9d79a..16476d80f475 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
@@ -220,11 +220,11 @@ static int uvd_v5_0_suspend(void *handle)
         int r;
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-        r = amdgpu_uvd_suspend(adev);
+        r = uvd_v5_0_hw_fini(adev);
         if (r)
                 return r;
 
-        r = uvd_v5_0_hw_fini(adev);
+        r = amdgpu_uvd_suspend(adev);
         if (r)
                 return r;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 3375e614ac67..d49379145ef2 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -214,15 +214,16 @@ static int uvd_v6_0_suspend(void *handle)
         int r;
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
+        r = uvd_v6_0_hw_fini(adev);
+        if (r)
+                return r;
+
         /* Skip this for APU for now */
         if (!(adev->flags & AMD_IS_APU)) {
                 r = amdgpu_uvd_suspend(adev);
                 if (r)
                         return r;
         }
-        r = uvd_v6_0_hw_fini(adev);
-        if (r)
-                return r;
 
         return r;
 }
diff --git a/drivers/gpu/drm/amd/include/cgs_common.h b/drivers/gpu/drm/amd/include/cgs_common.h
index aec38fc3834f..ab84d4947247 100644
--- a/drivers/gpu/drm/amd/include/cgs_common.h
+++ b/drivers/gpu/drm/amd/include/cgs_common.h
@@ -589,6 +589,8 @@ typedef int(*cgs_get_active_displays_info)(
                                         void *cgs_device,
                                         struct cgs_display_info *info);
 
+typedef int (*cgs_notify_dpm_enabled)(void *cgs_device, bool enabled);
+
 typedef int (*cgs_call_acpi_method)(void *cgs_device,
                                         uint32_t acpi_method,
                                         uint32_t acpi_function,
@@ -644,6 +646,8 @@ struct cgs_ops {
         cgs_set_clockgating_state set_clockgating_state;
         /* display manager */
         cgs_get_active_displays_info get_active_displays_info;
+        /* notify dpm enabled */
+        cgs_notify_dpm_enabled notify_dpm_enabled;
         /* ACPI */
         cgs_call_acpi_method call_acpi_method;
         /* get system info */
@@ -734,8 +738,12 @@ struct cgs_device
         CGS_CALL(set_powergating_state, dev, block_type, state)
 #define cgs_set_clockgating_state(dev, block_type, state)       \
         CGS_CALL(set_clockgating_state, dev, block_type, state)
+#define cgs_notify_dpm_enabled(dev, enabled)    \
+        CGS_CALL(notify_dpm_enabled, dev, enabled)
+
 #define cgs_get_active_displays_info(dev, info) \
         CGS_CALL(get_active_displays_info, dev, info)
+
 #define cgs_call_acpi_method(dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size)  \
         CGS_CALL(call_acpi_method, dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size)
 #define cgs_query_system_info(dev, sys_info)    \
diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
index 6b52c78cb404..56856a2864d1 100644
--- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
@@ -137,14 +137,14 @@ static const pem_event_action *resume_event[] = {
         reset_display_configCounter_tasks,
         update_dal_configuration_tasks,
         vari_bright_resume_tasks,
-        block_adjust_power_state_tasks,
         setup_asic_tasks,
         enable_stutter_mode_tasks, /*must do this in boot state and before SMC is started */
         enable_dynamic_state_management_tasks,
         enable_clock_power_gatings_tasks,
         enable_disable_bapm_tasks,
         initialize_thermal_controller_tasks,
-        reset_boot_state_tasks,
+        get_2d_performance_state_tasks,
+        set_performance_state_tasks,
         adjust_power_state_tasks,
         enable_disable_fps_tasks,
         notify_hw_power_source_tasks,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
index 51dedf84623c..89f31bc5b68b 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
@@ -2389,6 +2389,7 @@ static int fiji_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
 
         for(count = 0; count < table->VceLevelCount; count++) {
                 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
+                table->VceLevel[count].MinVoltage = 0;
                 table->VceLevel[count].MinVoltage |=
                                 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
                 table->VceLevel[count].MinVoltage |=
@@ -2465,6 +2466,7 @@ static int fiji_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
 
         for (count = 0; count < table->SamuLevelCount; count++) {
                 /* not sure whether we need evclk or not */
+                table->SamuLevel[count].MinVoltage = 0;
                 table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
                 table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
                                 VOLTAGE_SCALE) << VDDC_SHIFT;
@@ -2562,6 +2564,7 @@ static int fiji_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
         table->UvdBootLevel = 0;
 
         for (count = 0; count < table->UvdLevelCount; count++) {
+                table->UvdLevel[count].MinVoltage = 0;
                 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
                 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
                 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
@@ -2900,6 +2903,8 @@ static int fiji_init_smc_table(struct pp_hwmgr *hwmgr)
         if(FIJI_VOLTAGE_CONTROL_NONE != data->voltage_control)
                 fiji_populate_smc_voltage_tables(hwmgr, table);
 
+        table->SystemFlags = 0;
+
         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
                         PHM_PlatformCaps_AutomaticDCTransition))
                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
@@ -2997,6 +3002,7 @@ static int fiji_init_smc_table(struct pp_hwmgr *hwmgr)
         table->MemoryThermThrottleEnable = 1;
         table->PCIeBootLinkLevel = 0;      /* 0:Gen1 1:Gen2 2:Gen3*/
         table->PCIeGenInterval = 1;
+        table->VRConfig = 0;
 
         result = fiji_populate_vr_config(hwmgr, table);
         PP_ASSERT_WITH_CODE(0 == result,
@@ -5195,6 +5201,67 @@ static int fiji_print_clock_levels(struct pp_hwmgr *hwmgr,
         return size;
 }
 
+static inline bool fiji_are_power_levels_equal(const struct fiji_performance_level *pl1,
+                                                           const struct fiji_performance_level *pl2)
+{
+        return ((pl1->memory_clock == pl2->memory_clock) &&
+                  (pl1->engine_clock == pl2->engine_clock) &&
+                  (pl1->pcie_gen == pl2->pcie_gen) &&
+                  (pl1->pcie_lane == pl2->pcie_lane));
+}
+
+int fiji_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
+{
+        const struct fiji_power_state *psa = cast_const_phw_fiji_power_state(pstate1);
+        const struct fiji_power_state *psb = cast_const_phw_fiji_power_state(pstate2);
+        int i;
+
+        if (equal == NULL || psa == NULL || psb == NULL)
+                return -EINVAL;
+
+        /* If the two states don't even have the same number of performance levels they cannot be the same state. */
+        if (psa->performance_level_count != psb->performance_level_count) {
+                *equal = false;
+                return 0;
+        }
+
+        for (i = 0; i < psa->performance_level_count; i++) {
+                if (!fiji_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
+                        /* If we have found even one performance level pair that is different the states are different. */
+                        *equal = false;
+                        return 0;
+                }
+        }
+
+        /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
+        *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
+        *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
+        *equal &= (psa->sclk_threshold == psb->sclk_threshold);
+        *equal &= (psa->acp_clk == psb->acp_clk);
+
+        return 0;
+}
+
+bool fiji_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
+{
+        struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
+        bool is_update_required = false;
+        struct cgs_display_info info = {0,0,NULL};
+
+        cgs_get_active_displays_info(hwmgr->device, &info);
+
+        if (data->display_timing.num_existing_displays != info.display_count)
+                is_update_required = true;
+/* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL
+        if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
+                cgs_get_min_clock_settings(hwmgr->device, &min_clocks);
+                if(min_clocks.engineClockInSR != data->display_timing.minClockInSR)
+                        is_update_required = true;
+*/
+        return is_update_required;
+}
+
+
 static const struct pp_hwmgr_func fiji_hwmgr_funcs = {
         .backend_init = &fiji_hwmgr_backend_init,
         .backend_fini = &tonga_hwmgr_backend_fini,
@@ -5230,6 +5297,8 @@ static const struct pp_hwmgr_func fiji_hwmgr_funcs = {
         .register_internal_thermal_interrupt = fiji_register_internal_thermal_interrupt,
         .set_fan_control_mode = fiji_set_fan_control_mode,
         .get_fan_control_mode = fiji_get_fan_control_mode,
+        .check_states_equal = fiji_check_states_equal,
+        .check_smc_update_required_for_display_configuration = fiji_check_smc_update_required_for_display_configuration,
         .get_pp_table = fiji_get_pp_table,
         .set_pp_table = fiji_set_pp_table,
         .force_clock_level = fiji_force_clock_level,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
index be31bed2538a..fa208ada6892 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
@@ -58,6 +58,9 @@ void phm_init_dynamic_caps(struct pp_hwmgr *hwmgr)
 
         phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VpuRecoveryInProgress);
 
+        phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDDPM);
+        phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEDPM);
+
         if (acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST) &&
                 acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION))
                 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
@@ -130,18 +133,25 @@ int phm_set_power_state(struct pp_hwmgr *hwmgr,
 
 int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
 {
+        int ret = 1;
+        bool enabled;
         PHM_FUNC_CHECK(hwmgr);
 
         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
                 PHM_PlatformCaps_TablelessHardwareInterface)) {
                 if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable)
-                        return hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr);
+                        ret = hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr);
         } else {
-                return phm_dispatch_table(hwmgr,
+                ret = phm_dispatch_table(hwmgr,
                                 &(hwmgr->enable_dynamic_state_management),
                                 NULL, NULL);
         }
-        return 0;
+
+        enabled = ret == 0 ? true : false;
+
+        cgs_notify_dpm_enabled(hwmgr->device, enabled);
+
+        return ret;
 }
 
 int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level)
diff --git a/drivers/gpu/drm/arm/hdlcd_drv.c b/drivers/gpu/drm/arm/hdlcd_drv.c
index 56b829f97699..3ac1ae4d8caf 100644
--- a/drivers/gpu/drm/arm/hdlcd_drv.c
+++ b/drivers/gpu/drm/arm/hdlcd_drv.c
@@ -57,14 +57,13 @@ static int hdlcd_load(struct drm_device *drm, unsigned long flags)
                 DRM_ERROR("failed to map control registers area\n");
                 ret = PTR_ERR(hdlcd->mmio);
                 hdlcd->mmio = NULL;
-                goto fail;
+                return ret;
         }
 
         version = hdlcd_read(hdlcd, HDLCD_REG_VERSION);
         if ((version & HDLCD_PRODUCT_MASK) != HDLCD_PRODUCT_ID) {
                 DRM_ERROR("unknown product id: 0x%x\n", version);
-                ret = -EINVAL;
-                goto fail;
+                return -EINVAL;
         }
         DRM_INFO("found ARM HDLCD version r%dp%d\n",
                 (version & HDLCD_VERSION_MAJOR_MASK) >> 8,
@@ -73,7 +72,7 @@ static int hdlcd_load(struct drm_device *drm, unsigned long flags)
         /* Get the optional framebuffer memory resource */
         ret = of_reserved_mem_device_init(drm->dev);
         if (ret && ret != -ENODEV)
-                goto fail;
+                return ret;
 
         ret = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32));
         if (ret)
@@ -101,8 +100,6 @@ irq_fail:
         drm_crtc_cleanup(&hdlcd->crtc);
 setup_fail:
         of_reserved_mem_device_release(drm->dev);
-fail:
-        devm_clk_put(drm->dev, hdlcd->clk);
 
         return ret;
 }
@@ -412,7 +409,6 @@ err_unload:
         pm_runtime_put_sync(drm->dev);
         pm_runtime_disable(drm->dev);
         of_reserved_mem_device_release(drm->dev);
-        devm_clk_put(dev, hdlcd->clk);
 err_free:
         drm_dev_unref(drm);
 
@@ -436,10 +432,6 @@ static void hdlcd_drm_unbind(struct device *dev)
         pm_runtime_put_sync(drm->dev);
         pm_runtime_disable(drm->dev);
         of_reserved_mem_device_release(drm->dev);
-        if (!IS_ERR(hdlcd->clk)) {
-                devm_clk_put(drm->dev, hdlcd->clk);
-                hdlcd->clk = NULL;
-        }
         drm_mode_config_cleanup(drm);
         drm_dev_unregister(drm);
         drm_dev_unref(drm);
diff --git a/drivers/gpu/drm/armada/armada_gem.c b/drivers/gpu/drm/armada/armada_gem.c
index 6e731db31aa4..aca7f9cc6109 100644
--- a/drivers/gpu/drm/armada/armada_gem.c
+++ b/drivers/gpu/drm/armada/armada_gem.c
@@ -481,7 +481,7 @@ armada_gem_prime_map_dma_buf(struct dma_buf_attachment *attach,
 
  release:
         for_each_sg(sgt->sgl, sg, num, i)
-                page_cache_release(sg_page(sg));
+                put_page(sg_page(sg));
  free_table:
         sg_free_table(sgt);
  free_sgt:
@@ -502,7 +502,7 @@ static void armada_gem_prime_unmap_dma_buf(struct dma_buf_attachment *attach,
         if (dobj->obj.filp) {
                 struct scatterlist *sg;
                 for_each_sg(sgt->sgl, sg, sgt->nents, i)
-                        page_cache_release(sg_page(sg));
+                        put_page(sg_page(sg));
         }
 
         sg_free_table(sgt);
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c
index 27fbd79d0daf..71ea0521ea96 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -1672,13 +1672,19 @@ static int drm_dp_payload_send_msg(struct drm_dp_mst_topology_mgr *mgr,
         u8 sinks[DRM_DP_MAX_SDP_STREAMS];
         int i;
 
+        port = drm_dp_get_validated_port_ref(mgr, port);
+        if (!port)
+                return -EINVAL;
+
         port_num = port->port_num;
         mstb = drm_dp_get_validated_mstb_ref(mgr, port->parent);
         if (!mstb) {
                 mstb = drm_dp_get_last_connected_port_and_mstb(mgr, port->parent, &port_num);
 
-                if (!mstb)
+                if (!mstb) {
+                        drm_dp_put_port(port);
                         return -EINVAL;
+                }
         }
 
         txmsg = kzalloc(sizeof(*txmsg), GFP_KERNEL);
@@ -1707,6 +1713,7 @@ static int drm_dp_payload_send_msg(struct drm_dp_mst_topology_mgr *mgr,
         kfree(txmsg);
 fail_put:
         drm_dp_put_mst_branch_device(mstb);
+        drm_dp_put_port(port);
         return ret;
 }
 
@@ -1789,6 +1796,11 @@ int drm_dp_update_payload_part1(struct drm_dp_mst_topology_mgr *mgr)
                 req_payload.start_slot = cur_slots;
                 if (mgr->proposed_vcpis[i]) {
                         port = container_of(mgr->proposed_vcpis[i], struct drm_dp_mst_port, vcpi);
+                        port = drm_dp_get_validated_port_ref(mgr, port);
+                        if (!port) {
+                                mutex_unlock(&mgr->payload_lock);
+                                return -EINVAL;
+                        }
                         req_payload.num_slots = mgr->proposed_vcpis[i]->num_slots;
                         req_payload.vcpi = mgr->proposed_vcpis[i]->vcpi;
                 } else {
@@ -1816,6 +1828,9 @@ int drm_dp_update_payload_part1(struct drm_dp_mst_topology_mgr *mgr)
                         mgr->payloads[i].payload_state = req_payload.payload_state;
                 }
                 cur_slots += req_payload.num_slots;
+
+                if (port)
+                        drm_dp_put_port(port);
         }
 
         for (i = 0; i < mgr->max_payloads; i++) {
@@ -2121,6 +2136,8 @@ int drm_dp_mst_topology_mgr_resume(struct drm_dp_mst_topology_mgr *mgr)
 
         if (mgr->mst_primary) {
                 int sret;
+                u8 guid[16];
+
                 sret = drm_dp_dpcd_read(mgr->aux, DP_DPCD_REV, mgr->dpcd, DP_RECEIVER_CAP_SIZE);
                 if (sret != DP_RECEIVER_CAP_SIZE) {
                         DRM_DEBUG_KMS("dpcd read failed - undocked during suspend?\n");
@@ -2135,6 +2152,16 @@ int drm_dp_mst_topology_mgr_resume(struct drm_dp_mst_topology_mgr *mgr)
                         ret = -1;
                         goto out_unlock;
                 }
+
+                /* Some hubs forget their guids after they resume */
+                sret = drm_dp_dpcd_read(mgr->aux, DP_GUID, guid, 16);
+                if (sret != 16) {
+                        DRM_DEBUG_KMS("dpcd read failed - undocked during suspend?\n");
+                        ret = -1;
+                        goto out_unlock;
+                }
+                drm_dp_check_mstb_guid(mgr->mst_primary, guid);
+
                 ret = 0;
         } else
                 ret = -1;
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 414d7f61aa05..558ef9fc39e6 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -205,7 +205,7 @@ static const struct drm_display_mode drm_dmt_modes[] = {
                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
         /* 0x0f - 1024x768@43Hz, interlace */
         { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
-                   1208, 1264, 0, 768, 768, 772, 817, 0,
+                   1208, 1264, 0, 768, 768, 776, 817, 0,
                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
                    DRM_MODE_FLAG_INTERLACE) },
         /* 0x10 - 1024x768@60Hz */
@@ -522,12 +522,12 @@ static const struct drm_display_mode edid_est_modes[] = {
                    720, 840, 0, 480, 481, 484, 500, 0,
                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
         { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
-                   704,  832, 0, 480, 489, 491, 520, 0,
+                   704,  832, 0, 480, 489, 492, 520, 0,
                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
         { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
                    768,  864, 0, 480, 483, 486, 525, 0,
                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
-        { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25200, 640, 656,
+        { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
                    752, 800, 0, 480, 490, 492, 525, 0,
                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
         { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
@@ -539,7 +539,7 @@ static const struct drm_display_mode edid_est_modes[] = {
         { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
                    1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
-        { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78800, 1024, 1040,
+        { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
                    1136, 1312, 0,  768, 769, 772, 800, 0,
                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
         { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
@@ -2241,7 +2241,7 @@ drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
 {
         int i, j, m, modes = 0;
         struct drm_display_mode *mode;
-        u8 *est = ((u8 *)timing) + 5;
+        u8 *est = ((u8 *)timing) + 6;
 
         for (i = 0; i < 6; i++) {
                 for (j = 7; j >= 0; j--) {
diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
index 2e8c77e71e1f..da0c5320789f 100644
--- a/drivers/gpu/drm/drm_gem.c
+++ b/drivers/gpu/drm/drm_gem.c
@@ -534,7 +534,7 @@ struct page **drm_gem_get_pages(struct drm_gem_object *obj)
 
 fail:
         while (i--)
-                page_cache_release(pages[i]);
+                put_page(pages[i]);
 
         drm_free_large(pages);
         return ERR_CAST(p);
@@ -569,7 +569,7 @@ void drm_gem_put_pages(struct drm_gem_object *obj, struct page **pages,
                         mark_page_accessed(pages[i]);
 
                 /* Undo the reference we took when populating the table */
-                page_cache_release(pages[i]);
+                put_page(pages[i]);
         }
 
         drm_free_large(pages);
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
index 09198d0b5814..306dde18a94a 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
@@ -572,6 +572,24 @@ int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
                 goto fail;
         }
 
+        /*
+         * Set the GPU linear window to be at the end of the DMA window, where
+         * the CMA area is likely to reside. This ensures that we are able to
+         * map the command buffers while having the linear window overlap as
+         * much RAM as possible, so we can optimize mappings for other buffers.
+         *
+         * For 3D cores only do this if MC2.0 is present, as with MC1.0 it leads
+         * to different views of the memory on the individual engines.
+         */
+        if (!(gpu->identity.features & chipFeatures_PIPE_3D) ||
+            (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) {
+                u32 dma_mask = (u32)dma_get_required_mask(gpu->dev);
+                if (dma_mask < PHYS_OFFSET + SZ_2G)
+                        gpu->memory_base = PHYS_OFFSET;
+                else
+                        gpu->memory_base = dma_mask - SZ_2G + 1;
+        }
+
         ret = etnaviv_hw_reset(gpu);
         if (ret)
                 goto fail;
@@ -1566,7 +1584,6 @@ static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
 {
         struct device *dev = &pdev->dev;
         struct etnaviv_gpu *gpu;
-        u32 dma_mask;
         int err = 0;
 
         gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL);
@@ -1576,18 +1593,6 @@ static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
         gpu->dev = &pdev->dev;
         mutex_init(&gpu->lock);
 
-        /*
-         * Set the GPU linear window to be at the end of the DMA window, where
-         * the CMA area is likely to reside. This ensures that we are able to
-         * map the command buffers while having the linear window overlap as
-         * much RAM as possible, so we can optimize mappings for other buffers.
-         */
-        dma_mask = (u32)dma_get_required_mask(dev);
-        if (dma_mask < PHYS_OFFSET + SZ_2G)
-                gpu->memory_base = PHYS_OFFSET;
-        else
-                gpu->memory_base = dma_mask - SZ_2G + 1;
-
         /* Map registers: */
         gpu->mmio = etnaviv_ioremap(pdev, NULL, dev_name(gpu->dev));
         if (IS_ERR(gpu->mmio))
diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig
index f17d39279596..baddf33fb475 100644
--- a/drivers/gpu/drm/exynos/Kconfig
+++ b/drivers/gpu/drm/exynos/Kconfig
@@ -94,7 +94,7 @@ comment "Sub-drivers"
 
 config DRM_EXYNOS_G2D
         bool "G2D"
-        depends on !VIDEO_SAMSUNG_S5P_G2D
+        depends on VIDEO_SAMSUNG_S5P_G2D=n
         select FRAME_VECTOR
         help
           Choose this option if you want to use Exynos G2D for DRM.
diff --git a/drivers/gpu/drm/exynos/Makefile b/drivers/gpu/drm/exynos/Makefile
index 968b31c522b2..23d2f958739b 100644
--- a/drivers/gpu/drm/exynos/Makefile
+++ b/drivers/gpu/drm/exynos/Makefile
@@ -2,10 +2,10 @@
 # Makefile for the drm device driver.  This driver provides support for the
 # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
 
-exynosdrm-y := exynos_drm_drv.o exynos_drm_crtc.o exynos_drm_fbdev.o \
-                exynos_drm_fb.o exynos_drm_gem.o exynos_drm_core.o \
-                exynos_drm_plane.o
+exynosdrm-y := exynos_drm_drv.o exynos_drm_crtc.o exynos_drm_fb.o \
+                exynos_drm_gem.o exynos_drm_core.o exynos_drm_plane.o
 
+exynosdrm-$(CONFIG_DRM_FBDEV_EMULATION) += exynos_drm_fbdev.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_IOMMU) += exynos_drm_iommu.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_FIMD)     += exynos_drm_fimd.o
 exynosdrm-$(CONFIG_DRM_EXYNOS5433_DECON)        += exynos5433_drm_decon.o
diff --git a/drivers/gpu/drm/exynos/exynos_drm_core.c b/drivers/gpu/drm/exynos/exynos_drm_core.c
index 7f55ba6771c6..011211e4167d 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_core.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_core.c
@@ -101,7 +101,7 @@ int exynos_drm_subdrv_open(struct drm_device *dev, struct drm_file *file)
         return 0;
 
 err:
-        list_for_each_entry_reverse(subdrv, &subdrv->list, list) {
+        list_for_each_entry_continue_reverse(subdrv, &exynos_drm_subdrv_list, list) {
                 if (subdrv->close)
                         subdrv->close(dev, subdrv->dev, file);
         }
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fb.c b/drivers/gpu/drm/exynos/exynos_drm_fb.c
index d614194644c8..81cc5537cf25 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fb.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fb.c
@@ -199,17 +199,6 @@ dma_addr_t exynos_drm_fb_dma_addr(struct drm_framebuffer *fb, int index)
         return exynos_fb->dma_addr[index];
 }
 
-static void exynos_drm_output_poll_changed(struct drm_device *dev)
-{
-        struct exynos_drm_private *private = dev->dev_private;
-        struct drm_fb_helper *fb_helper = private->fb_helper;
-
-        if (fb_helper)
-                drm_fb_helper_hotplug_event(fb_helper);
-        else
-                exynos_drm_fbdev_init(dev);
-}
-
 static const struct drm_mode_config_funcs exynos_drm_mode_config_funcs = {
         .fb_create = exynos_user_fb_create,
         .output_poll_changed = exynos_drm_output_poll_changed,
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
index 4ae860c44f1d..72d7c0b7c216 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
@@ -317,3 +317,14 @@ void exynos_drm_fbdev_restore_mode(struct drm_device *dev)
 
         drm_fb_helper_restore_fbdev_mode_unlocked(private->fb_helper);
 }
+
+void exynos_drm_output_poll_changed(struct drm_device *dev)
+{
+        struct exynos_drm_private *private = dev->dev_private;
+        struct drm_fb_helper *fb_helper = private->fb_helper;
+
+        if (fb_helper)
+                drm_fb_helper_hotplug_event(fb_helper);
+        else
+                exynos_drm_fbdev_init(dev);
+}
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fbdev.h b/drivers/gpu/drm/exynos/exynos_drm_fbdev.h
index e16d7f0ae192..330eef87f718 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fbdev.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_fbdev.h
@@ -15,9 +15,30 @@
 #ifndef _EXYNOS_DRM_FBDEV_H_
 #define _EXYNOS_DRM_FBDEV_H_
 
+#ifdef CONFIG_DRM_FBDEV_EMULATION
+
 int exynos_drm_fbdev_init(struct drm_device *dev);
-int exynos_drm_fbdev_reinit(struct drm_device *dev);
 void exynos_drm_fbdev_fini(struct drm_device *dev);
 void exynos_drm_fbdev_restore_mode(struct drm_device *dev);
+void exynos_drm_output_poll_changed(struct drm_device *dev);
+
+#else
+
+static inline int exynos_drm_fbdev_init(struct drm_device *dev)
+{
+        return 0;
+}
+
+static inline void exynos_drm_fbdev_fini(struct drm_device *dev)
+{
+}
+
+static inline void exynos_drm_fbdev_restore_mode(struct drm_device *dev)
+{
+}
+
+#define exynos_drm_output_poll_changed (NULL)
+
+#endif
 
 #endif
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 51d484ae9f49..018449f8d557 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -888,7 +888,7 @@ static void fimd_dp_clock_enable(struct exynos_drm_crtc *crtc, bool enable)
          * clock. On these SoCs the bootloader may enable it but any
          * power domain off/on will reset it to disable state.
          */
-        if (ctx->driver_data != &exynos5_fimd_driver_data ||
+        if (ctx->driver_data != &exynos5_fimd_driver_data &&
             ctx->driver_data != &exynos5420_fimd_driver_data)
                 return;
 
diff --git a/drivers/gpu/drm/exynos/exynos_drm_mic.c b/drivers/gpu/drm/exynos/exynos_drm_mic.c
index 9869d70e9e54..a0def0be6d65 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_mic.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_mic.c
@@ -129,7 +129,7 @@ static void mic_set_path(struct exynos_mic *mic, bool enable)
         } else
                 val &= ~(MIC0_RGB_MUX | MIC0_I80_MUX | MIC0_ON_MUX);
 
-        regmap_write(mic->sysreg, DSD_CFG_MUX, val);
+        ret = regmap_write(mic->sysreg, DSD_CFG_MUX, val);
         if (ret)
                 DRM_ERROR("mic: Failed to read system register\n");
 }
@@ -457,6 +457,7 @@ static int exynos_mic_probe(struct platform_device *pdev)
                                                         "samsung,disp-syscon");
         if (IS_ERR(mic->sysreg)) {
                 DRM_ERROR("mic: Failed to get system register.\n");
+                ret = PTR_ERR(mic->sysreg);
                 goto err;
         }
 
diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c b/drivers/gpu/drm/exynos/exynos_drm_plane.c
index d86227236f55..50185ac347b2 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_plane.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c
@@ -11,9 +11,10 @@
 
 #include <drm/drmP.h>
 
-#include <drm/exynos_drm.h>
-#include <drm/drm_plane_helper.h>
+#include <drm/drm_atomic.h>
 #include <drm/drm_atomic_helper.h>
+#include <drm/drm_plane_helper.h>
+#include <drm/exynos_drm.h>
 #include "exynos_drm_drv.h"
 #include "exynos_drm_crtc.h"
 #include "exynos_drm_fb.h"
@@ -57,11 +58,12 @@ static int exynos_plane_get_size(int start, unsigned length, unsigned last)
 }
 
 static void exynos_plane_mode_set(struct exynos_drm_plane_state *exynos_state)
-
 {
         struct drm_plane_state *state = &exynos_state->base;
-        struct drm_crtc *crtc = exynos_state->base.crtc;
-        struct drm_display_mode *mode = &crtc->state->adjusted_mode;
+        struct drm_crtc *crtc = state->crtc;
+        struct drm_crtc_state *crtc_state =
+                        drm_atomic_get_existing_crtc_state(state->state, crtc);
+        struct drm_display_mode *mode = &crtc_state->adjusted_mode;
         int crtc_x, crtc_y;
         unsigned int crtc_w, crtc_h;
         unsigned int src_x, src_y;
diff --git a/drivers/gpu/drm/gma500/cdv_intel_dp.c b/drivers/gpu/drm/gma500/cdv_intel_dp.c
index 7bb1f1aff932..c52f9adf5e04 100644
--- a/drivers/gpu/drm/gma500/cdv_intel_dp.c
+++ b/drivers/gpu/drm/gma500/cdv_intel_dp.c
@@ -220,7 +220,7 @@ i2c_dp_aux_prepare_bus(struct i2c_adapter *adapter)
  * FIXME: This is the old dp aux helper, gma500 is the last driver that needs to
  * be ported over to the new helper code in drm_dp_helper.c like i915 or radeon.
  */
-static int __deprecated
+static int
 i2c_dp_aux_add_bus(struct i2c_adapter *adapter)
 {
         int error;
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 20e82008b8b6..30798cbc6fc0 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -758,10 +758,10 @@ static int i915_drm_resume(struct drm_device *dev)
                 dev_priv->display.hpd_irq_setup(dev);
         spin_unlock_irq(&dev_priv->irq_lock);
 
-        intel_display_resume(dev);
-
         intel_dp_mst_resume(dev);
 
+        intel_display_resume(dev);
+
         /*
          * ... but also need to make sure that hotplug processing
          * doesn't cause havoc. Like in the driver load code we don't
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 10480939159c..daba7ebb9699 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2634,8 +2634,9 @@ struct drm_i915_cmd_table {
 
 /* WaRsDisableCoarsePowerGating:skl,bxt */
 #define NEEDS_WaRsDisableCoarsePowerGating(dev) (IS_BXT_REVID(dev, 0, BXT_REVID_A1) || \
-                                                 ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && \
-                                                  IS_SKL_REVID(dev, 0, SKL_REVID_F0)))
+                                                 IS_SKL_GT3(dev) || \
+                                                 IS_SKL_GT4(dev))
+
 /*
  * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
  * even when in MSI mode. This results in spurious interrupt warnings if the
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 3d31d3ac589e..dabc08987b5e 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -177,7 +177,7 @@ i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
                 drm_clflush_virt_range(vaddr, PAGE_SIZE);
                 kunmap_atomic(src);
 
-                page_cache_release(page);
+                put_page(page);
                 vaddr += PAGE_SIZE;
         }
 
@@ -243,7 +243,7 @@ i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj)
                         set_page_dirty(page);
                         if (obj->madv == I915_MADV_WILLNEED)
                                 mark_page_accessed(page);
-                        page_cache_release(page);
+                        put_page(page);
                         vaddr += PAGE_SIZE;
                 }
                 obj->dirty = 0;
@@ -2206,7 +2206,7 @@ i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
                 if (obj->madv == I915_MADV_WILLNEED)
                         mark_page_accessed(page);
 
-                page_cache_release(page);
+                put_page(page);
         }
         obj->dirty = 0;
 
@@ -2346,7 +2346,7 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
 err_pages:
         sg_mark_end(sg);
         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
-                page_cache_release(sg_page_iter_page(&sg_iter));
+                put_page(sg_page_iter_page(&sg_iter));
         sg_free_table(st);
         kfree(st);
 
diff --git a/drivers/gpu/drm/i915/i915_gem_userptr.c b/drivers/gpu/drm/i915/i915_gem_userptr.c
index 6be40f3ba2c7..4d30b60defda 100644
--- a/drivers/gpu/drm/i915/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/i915_gem_userptr.c
@@ -501,19 +501,24 @@ __i915_gem_userptr_get_pages_worker(struct work_struct *_work)
         if (pvec != NULL) {
                 struct mm_struct *mm = obj->userptr.mm->mm;
 
-                down_read(&mm->mmap_sem);
-                while (pinned < npages) {
-                        ret = get_user_pages_remote(work->task, mm,
-                                        obj->userptr.ptr + pinned * PAGE_SIZE,
-                                        npages - pinned,
-                                        !obj->userptr.read_only, 0,
-                                        pvec + pinned, NULL);
-                        if (ret < 0)
-                                break;
-
-                        pinned += ret;
+                ret = -EFAULT;
+                if (atomic_inc_not_zero(&mm->mm_users)) {
+                        down_read(&mm->mmap_sem);
+                        while (pinned < npages) {
+                                ret = get_user_pages_remote
+                                        (work->task, mm,
+                                         obj->userptr.ptr + pinned * PAGE_SIZE,
+                                         npages - pinned,
+                                         !obj->userptr.read_only, 0,
+                                         pvec + pinned, NULL);
+                                if (ret < 0)
+                                        break;
+
+                                pinned += ret;
+                        }
+                        up_read(&mm->mmap_sem);
+                        mmput(mm);
                 }
-                up_read(&mm->mmap_sem);
         }
 
         mutex_lock(&dev->struct_mutex);
@@ -683,7 +688,7 @@ i915_gem_userptr_put_pages(struct drm_i915_gem_object *obj)
                         set_page_dirty(page);
 
                 mark_page_accessed(page);
-                page_cache_release(page);
+                put_page(page);
         }
         obj->dirty = 0;
 
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d1a46ef5ab3f..1c212205d0e7 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1829,7 +1829,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
         disable_rpm_wakeref_asserts(dev_priv);
 
-        for (;;) {
+        do {
                 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
                 iir = I915_READ(VLV_IIR);
 
@@ -1857,7 +1857,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
 
                 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
                 POSTING_READ(GEN8_MASTER_IRQ);
-        }
+        } while (0);
 
         enable_rpm_wakeref_asserts(dev_priv);
 
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index a2bd698fe2f7..937e77228466 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -506,6 +506,8 @@ static void intel_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
         struct intel_connector *intel_connector = to_intel_connector(connector);
         struct drm_device *dev = connector->dev;
 
+        intel_connector->unregister(intel_connector);
+
         /* need to nuke the connector */
         drm_modeset_lock_all(dev);
         if (connector->state->crtc) {
@@ -519,11 +521,7 @@ static void intel_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
 
                 WARN(ret, "Disabling mst crtc failed with %i\n", ret);
         }
-        drm_modeset_unlock_all(dev);
 
-        intel_connector->unregister(intel_connector);
-
-        drm_modeset_lock_all(dev);
         intel_connector_remove_from_fbdev(intel_connector);
         drm_connector_cleanup(connector);
         drm_modeset_unlock_all(dev);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 6a978ce80244..5c6080fd0968 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -841,11 +841,11 @@ static int logical_ring_prepare(struct drm_i915_gem_request *req, int bytes)
                 if (unlikely(total_bytes > remain_usable)) {
                         /*
                          * The base request will fit but the reserved space
-                         * falls off the end. So only need to to wait for the
-                         * reserved size after flushing out the remainder.
+                         * falls off the end. So don't need an immediate wrap
+                         * and only need to effectively wait for the reserved
+                         * size space from the start of ringbuffer.
                          */
                         wait_bytes = remain_actual + ringbuf->reserved_size;
-                        need_wrap = true;
                 } else if (total_bytes > ringbuf->space) {
                         /* No wrapping required, just waiting. */
                         wait_bytes = total_bytes;
@@ -1913,15 +1913,18 @@ static int gen8_emit_request_render(struct drm_i915_gem_request *request)
         struct intel_ringbuffer *ringbuf = request->ringbuf;
         int ret;
 
-        ret = intel_logical_ring_begin(request, 6 + WA_TAIL_DWORDS);
+        ret = intel_logical_ring_begin(request, 8 + WA_TAIL_DWORDS);
         if (ret)
                 return ret;
 
+        /* We're using qword write, seqno should be aligned to 8 bytes. */
+        BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1);
+
         /* w/a for post sync ops following a GPGPU operation we
          * need a prior CS_STALL, which is emitted by the flush
          * following the batch.
          */
-        intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(5));
+        intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
         intel_logical_ring_emit(ringbuf,
                                 (PIPE_CONTROL_GLOBAL_GTT_IVB |
                                  PIPE_CONTROL_CS_STALL |
@@ -1929,7 +1932,10 @@ static int gen8_emit_request_render(struct drm_i915_gem_request *request)
         intel_logical_ring_emit(ringbuf, hws_seqno_address(request->ring));
         intel_logical_ring_emit(ringbuf, 0);
         intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request));
+        /* We're thrashing one dword of HWS. */
+        intel_logical_ring_emit(ringbuf, 0);
         intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
+        intel_logical_ring_emit(ringbuf, MI_NOOP);
         return intel_logical_ring_advance_and_submit(request);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 30a8403a8f4f..cd9fe609aefb 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -478,11 +478,8 @@ static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
          * and as part of the cleanup in the hw state restore we also redisable
          * the vga plane.
          */
-        if (!HAS_PCH_SPLIT(dev)) {
-                drm_modeset_lock_all(dev);
+        if (!HAS_PCH_SPLIT(dev))
                 intel_display_resume(dev);
-                drm_modeset_unlock_all(dev);
-        }
 
         dev_priv->modeset_restore = MODESET_DONE;
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 347d4df49a9b..8ed3cf34f82d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2876,25 +2876,28 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
                              const struct drm_plane_state *pstate,
                              int y)
 {
-        struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
+        struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
         struct drm_framebuffer *fb = pstate->fb;
+        uint32_t width = 0, height = 0;
+
+        width = drm_rect_width(&intel_pstate->src) >> 16;
+        height = drm_rect_height(&intel_pstate->src) >> 16;
+
+        if (intel_rotation_90_or_270(pstate->rotation))
+                swap(width, height);
 
         /* for planar format */
         if (fb->pixel_format == DRM_FORMAT_NV12) {
                 if (y)  /* y-plane data rate */
-                        return intel_crtc->config->pipe_src_w *
-                                intel_crtc->config->pipe_src_h *
+                        return width * height *
                                 drm_format_plane_cpp(fb->pixel_format, 0);
                 else    /* uv-plane data rate */
-                        return (intel_crtc->config->pipe_src_w/2) *
-                                (intel_crtc->config->pipe_src_h/2) *
+                        return (width / 2) * (height / 2) *
                                 drm_format_plane_cpp(fb->pixel_format, 1);
         }
 
         /* for packed formats */
-        return intel_crtc->config->pipe_src_w *
-                intel_crtc->config->pipe_src_h *
-                drm_format_plane_cpp(fb->pixel_format, 0);
+        return width * height * drm_format_plane_cpp(fb->pixel_format, 0);
 }
 
 /*
@@ -2973,8 +2976,9 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
                 struct drm_framebuffer *fb = plane->state->fb;
                 int id = skl_wm_plane_id(intel_plane);
 
-                if (fb == NULL)
+                if (!to_intel_plane_state(plane->state)->visible)
                         continue;
+
                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
                         continue;
 
@@ -3000,7 +3004,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
                 uint16_t plane_blocks, y_plane_blocks = 0;
                 int id = skl_wm_plane_id(intel_plane);
 
-                if (pstate->fb == NULL)
+                if (!to_intel_plane_state(pstate)->visible)
                         continue;
                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
                         continue;
@@ -3123,26 +3127,36 @@ static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 {
         struct drm_plane *plane = &intel_plane->base;
         struct drm_framebuffer *fb = plane->state->fb;
+        struct intel_plane_state *intel_pstate =
+                                        to_intel_plane_state(plane->state);
         uint32_t latency = dev_priv->wm.skl_latency[level];
         uint32_t method1, method2;
         uint32_t plane_bytes_per_line, plane_blocks_per_line;
         uint32_t res_blocks, res_lines;
         uint32_t selected_result;
         uint8_t cpp;
+        uint32_t width = 0, height = 0;
 
-        if (latency == 0 || !cstate->base.active || !fb)
+        if (latency == 0 || !cstate->base.active || !intel_pstate->visible)
                 return false;
 
+        width = drm_rect_width(&intel_pstate->src) >> 16;
+        height = drm_rect_height(&intel_pstate->src) >> 16;
+
+        if (intel_rotation_90_or_270(plane->state->rotation))
+                swap(width, height);
+
         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
         method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate),
                                  cpp, latency);
         method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate),
                                  cstate->base.adjusted_mode.crtc_htotal,
-                                 cstate->pipe_src_w,
-                                 cpp, fb->modifier[0],
+                                 width,
+                                 cpp,
+                                 fb->modifier[0],
                                  latency);
 
-        plane_bytes_per_line = cstate->pipe_src_w * cpp;
+        plane_bytes_per_line = width * cpp;
         plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
 
         if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 45ce45a5e122..9121646d7c4d 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -968,7 +968,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 
         /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
         tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
-        if (IS_SKL_REVID(dev, SKL_REVID_F0, SKL_REVID_F0) ||
+        if (IS_SKL_REVID(dev, SKL_REVID_F0, REVID_FOREVER) ||
             IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER))
                 tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
         WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
@@ -1085,7 +1085,8 @@ static int skl_init_workarounds(struct intel_engine_cs *ring)
                 WA_SET_BIT_MASKED(HIZ_CHICKEN,
                                   BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
 
-        if (IS_SKL_REVID(dev, 0, SKL_REVID_F0)) {
+        /* This is tied to WaForceContextSaveRestoreNonCoherent */
+        if (IS_SKL_REVID(dev, 0, REVID_FOREVER)) {
                 /*
                  *Use Force Non-Coherent whenever executing a 3D context. This
                  * is a workaround for a possible hang in the unlikely event
@@ -2090,10 +2091,12 @@ int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
 {
         struct drm_i915_private *dev_priv = to_i915(dev);
         struct drm_i915_gem_object *obj = ringbuf->obj;
+        /* Ring wraparound at offset 0 sometimes hangs. No idea why. */
+        unsigned flags = PIN_OFFSET_BIAS | 4096;
         int ret;
 
         if (HAS_LLC(dev_priv) && !obj->stolen) {
-                ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, 0);
+                ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, flags);
                 if (ret)
                         return ret;
 
@@ -2109,7 +2112,8 @@ int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
                         return -ENOMEM;
                 }
         } else {
-                ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
+                ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE,
+                                            flags | PIN_MAPPABLE);
                 if (ret)
                         return ret;
 
@@ -2454,11 +2458,11 @@ static int __intel_ring_prepare(struct intel_engine_cs *ring, int bytes)
                 if (unlikely(total_bytes > remain_usable)) {
                         /*
                          * The base request will fit but the reserved space
-                         * falls off the end. So only need to to wait for the
-                         * reserved size after flushing out the remainder.
+                         * falls off the end. So don't need an immediate wrap
+                         * and only need to effectively wait for the reserved
+                         * size space from the start of ringbuffer.
                          */
                         wait_bytes = remain_actual + ringbuf->reserved_size;
-                        need_wrap = true;
                 } else if (total_bytes > ringbuf->space) {
                         /* No wrapping required, just waiting. */
                         wait_bytes = total_bytes;
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 436d8f2b8682..68b6f69aa682 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1189,7 +1189,11 @@ static void intel_uncore_fw_domains_init(struct drm_device *dev)
         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
                 dev_priv->uncore.funcs.force_wake_get =
                         fw_domains_get_with_thread_status;
-                dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
+                if (IS_HASWELL(dev))
+                        dev_priv->uncore.funcs.force_wake_put =
+                                fw_domains_put_with_fifo;
+                else
+                        dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
                                FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
         } else if (IS_IVYBRIDGE(dev)) {
diff --git a/drivers/gpu/drm/imx/dw_hdmi-imx.c b/drivers/gpu/drm/imx/dw_hdmi-imx.c
index 2a95d10e9d92..a24631fdf4ad 100644
--- a/drivers/gpu/drm/imx/dw_hdmi-imx.c
+++ b/drivers/gpu/drm/imx/dw_hdmi-imx.c
@@ -225,8 +225,6 @@ static int dw_hdmi_imx_bind(struct device *dev, struct device *master,
         if (!iores)
                 return -ENXIO;
 
-        platform_set_drvdata(pdev, hdmi);
-
         encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
         /*
          * If we failed to find the CRTC(s) which this encoder is
@@ -245,7 +243,16 @@ static int dw_hdmi_imx_bind(struct device *dev, struct device *master,
         drm_encoder_init(drm, encoder, &dw_hdmi_imx_encoder_funcs,
                          DRM_MODE_ENCODER_TMDS, NULL);
 
-        return dw_hdmi_bind(dev, master, data, encoder, iores, irq, plat_data);
+        ret = dw_hdmi_bind(dev, master, data, encoder, iores, irq, plat_data);
+
+        /*
+         * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(),
+         * which would have called the encoder cleanup.  Do it manually.
+         */
+        if (ret)
+                drm_encoder_cleanup(encoder);
+
+        return ret;
 }
 
 static void dw_hdmi_imx_unbind(struct device *dev, struct device *master,
diff --git a/drivers/gpu/drm/imx/imx-drm-core.c b/drivers/gpu/drm/imx/imx-drm-core.c
index 9876e0f0c3e1..e26dcdec2aba 100644
--- a/drivers/gpu/drm/imx/imx-drm-core.c
+++ b/drivers/gpu/drm/imx/imx-drm-core.c
@@ -326,7 +326,6 @@ int imx_drm_add_crtc(struct drm_device *drm, struct drm_crtc *crtc,
 {
         struct imx_drm_device *imxdrm = drm->dev_private;
         struct imx_drm_crtc *imx_drm_crtc;
-        int ret;
 
         /*
          * The vblank arrays are dimensioned by MAX_CRTC - we can't
@@ -351,10 +350,6 @@ int imx_drm_add_crtc(struct drm_device *drm, struct drm_crtc *crtc,
 
         *new_crtc = imx_drm_crtc;
 
-        ret = drm_mode_crtc_set_gamma_size(imx_drm_crtc->crtc, 256);
-        if (ret)
-                goto err_register;
-
         drm_crtc_helper_add(crtc,
                         imx_drm_crtc->imx_drm_helper_funcs.crtc_helper_funcs);
 
@@ -362,11 +357,6 @@ int imx_drm_add_crtc(struct drm_device *drm, struct drm_crtc *crtc,
                         imx_drm_crtc->imx_drm_helper_funcs.crtc_funcs, NULL);
 
         return 0;
-
-err_register:
-        imxdrm->crtc[--imxdrm->pipes] = NULL;
-        kfree(imx_drm_crtc);
-        return ret;
 }
 EXPORT_SYMBOL_GPL(imx_drm_add_crtc);
 
diff --git a/drivers/gpu/drm/imx/ipuv3-plane.c b/drivers/gpu/drm/imx/ipuv3-plane.c
index 588827844f30..681ec6eb77d9 100644
--- a/drivers/gpu/drm/imx/ipuv3-plane.c
+++ b/drivers/gpu/drm/imx/ipuv3-plane.c
@@ -72,22 +72,101 @@ static inline int calc_bandwidth(int width, int height, unsigned int vref)
 int ipu_plane_set_base(struct ipu_plane *ipu_plane, struct drm_framebuffer *fb,
                        int x, int y)
 {
-        struct drm_gem_cma_object *cma_obj;
-        unsigned long eba;
-        int active;
-
-        cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
-        if (!cma_obj) {
-                DRM_DEBUG_KMS("entry is null.\n");
-                return -EFAULT;
+        struct drm_gem_cma_object *cma_obj[3];
+        unsigned long eba, ubo, vbo;
+        int active, i;
+
+        for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
+                cma_obj[i] = drm_fb_cma_get_gem_obj(fb, i);
+                if (!cma_obj[i]) {
+                        DRM_DEBUG_KMS("plane %d entry is null.\n", i);
+                        return -EFAULT;
+                }
         }
 
-        dev_dbg(ipu_plane->base.dev->dev, "phys = %pad, x = %d, y = %d",
-                &cma_obj->paddr, x, y);
-
-        eba = cma_obj->paddr + fb->offsets[0] +
+        eba = cma_obj[0]->paddr + fb->offsets[0] +
               fb->pitches[0] * y + (fb->bits_per_pixel >> 3) * x;
 
+        if (eba & 0x7) {
+                DRM_DEBUG_KMS("base address must be a multiple of 8.\n");
+                return -EINVAL;
+        }
+
+        if (fb->pitches[0] < 1 || fb->pitches[0] > 16384) {
+                DRM_DEBUG_KMS("pitches out of range.\n");
+                return -EINVAL;
+        }
+
+        if (ipu_plane->enabled && fb->pitches[0] != ipu_plane->stride[0]) {
+                DRM_DEBUG_KMS("pitches must not change while plane is enabled.\n");
+                return -EINVAL;
+        }
+
+        ipu_plane->stride[0] = fb->pitches[0];
+
+        switch (fb->pixel_format) {
+        case DRM_FORMAT_YUV420:
+        case DRM_FORMAT_YVU420:
+                /*
+                 * Multiplanar formats have to meet the following restrictions:
+                 * - The (up to) three plane addresses are EBA, EBA+UBO, EBA+VBO
+                 * - EBA, UBO and VBO are a multiple of 8
+                 * - UBO and VBO are unsigned and not larger than 0xfffff8
+                 * - Only EBA may be changed while scanout is active
+                 * - The strides of U and V planes must be identical.
+                 */
+                ubo = cma_obj[1]->paddr + fb->offsets[1] +
+                      fb->pitches[1] * y / 2 + x / 2 - eba;
+                vbo = cma_obj[2]->paddr + fb->offsets[2] +
+                      fb->pitches[2] * y / 2 + x / 2 - eba;
+
+                if ((ubo & 0x7) || (vbo & 0x7)) {
+                        DRM_DEBUG_KMS("U/V buffer offsets must be a multiple of 8.\n");
+                        return -EINVAL;
+                }
+
+                if ((ubo > 0xfffff8) || (vbo > 0xfffff8)) {
+                        DRM_DEBUG_KMS("U/V buffer offsets must be positive and not larger than 0xfffff8.\n");
+                        return -EINVAL;
+                }
+
+                if (ipu_plane->enabled && ((ipu_plane->u_offset != ubo) ||
+                                           (ipu_plane->v_offset != vbo))) {
+                        DRM_DEBUG_KMS("U/V buffer offsets must not change while plane is enabled.\n");
+                        return -EINVAL;
+                }
+
+                if (fb->pitches[1] != fb->pitches[2]) {
+                        DRM_DEBUG_KMS("U/V pitches must be identical.\n");
+                        return -EINVAL;
+                }
+
+                if (fb->pitches[1] < 1 || fb->pitches[1] > 16384) {
+                        DRM_DEBUG_KMS("U/V pitches out of range.\n");
+                        return -EINVAL;
+                }
+
+                if (ipu_plane->enabled &&
+                    (ipu_plane->stride[1] != fb->pitches[1])) {
+                        DRM_DEBUG_KMS("U/V pitches must not change while plane is enabled.\n");
+                        return -EINVAL;
+                }
+
+                ipu_plane->u_offset = ubo;
+                ipu_plane->v_offset = vbo;
+                ipu_plane->stride[1] = fb->pitches[1];
+
+                dev_dbg(ipu_plane->base.dev->dev,
+                        "phys = %pad %pad %pad, x = %d, y = %d",
+                        &cma_obj[0]->paddr, &cma_obj[1]->paddr,
+                        &cma_obj[2]->paddr, x, y);
+                break;
+        default:
+                dev_dbg(ipu_plane->base.dev->dev, "phys = %pad, x = %d, y = %d",
+                        &cma_obj[0]->paddr, x, y);
+                break;
+        }
+
         if (ipu_plane->enabled) {
                 active = ipu_idmac_get_current_buffer(ipu_plane->ipu_ch);
                 ipu_cpmem_set_buffer(ipu_plane->ipu_ch, !active, eba);
@@ -201,12 +280,6 @@ int ipu_plane_mode_set(struct ipu_plane *ipu_plane, struct drm_crtc *crtc,
                 }
         }
 
-        ret = ipu_dmfc_init_channel(ipu_plane->dmfc, crtc_w);
-        if (ret) {
-                dev_err(dev, "initializing dmfc channel failed with %d\n", ret);
-                return ret;
-        }
-
         ret = ipu_dmfc_alloc_bandwidth(ipu_plane->dmfc,
                         calc_bandwidth(crtc_w, crtc_h,
                                        calc_vref(mode)), 64);
@@ -215,6 +288,8 @@ int ipu_plane_mode_set(struct ipu_plane *ipu_plane, struct drm_crtc *crtc,
                 return ret;
         }
 
+        ipu_dmfc_config_wait4eot(ipu_plane->dmfc, crtc_w);
+
         ipu_cpmem_zero(ipu_plane->ipu_ch);
         ipu_cpmem_set_resolution(ipu_plane->ipu_ch, src_w, src_h);
         ret = ipu_cpmem_set_fmt(ipu_plane->ipu_ch, fb->pixel_format);
@@ -233,6 +308,18 @@ int ipu_plane_mode_set(struct ipu_plane *ipu_plane, struct drm_crtc *crtc,
         if (interlaced)
                 ipu_cpmem_interlaced_scan(ipu_plane->ipu_ch, fb->pitches[0]);
 
+        if (fb->pixel_format == DRM_FORMAT_YUV420) {
+                ipu_cpmem_set_yuv_planar_full(ipu_plane->ipu_ch,
+                                              ipu_plane->stride[1],
+                                              ipu_plane->u_offset,
+                                              ipu_plane->v_offset);
+        } else if (fb->pixel_format == DRM_FORMAT_YVU420) {
+                ipu_cpmem_set_yuv_planar_full(ipu_plane->ipu_ch,
+                                              ipu_plane->stride[1],
+                                              ipu_plane->v_offset,
+                                              ipu_plane->u_offset);
+        }
+
         ipu_plane->w = src_w;
         ipu_plane->h = src_h;
 
diff --git a/drivers/gpu/drm/imx/ipuv3-plane.h b/drivers/gpu/drm/imx/ipuv3-plane.h
index 3a443b413c60..4448fd4ad4eb 100644
--- a/drivers/gpu/drm/imx/ipuv3-plane.h
+++ b/drivers/gpu/drm/imx/ipuv3-plane.h
@@ -29,6 +29,10 @@ struct ipu_plane {
         int                     w;
         int                     h;
 
+        unsigned int            u_offset;
+        unsigned int            v_offset;
+        unsigned int            stride[2];
+
         bool                    enabled;
 };
 
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h b/drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h
index 16641cec18a2..b5370cb56e3c 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h
@@ -11,6 +11,7 @@ struct nvkm_device_tegra {
 
         struct reset_control *rst;
         struct clk *clk;
+        struct clk *clk_ref;
         struct clk *clk_pwr;
 
         struct regulator *vdd;
@@ -36,6 +37,10 @@ struct nvkm_device_tegra_func {
          * bypassed). A value of 0 means an IOMMU is never used.
          */
         u8 iommu_bit;
+        /*
+         * Whether the chip requires a reference clock
+         */
+        bool require_ref_clk;
 };
 
 int nvkm_device_tegra_new(const struct nvkm_device_tegra_func *,
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c
index ae96ebc490fb..e81aefe5ffa7 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.c
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
@@ -1276,18 +1276,18 @@ nouveau_connector_create(struct drm_device *dev, int index)
                 break;
         default:
                 if (disp->dithering_mode) {
+                        nv_connector->dithering_mode = DITHERING_MODE_AUTO;
                         drm_object_attach_property(&connector->base,
                                                    disp->dithering_mode,
                                                    nv_connector->
                                                    dithering_mode);
-                        nv_connector->dithering_mode = DITHERING_MODE_AUTO;
                 }
                 if (disp->dithering_depth) {
+                        nv_connector->dithering_depth = DITHERING_DEPTH_AUTO;
                         drm_object_attach_property(&connector->base,
                                                    disp->dithering_depth,
                                                    nv_connector->
                                                    dithering_depth);
-                        nv_connector->dithering_depth = DITHERING_DEPTH_AUTO;
                 }
                 break;
         }
diff --git a/drivers/gpu/drm/nouveau/nouveau_platform.c b/drivers/gpu/drm/nouveau/nouveau_platform.c
index 2dfe58af12e4..4c4cc2260257 100644
--- a/drivers/gpu/drm/nouveau/nouveau_platform.c
+++ b/drivers/gpu/drm/nouveau/nouveau_platform.c
@@ -55,6 +55,11 @@ static const struct nvkm_device_tegra_func gk20a_platform_data = {
         .iommu_bit = 34,
 };
 
+static const struct nvkm_device_tegra_func gm20b_platform_data = {
+        .iommu_bit = 34,
+        .require_ref_clk = true,
+};
+
 static const struct of_device_id nouveau_platform_match[] = {
         {
                 .compatible = "nvidia,gk20a",
@@ -62,7 +67,7 @@ static const struct of_device_id nouveau_platform_match[] = {
         },
         {
                 .compatible = "nvidia,gm20b",
-                .data = &gk20a_platform_data,
+                .data = &gm20b_platform_data,
         },
         { }
 };
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
index 9afa5f3e3c1c..ec12efb4689a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
@@ -35,6 +35,11 @@ nvkm_device_tegra_power_up(struct nvkm_device_tegra *tdev)
         ret = clk_prepare_enable(tdev->clk);
         if (ret)
                 goto err_clk;
+        if (tdev->clk_ref) {
+                ret = clk_prepare_enable(tdev->clk_ref);
+                if (ret)
+                        goto err_clk_ref;
+        }
         ret = clk_prepare_enable(tdev->clk_pwr);
         if (ret)
                 goto err_clk_pwr;
@@ -57,6 +62,9 @@ nvkm_device_tegra_power_up(struct nvkm_device_tegra *tdev)
 err_clamp:
         clk_disable_unprepare(tdev->clk_pwr);
 err_clk_pwr:
+        if (tdev->clk_ref)
+                clk_disable_unprepare(tdev->clk_ref);
+err_clk_ref:
         clk_disable_unprepare(tdev->clk);
 err_clk:
         regulator_disable(tdev->vdd);
@@ -71,6 +79,8 @@ nvkm_device_tegra_power_down(struct nvkm_device_tegra *tdev)
         udelay(10);
 
         clk_disable_unprepare(tdev->clk_pwr);
+        if (tdev->clk_ref)
+                clk_disable_unprepare(tdev->clk_ref);
         clk_disable_unprepare(tdev->clk);
         udelay(10);
 
@@ -274,6 +284,13 @@ nvkm_device_tegra_new(const struct nvkm_device_tegra_func *func,
                 goto free;
         }
 
+        if (func->require_ref_clk)
+                tdev->clk_ref = devm_clk_get(&pdev->dev, "ref");
+        if (IS_ERR(tdev->clk_ref)) {
+                ret = PTR_ERR(tdev->clk_ref);
+                goto free;
+        }
+
         tdev->clk_pwr = devm_clk_get(&pdev->dev, "pwr");
         if (IS_ERR(tdev->clk_pwr)) {
                 ret = PTR_ERR(tdev->clk_pwr);
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
index c56a886229f1..b2de290da16f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
@@ -1832,6 +1832,8 @@ gf100_gr_init(struct gf100_gr *gr)
 
         gf100_gr_mmio(gr, gr->func->mmio);
 
+        nvkm_mask(device, TPC_UNIT(0, 0, 0x05c), 0x00000001, 0x00000001);
+
         memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
         for (i = 0, gpc = -1; i < gr->tpc_total; i++) {
                 do {
diff --git a/drivers/gpu/drm/qxl/qxl_display.c b/drivers/gpu/drm/qxl/qxl_display.c
index 43e5f503d1c5..030409a3ee4e 100644
--- a/drivers/gpu/drm/qxl/qxl_display.c
+++ b/drivers/gpu/drm/qxl/qxl_display.c
@@ -375,10 +375,15 @@ static int qxl_crtc_cursor_set2(struct drm_crtc *crtc,
 
         qxl_bo_kunmap(user_bo);
 
+        qcrtc->cur_x += qcrtc->hot_spot_x - hot_x;
+        qcrtc->cur_y += qcrtc->hot_spot_y - hot_y;
+        qcrtc->hot_spot_x = hot_x;
+        qcrtc->hot_spot_y = hot_y;
+
         cmd = (struct qxl_cursor_cmd *)qxl_release_map(qdev, release);
         cmd->type = QXL_CURSOR_SET;
-        cmd->u.set.position.x = qcrtc->cur_x;
-        cmd->u.set.position.y = qcrtc->cur_y;
+        cmd->u.set.position.x = qcrtc->cur_x + qcrtc->hot_spot_x;
+        cmd->u.set.position.y = qcrtc->cur_y + qcrtc->hot_spot_y;
 
         cmd->u.set.shape = qxl_bo_physical_address(qdev, cursor_bo, 0);
 
@@ -441,8 +446,8 @@ static int qxl_crtc_cursor_move(struct drm_crtc *crtc,
 
         cmd = (struct qxl_cursor_cmd *)qxl_release_map(qdev, release);
         cmd->type = QXL_CURSOR_MOVE;
-        cmd->u.position.x = qcrtc->cur_x;
-        cmd->u.position.y = qcrtc->cur_y;
+        cmd->u.position.x = qcrtc->cur_x + qcrtc->hot_spot_x;
+        cmd->u.position.y = qcrtc->cur_y + qcrtc->hot_spot_y;
         qxl_release_unmap(qdev, release, &cmd->release_info);
 
         qxl_push_cursor_ring_release(qdev, release, QXL_CMD_CURSOR, false);
diff --git a/drivers/gpu/drm/qxl/qxl_drv.h b/drivers/gpu/drm/qxl/qxl_drv.h
index 6e6b9b1519b8..3f3897eb458c 100644
--- a/drivers/gpu/drm/qxl/qxl_drv.h
+++ b/drivers/gpu/drm/qxl/qxl_drv.h
@@ -135,6 +135,8 @@ struct qxl_crtc {
         int index;
         int cur_x;
         int cur_y;
+        int hot_spot_x;
+        int hot_spot_y;
 };
 
 struct qxl_output {
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index cf61e0856f4a..b80b08f71cb4 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -275,13 +275,15 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
                 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
                         atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
                 atombios_blank_crtc(crtc, ATOM_DISABLE);
-                drm_vblank_on(dev, radeon_crtc->crtc_id);
+                if (dev->num_crtcs > radeon_crtc->crtc_id)
+                        drm_vblank_on(dev, radeon_crtc->crtc_id);
                 radeon_crtc_load_lut(crtc);
                 break;
         case DRM_MODE_DPMS_STANDBY:
         case DRM_MODE_DPMS_SUSPEND:
         case DRM_MODE_DPMS_OFF:
-                drm_vblank_off(dev, radeon_crtc->crtc_id);
+                if (dev->num_crtcs > radeon_crtc->crtc_id)
+                        drm_vblank_off(dev, radeon_crtc->crtc_id);
                 if (radeon_crtc->enabled)
                         atombios_blank_crtc(crtc, ATOM_ENABLE);
                 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 76c4bdf21b20..34f7a29d9366 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -2608,10 +2608,152 @@ static void evergreen_agp_enable(struct radeon_device *rdev)
         WREG32(VM_CONTEXT1_CNTL, 0);
 }
 
+static const unsigned ni_dig_offsets[] =
+{
+        NI_DIG0_REGISTER_OFFSET,
+        NI_DIG1_REGISTER_OFFSET,
+        NI_DIG2_REGISTER_OFFSET,
+        NI_DIG3_REGISTER_OFFSET,
+        NI_DIG4_REGISTER_OFFSET,
+        NI_DIG5_REGISTER_OFFSET
+};
+
+static const unsigned ni_tx_offsets[] =
+{
+        NI_DCIO_UNIPHY0_UNIPHY_TX_CONTROL1,
+        NI_DCIO_UNIPHY1_UNIPHY_TX_CONTROL1,
+        NI_DCIO_UNIPHY2_UNIPHY_TX_CONTROL1,
+        NI_DCIO_UNIPHY3_UNIPHY_TX_CONTROL1,
+        NI_DCIO_UNIPHY4_UNIPHY_TX_CONTROL1,
+        NI_DCIO_UNIPHY5_UNIPHY_TX_CONTROL1
+};
+
+static const unsigned evergreen_dp_offsets[] =
+{
+        EVERGREEN_DP0_REGISTER_OFFSET,
+        EVERGREEN_DP1_REGISTER_OFFSET,
+        EVERGREEN_DP2_REGISTER_OFFSET,
+        EVERGREEN_DP3_REGISTER_OFFSET,
+        EVERGREEN_DP4_REGISTER_OFFSET,
+        EVERGREEN_DP5_REGISTER_OFFSET
+};
+
+
+/*
+ * Assumption is that EVERGREEN_CRTC_MASTER_EN enable for requested crtc
+ * We go from crtc to connector and it is not relible  since it
+ * should be an opposite direction .If crtc is enable then
+ * find the dig_fe which selects this crtc and insure that it enable.
+ * if such dig_fe is found then find dig_be which selects found dig_be and
+ * insure that it enable and in DP_SST mode.
+ * if UNIPHY_PLL_CONTROL1.enable then we should disconnect timing
+ * from dp symbols clocks .
+ */
+static bool evergreen_is_dp_sst_stream_enabled(struct radeon_device *rdev,
+                                               unsigned crtc_id, unsigned *ret_dig_fe)
+{
+        unsigned i;
+        unsigned dig_fe;
+        unsigned dig_be;
+        unsigned dig_en_be;
+        unsigned uniphy_pll;
+        unsigned digs_fe_selected;
+        unsigned dig_be_mode;
+        unsigned dig_fe_mask;
+        bool is_enabled = false;
+        bool found_crtc = false;
+
+        /* loop through all running dig_fe to find selected crtc */
+        for (i = 0; i < ARRAY_SIZE(ni_dig_offsets); i++) {
+                dig_fe = RREG32(NI_DIG_FE_CNTL + ni_dig_offsets[i]);
+                if (dig_fe & NI_DIG_FE_CNTL_SYMCLK_FE_ON &&
+                    crtc_id == NI_DIG_FE_CNTL_SOURCE_SELECT(dig_fe)) {
+                        /* found running pipe */
+                        found_crtc = true;
+                        dig_fe_mask = 1 << i;
+                        dig_fe = i;
+                        break;
+                }
+        }
+
+        if (found_crtc) {
+                /* loop through all running dig_be to find selected dig_fe */
+                for (i = 0; i < ARRAY_SIZE(ni_dig_offsets); i++) {
+                        dig_be = RREG32(NI_DIG_BE_CNTL + ni_dig_offsets[i]);
+                        /* if dig_fe_selected by dig_be? */
+                        digs_fe_selected = NI_DIG_BE_CNTL_FE_SOURCE_SELECT(dig_be);
+                        dig_be_mode = NI_DIG_FE_CNTL_MODE(dig_be);
+                        if (dig_fe_mask &  digs_fe_selected &&
+                            /* if dig_be in sst mode? */
+                            dig_be_mode == NI_DIG_BE_DPSST) {
+                                dig_en_be = RREG32(NI_DIG_BE_EN_CNTL +
+                                                   ni_dig_offsets[i]);
+                                uniphy_pll = RREG32(NI_DCIO_UNIPHY0_PLL_CONTROL1 +
+                                                    ni_tx_offsets[i]);
+                                /* dig_be enable and tx is running */
+                                if (dig_en_be & NI_DIG_BE_EN_CNTL_ENABLE &&
+                                    dig_en_be & NI_DIG_BE_EN_CNTL_SYMBCLK_ON &&
+                                    uniphy_pll & NI_DCIO_UNIPHY0_PLL_CONTROL1_ENABLE) {
+                                        is_enabled = true;
+                                        *ret_dig_fe = dig_fe;
+                                        break;
+                                }
+                        }
+                }
+        }
+
+        return is_enabled;
+}
+
+/*
+ * Blank dig when in dp sst mode
+ * Dig ignores crtc timing
+ */
+static void evergreen_blank_dp_output(struct radeon_device *rdev,
+                                      unsigned dig_fe)
+{
+        unsigned stream_ctrl;
+        unsigned fifo_ctrl;
+        unsigned counter = 0;
+
+        if (dig_fe >= ARRAY_SIZE(evergreen_dp_offsets)) {
+                DRM_ERROR("invalid dig_fe %d\n", dig_fe);
+                return;
+        }
+
+        stream_ctrl = RREG32(EVERGREEN_DP_VID_STREAM_CNTL +
+                             evergreen_dp_offsets[dig_fe]);
+        if (!(stream_ctrl & EVERGREEN_DP_VID_STREAM_CNTL_ENABLE)) {
+                DRM_ERROR("dig %d , should be enable\n", dig_fe);
+                return;
+        }
+
+        stream_ctrl &=~EVERGREEN_DP_VID_STREAM_CNTL_ENABLE;
+        WREG32(EVERGREEN_DP_VID_STREAM_CNTL +
+               evergreen_dp_offsets[dig_fe], stream_ctrl);
+
+        stream_ctrl = RREG32(EVERGREEN_DP_VID_STREAM_CNTL +
+                             evergreen_dp_offsets[dig_fe]);
+        while (counter < 32 && stream_ctrl & EVERGREEN_DP_VID_STREAM_STATUS) {
+                msleep(1);
+                counter++;
+                stream_ctrl = RREG32(EVERGREEN_DP_VID_STREAM_CNTL +
+                                     evergreen_dp_offsets[dig_fe]);
+        }
+        if (counter >= 32 )
+                DRM_ERROR("counter exceeds %d\n", counter);
+
+        fifo_ctrl = RREG32(EVERGREEN_DP_STEER_FIFO + evergreen_dp_offsets[dig_fe]);
+        fifo_ctrl |= EVERGREEN_DP_STEER_FIFO_RESET;
+        WREG32(EVERGREEN_DP_STEER_FIFO + evergreen_dp_offsets[dig_fe], fifo_ctrl);
+
+}
+
 void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
 {
         u32 crtc_enabled, tmp, frame_count, blackout;
         int i, j;
+        unsigned dig_fe;
 
         if (!ASIC_IS_NODCE(rdev)) {
                 save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
@@ -2651,7 +2793,17 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav
                                         break;
                                 udelay(1);
                         }
-
+                        /*we should disable dig if it drives dp sst*/
+                        /*but we are in radeon_device_init and the topology is unknown*/
+                        /*and it is available after radeon_modeset_init*/
+                        /*the following method radeon_atom_encoder_dpms_dig*/
+                        /*does the job if we initialize it properly*/
+                        /*for now we do it this manually*/
+                        /**/
+                        if (ASIC_IS_DCE5(rdev) &&
+                            evergreen_is_dp_sst_stream_enabled(rdev, i ,&dig_fe))
+                                evergreen_blank_dp_output(rdev, dig_fe);
+                        /*we could remove 6 lines below*/
                         /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
                         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
diff --git a/drivers/gpu/drm/radeon/evergreen_reg.h b/drivers/gpu/drm/radeon/evergreen_reg.h
index aa939dfed3a3..b436badf9efa 100644
--- a/drivers/gpu/drm/radeon/evergreen_reg.h
+++ b/drivers/gpu/drm/radeon/evergreen_reg.h
@@ -250,8 +250,43 @@
 
 /* HDMI blocks at 0x7030, 0x7c30, 0x10830, 0x11430, 0x12030, 0x12c30 */
 #define EVERGREEN_HDMI_BASE                             0x7030
+/*DIG block*/
+#define NI_DIG0_REGISTER_OFFSET                 (0x7000  - 0x7000)
+#define NI_DIG1_REGISTER_OFFSET                 (0x7C00  - 0x7000)
+#define NI_DIG2_REGISTER_OFFSET                 (0x10800 - 0x7000)
+#define NI_DIG3_REGISTER_OFFSET                 (0x11400 - 0x7000)
+#define NI_DIG4_REGISTER_OFFSET                 (0x12000 - 0x7000)
+#define NI_DIG5_REGISTER_OFFSET                 (0x12C00 - 0x7000)
+
+
+#define NI_DIG_FE_CNTL                               0x7000
+#       define NI_DIG_FE_CNTL_SOURCE_SELECT(x)        ((x) & 0x3)
+#       define NI_DIG_FE_CNTL_SYMCLK_FE_ON            (1<<24)
+
+
+#define NI_DIG_BE_CNTL                    0x7140
+#       define NI_DIG_BE_CNTL_FE_SOURCE_SELECT(x)     (((x) >> 8 ) & 0x3F)
+#       define NI_DIG_FE_CNTL_MODE(x)                 (((x) >> 16) & 0x7 )
+
+#define NI_DIG_BE_EN_CNTL                              0x7144
+#       define NI_DIG_BE_EN_CNTL_ENABLE               (1 << 0)
+#       define NI_DIG_BE_EN_CNTL_SYMBCLK_ON           (1 << 8)
+#       define NI_DIG_BE_DPSST 0
 
 /* Display Port block */
+#define EVERGREEN_DP0_REGISTER_OFFSET                 (0x730C  - 0x730C)
+#define EVERGREEN_DP1_REGISTER_OFFSET                 (0x7F0C  - 0x730C)
+#define EVERGREEN_DP2_REGISTER_OFFSET                 (0x10B0C - 0x730C)
+#define EVERGREEN_DP3_REGISTER_OFFSET                 (0x1170C - 0x730C)
+#define EVERGREEN_DP4_REGISTER_OFFSET                 (0x1230C - 0x730C)
+#define EVERGREEN_DP5_REGISTER_OFFSET                 (0x12F0C - 0x730C)
+
+
+#define EVERGREEN_DP_VID_STREAM_CNTL                    0x730C
+#       define EVERGREEN_DP_VID_STREAM_CNTL_ENABLE     (1 << 0)
+#       define EVERGREEN_DP_VID_STREAM_STATUS          (1 <<16)
+#define EVERGREEN_DP_STEER_FIFO                         0x7310
+#       define EVERGREEN_DP_STEER_FIFO_RESET           (1 << 0)
 #define EVERGREEN_DP_SEC_CNTL                           0x7280
 #       define EVERGREEN_DP_SEC_STREAM_ENABLE           (1 << 0)
 #       define EVERGREEN_DP_SEC_ASP_ENABLE              (1 << 4)
@@ -266,4 +301,15 @@
 #       define EVERGREEN_DP_SEC_N_BASE_MULTIPLE(x)      (((x) & 0xf) << 24)
 #       define EVERGREEN_DP_SEC_SS_EN                   (1 << 28)
 
+/*DCIO_UNIPHY block*/
+#define NI_DCIO_UNIPHY0_UNIPHY_TX_CONTROL1            (0x6600  -0x6600)
+#define NI_DCIO_UNIPHY1_UNIPHY_TX_CONTROL1            (0x6640  -0x6600)
+#define NI_DCIO_UNIPHY2_UNIPHY_TX_CONTROL1            (0x6680 - 0x6600)
+#define NI_DCIO_UNIPHY3_UNIPHY_TX_CONTROL1            (0x66C0 - 0x6600)
+#define NI_DCIO_UNIPHY4_UNIPHY_TX_CONTROL1            (0x6700 - 0x6600)
+#define NI_DCIO_UNIPHY5_UNIPHY_TX_CONTROL1            (0x6740 - 0x6600)
+
+#define NI_DCIO_UNIPHY0_PLL_CONTROL1                   0x6618
+#       define NI_DCIO_UNIPHY0_PLL_CONTROL1_ENABLE     (1 << 0)
+
 #endif
diff --git a/drivers/gpu/drm/radeon/ni_reg.h b/drivers/gpu/drm/radeon/ni_reg.h
index da310a70c0f0..827ccc87cbc3 100644
--- a/drivers/gpu/drm/radeon/ni_reg.h
+++ b/drivers/gpu/drm/radeon/ni_reg.h
@@ -109,6 +109,8 @@
 #define NI_DP_MSE_SAT2                                 0x7398
 
 #define NI_DP_MSE_SAT_UPDATE                           0x739c
+#       define NI_DP_MSE_SAT_UPDATE_MASK               0x3
+#       define NI_DP_MSE_16_MTP_KEEPOUT                0x100
 
 #define NI_DIG_BE_CNTL                                 0x7140
 #       define NI_DIG_FE_SOURCE_SELECT(x)              (((x) & 0x7f) << 8)
diff --git a/drivers/gpu/drm/radeon/radeon_atpx_handler.c b/drivers/gpu/drm/radeon/radeon_atpx_handler.c
index fd8c4d317e60..95f4fea89302 100644
--- a/drivers/gpu/drm/radeon/radeon_atpx_handler.c
+++ b/drivers/gpu/drm/radeon/radeon_atpx_handler.c
@@ -62,10 +62,6 @@ bool radeon_has_atpx(void) {
         return radeon_atpx_priv.atpx_detected;
 }
 
-bool radeon_has_atpx_dgpu_power_cntl(void) {
-        return radeon_atpx_priv.atpx.functions.power_cntl;
-}
-
 /**
  * radeon_atpx_call - call an ATPX method
  *
@@ -145,6 +141,13 @@ static void radeon_atpx_parse_functions(struct radeon_atpx_functions *f, u32 mas
  */
 static int radeon_atpx_validate(struct radeon_atpx *atpx)
 {
+        /* make sure required functions are enabled */
+        /* dGPU power control is required */
+        if (atpx->functions.power_cntl == false) {
+                printk("ATPX dGPU power cntl not present, forcing\n");
+                atpx->functions.power_cntl = true;
+        }
+
         if (atpx->functions.px_params) {
                 union acpi_object *info;
                 struct atpx_px_params output;
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index cfcc099c537d..81a63d7f5cd9 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -2002,10 +2002,12 @@ radeon_add_atom_connector(struct drm_device *dev,
                                                    rdev->mode_info.dither_property,
                                                    RADEON_FMT_DITHER_DISABLE);
 
-                        if (radeon_audio != 0)
+                        if (radeon_audio != 0) {
                                 drm_object_attach_property(&radeon_connector->base.base,
                                                            rdev->mode_info.audio_property,
                                                            RADEON_AUDIO_AUTO);
+                                radeon_connector->audio = RADEON_AUDIO_AUTO;
+                        }
                         if (ASIC_IS_DCE5(rdev))
                                 drm_object_attach_property(&radeon_connector->base.base,
                                                            rdev->mode_info.output_csc_property,
@@ -2130,6 +2132,7 @@ radeon_add_atom_connector(struct drm_device *dev,
                                 drm_object_attach_property(&radeon_connector->base.base,
                                                            rdev->mode_info.audio_property,
                                                            RADEON_AUDIO_AUTO);
+                                radeon_connector->audio = RADEON_AUDIO_AUTO;
                         }
                         if (connector_type == DRM_MODE_CONNECTOR_DVII) {
                                 radeon_connector->dac_load_detect = true;
@@ -2185,6 +2188,7 @@ radeon_add_atom_connector(struct drm_device *dev,
                                 drm_object_attach_property(&radeon_connector->base.base,
                                                            rdev->mode_info.audio_property,
                                                            RADEON_AUDIO_AUTO);
+                                radeon_connector->audio = RADEON_AUDIO_AUTO;
                         }
                         if (ASIC_IS_DCE5(rdev))
                                 drm_object_attach_property(&radeon_connector->base.base,
@@ -2237,6 +2241,7 @@ radeon_add_atom_connector(struct drm_device *dev,
                                 drm_object_attach_property(&radeon_connector->base.base,
                                                            rdev->mode_info.audio_property,
                                                            RADEON_AUDIO_AUTO);
+                                radeon_connector->audio = RADEON_AUDIO_AUTO;
                         }
                         if (ASIC_IS_DCE5(rdev))
                                 drm_object_attach_property(&radeon_connector->base.base,
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 4fd1a961012d..d0826fb0434c 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -103,12 +103,6 @@ static const char radeon_family_name[][16] = {
         "LAST",
 };
 
-#if defined(CONFIG_VGA_SWITCHEROO)
-bool radeon_has_atpx_dgpu_power_cntl(void);
-#else
-static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; }
-#endif
-
 #define RADEON_PX_QUIRK_DISABLE_PX  (1 << 0)
 #define RADEON_PX_QUIRK_LONG_WAKEUP (1 << 1)
 
@@ -1305,9 +1299,9 @@ int radeon_device_init(struct radeon_device *rdev,
         }
         rdev->fence_context = fence_context_alloc(RADEON_NUM_RINGS);
 
-        DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
-                radeon_family_name[rdev->family], pdev->vendor, pdev->device,
-                pdev->subsystem_vendor, pdev->subsystem_device);
+        DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
+                 radeon_family_name[rdev->family], pdev->vendor, pdev->device,
+                 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
 
         /* mutex initialization are all done here so we
          * can recall function without having locking issues */
@@ -1439,7 +1433,7 @@ int radeon_device_init(struct radeon_device *rdev,
          * ignore it */
         vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
 
-        if ((rdev->flags & RADEON_IS_PX) && radeon_has_atpx_dgpu_power_cntl())
+        if (rdev->flags & RADEON_IS_PX)
                 runtime = true;
         vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops, runtime);
         if (runtime)
diff --git a/drivers/gpu/drm/radeon/radeon_dp_mst.c b/drivers/gpu/drm/radeon/radeon_dp_mst.c
index 43cffb526b0c..de504ea29c06 100644
--- a/drivers/gpu/drm/radeon/radeon_dp_mst.c
+++ b/drivers/gpu/drm/radeon/radeon_dp_mst.c
@@ -89,8 +89,16 @@ static int radeon_dp_mst_set_stream_attrib(struct radeon_encoder *primary,
         WREG32(NI_DP_MSE_SAT_UPDATE + primary->offset, 1);
 
         do {
+                unsigned value1, value2;
+                udelay(10);
                 temp = RREG32(NI_DP_MSE_SAT_UPDATE + primary->offset);
-        } while ((temp & 0x1) && retries++ < 10000);
+
+                value1 = temp & NI_DP_MSE_SAT_UPDATE_MASK;
+                value2 = temp & NI_DP_MSE_16_MTP_KEEPOUT;
+
+                if (!value1 && !value2)
+                        break;
+        } while (retries++ < 50);
 
         if (retries == 10000)
                 DRM_ERROR("timed out waitin for SAT update %d\n", primary->offset);
@@ -150,7 +158,7 @@ static int radeon_dp_mst_update_stream_attribs(struct radeon_connector *mst_conn
         return 0;
 }
 
-static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, uint32_t x, uint32_t y)
+static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, s64 avg_time_slots_per_mtp)
 {
         struct drm_device *dev = mst->base.dev;
         struct radeon_device *rdev = dev->dev_private;
@@ -158,6 +166,8 @@ static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, uint32_t x, ui
         uint32_t val, temp;
         uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe);
         int retries = 0;
+        uint32_t x = drm_fixp2int(avg_time_slots_per_mtp);
+        uint32_t y = drm_fixp2int_ceil((avg_time_slots_per_mtp - x) << 26);
 
         val = NI_DP_MSE_RATE_X(x) | NI_DP_MSE_RATE_Y(y);
 
@@ -165,6 +175,7 @@ static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, uint32_t x, ui
 
         do {
                 temp = RREG32(NI_DP_MSE_RATE_UPDATE + offset);
+                udelay(10);
         } while ((temp & 0x1) && (retries++ < 10000));
 
         if (retries >= 10000)
@@ -246,14 +257,8 @@ radeon_dp_mst_connector_destroy(struct drm_connector *connector)
         kfree(radeon_connector);
 }
 
-static int radeon_connector_dpms(struct drm_connector *connector, int mode)
-{
-        DRM_DEBUG_KMS("\n");
-        return 0;
-}
-
 static const struct drm_connector_funcs radeon_dp_mst_connector_funcs = {
-        .dpms = radeon_connector_dpms,
+        .dpms = drm_helper_connector_dpms,
         .detect = radeon_dp_mst_detect,
         .fill_modes = drm_helper_probe_single_connector_modes,
         .destroy = radeon_dp_mst_connector_destroy,
@@ -394,7 +399,7 @@ radeon_mst_encoder_dpms(struct drm_encoder *encoder, int mode)
         struct drm_crtc *crtc;
         struct radeon_crtc *radeon_crtc;
         int ret, slots;
-
+        s64 fixed_pbn, fixed_pbn_per_slot, avg_time_slots_per_mtp;
         if (!ASIC_IS_DCE5(rdev)) {
                 DRM_ERROR("got mst dpms on non-DCE5\n");
                 return;
@@ -456,7 +461,11 @@ radeon_mst_encoder_dpms(struct drm_encoder *encoder, int mode)
 
                 mst_enc->enc_active = true;
                 radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary);
-                radeon_dp_mst_set_vcp_size(radeon_encoder, slots, 0);
+
+                fixed_pbn = drm_int2fixp(mst_enc->pbn);
+                fixed_pbn_per_slot = drm_int2fixp(radeon_connector->mst_port->mst_mgr.pbn_div);
+                avg_time_slots_per_mtp = drm_fixp_div(fixed_pbn, fixed_pbn_per_slot);
+                radeon_dp_mst_set_vcp_size(radeon_encoder, avg_time_slots_per_mtp);
 
                 atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0,
                                             mst_enc->fe);
diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c
index 979f3bf65f2c..1e9304d1c88f 100644
--- a/drivers/gpu/drm/radeon/radeon_irq_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c
@@ -291,6 +291,8 @@ int radeon_irq_kms_init(struct radeon_device *rdev)
         if (r) {
                 return r;
         }
+        rdev->ddev->vblank_disable_allowed = true;
+
         /* enable msi */
         rdev->msi_enabled = 0;
 
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
index 24152dfef199..478d4099b0d0 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -331,13 +331,15 @@ static void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
                                                                          RADEON_CRTC_DISP_REQ_EN_B));
                         WREG32_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl, ~(mask | crtc_ext_cntl));
                 }
-                drm_vblank_on(dev, radeon_crtc->crtc_id);
+                if (dev->num_crtcs > radeon_crtc->crtc_id)
+                        drm_vblank_on(dev, radeon_crtc->crtc_id);
                 radeon_crtc_load_lut(crtc);
                 break;
         case DRM_MODE_DPMS_STANDBY:
         case DRM_MODE_DPMS_SUSPEND:
         case DRM_MODE_DPMS_OFF:
-                drm_vblank_off(dev, radeon_crtc->crtc_id);
+                if (dev->num_crtcs > radeon_crtc->crtc_id)
+                        drm_vblank_off(dev, radeon_crtc->crtc_id);
                 if (radeon_crtc->crtc_id)
                         WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask));
                 else {
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c
index c008312e1bcd..90f739478a1b 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -235,6 +235,8 @@ static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 {
         struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo);
 
+        if (radeon_ttm_tt_has_userptr(bo->ttm))
+                return -EPERM;
         return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp);
 }
 
@@ -615,7 +617,7 @@ static void radeon_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
                         set_page_dirty(page);
 
                 mark_page_accessed(page);
-                page_cache_release(page);
+                put_page(page);
         }
 
         sg_free_table(ttm->sg);
diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c
index af4df81c4e0c..e6abc09b67e3 100644
--- a/drivers/gpu/drm/radeon/si_dpm.c
+++ b/drivers/gpu/drm/radeon/si_dpm.c
@@ -2931,6 +2931,7 @@ static struct si_dpm_quirk si_dpm_quirk_list[] = {
         { PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 120000 },
         { PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 120000 },
         { PCI_VENDOR_ID_ATI, 0x6811, 0x148c, 0x2015, 0, 120000 },
+        { PCI_VENDOR_ID_ATI, 0x6810, 0x1682, 0x9275, 0, 120000 },
         { 0, 0, 0, 0 },
 };
 
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index 4cbf26555093..e3daafa1be13 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -230,22 +230,13 @@ EXPORT_SYMBOL(ttm_bo_del_sub_from_lru);
 
 void ttm_bo_move_to_lru_tail(struct ttm_buffer_object *bo)
 {
-        struct ttm_bo_device *bdev = bo->bdev;
-        struct ttm_mem_type_manager *man;
+        int put_count = 0;
 
         lockdep_assert_held(&bo->resv->lock.base);
 
-        if (bo->mem.placement & TTM_PL_FLAG_NO_EVICT) {
-                list_del_init(&bo->swap);
-                list_del_init(&bo->lru);
-
-        } else {
-                if (bo->ttm && !(bo->ttm->page_flags & TTM_PAGE_FLAG_SG))
-                        list_move_tail(&bo->swap, &bo->glob->swap_lru);
-
-                man = &bdev->man[bo->mem.mem_type];
-                list_move_tail(&bo->lru, &man->lru);
-        }
+        put_count = ttm_bo_del_from_lru(bo);
+        ttm_bo_list_ref_sub(bo, put_count, true);
+        ttm_bo_add_to_lru(bo);
 }
 EXPORT_SYMBOL(ttm_bo_move_to_lru_tail);
 
diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
index 4e19d0f9cc30..077ae9b2865d 100644
--- a/drivers/gpu/drm/ttm/ttm_tt.c
+++ b/drivers/gpu/drm/ttm/ttm_tt.c
@@ -311,7 +311,7 @@ int ttm_tt_swapin(struct ttm_tt *ttm)
                         goto out_err;
 
                 copy_highpage(to_page, from_page);
-                page_cache_release(from_page);
+                put_page(from_page);
         }
 
         if (!(ttm->page_flags & TTM_PAGE_FLAG_PERSISTENT_SWAP))
@@ -361,7 +361,7 @@ int ttm_tt_swapout(struct ttm_tt *ttm, struct file *persistent_swap_storage)
                 copy_highpage(to_page, from_page);
                 set_page_dirty(to_page);
                 mark_page_accessed(to_page);
-                page_cache_release(to_page);
+                put_page(to_page);
         }
 
         ttm_tt_unpopulate(ttm);
diff --git a/drivers/gpu/drm/via/via_dmablit.c b/drivers/gpu/drm/via/via_dmablit.c
index e797dfc07ae3..7e2a12c4fed2 100644
--- a/drivers/gpu/drm/via/via_dmablit.c
+++ b/drivers/gpu/drm/via/via_dmablit.c
@@ -188,7 +188,7 @@ via_free_sg_info(struct pci_dev *pdev, drm_via_sg_info_t *vsg)
                         if (NULL != (page = vsg->pages[i])) {
                                 if (!PageReserved(page) && (DMA_FROM_DEVICE == vsg->direction))
                                         SetPageDirty(page);
-                                page_cache_release(page);
+                                put_page(page);
                         }
                 }
         case dr_via_pages_alloc:
diff --git a/drivers/gpu/drm/virtio/virtgpu_display.c b/drivers/gpu/drm/virtio/virtgpu_display.c
index 4854dac87e24..5fd1fd06effc 100644
--- a/drivers/gpu/drm/virtio/virtgpu_display.c
+++ b/drivers/gpu/drm/virtio/virtgpu_display.c
@@ -267,11 +267,23 @@ static int virtio_gpu_crtc_atomic_check(struct drm_crtc *crtc,
         return 0;
 }
 
+static void virtio_gpu_crtc_atomic_flush(struct drm_crtc *crtc,
+                                         struct drm_crtc_state *old_state)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&crtc->dev->event_lock, flags);
+        if (crtc->state->event)
+                drm_crtc_send_vblank_event(crtc, crtc->state->event);
+        spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
+}
+
 static const struct drm_crtc_helper_funcs virtio_gpu_crtc_helper_funcs = {
         .enable        = virtio_gpu_crtc_enable,
         .disable       = virtio_gpu_crtc_disable,
         .mode_set_nofb = virtio_gpu_crtc_mode_set_nofb,
         .atomic_check  = virtio_gpu_crtc_atomic_check,
+        .atomic_flush  = virtio_gpu_crtc_atomic_flush,
 };
 
 static void virtio_gpu_enc_mode_set(struct drm_encoder *encoder,
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
index 723ba16c6084..1a1a87cbf109 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
@@ -3293,19 +3293,19 @@ static const struct vmw_cmd_entry vmw_cmd_entries[SVGA_3D_CMD_MAX] = {
                     &vmw_cmd_dx_cid_check, true, false, true),
         VMW_CMD_DEF(SVGA_3D_CMD_DX_DEFINE_QUERY, &vmw_cmd_dx_define_query,
                     true, false, true),
-        VMW_CMD_DEF(SVGA_3D_CMD_DX_DESTROY_QUERY, &vmw_cmd_ok,
+        VMW_CMD_DEF(SVGA_3D_CMD_DX_DESTROY_QUERY, &vmw_cmd_dx_cid_check,
                     true, false, true),
         VMW_CMD_DEF(SVGA_3D_CMD_DX_BIND_QUERY, &vmw_cmd_dx_bind_query,
                     true, false, true),
         VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_QUERY_OFFSET,
-                    &vmw_cmd_ok, true, false, true),
-        VMW_CMD_DEF(SVGA_3D_CMD_DX_BEGIN_QUERY, &vmw_cmd_ok,
+                    &vmw_cmd_dx_cid_check, true, false, true),
+        VMW_CMD_DEF(SVGA_3D_CMD_DX_BEGIN_QUERY, &vmw_cmd_dx_cid_check,
                     true, false, true),
-        VMW_CMD_DEF(SVGA_3D_CMD_DX_END_QUERY, &vmw_cmd_ok,
+        VMW_CMD_DEF(SVGA_3D_CMD_DX_END_QUERY, &vmw_cmd_dx_cid_check,
                     true, false, true),
         VMW_CMD_DEF(SVGA_3D_CMD_DX_READBACK_QUERY, &vmw_cmd_invalid,
                     true, false, true),
-        VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_PREDICATION, &vmw_cmd_invalid,
+        VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_PREDICATION, &vmw_cmd_dx_cid_check,
                     true, false, true),
         VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_VIEWPORTS, &vmw_cmd_dx_cid_check,
                     true, false, true),
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c b/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c
index 3b1faf7862a5..679a4cb98ee3 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c
@@ -573,9 +573,9 @@ static int vmw_fb_set_par(struct fb_info *info)
                 mode = old_mode;
                 old_mode = NULL;
         } else if (!vmw_kms_validate_mode_vram(vmw_priv,
-                                               mode->hdisplay *
-                                               (var->bits_per_pixel + 7) / 8,
-                                               mode->vdisplay)) {
+                                        mode->hdisplay *
+                                        DIV_ROUND_UP(var->bits_per_pixel, 8),
+                                        mode->vdisplay)) {
                 drm_mode_destroy(vmw_priv->dev, mode);
                 return -EINVAL;
         }
diff --git a/drivers/gpu/ipu-v3/ipu-cpmem.c b/drivers/gpu/ipu-v3/ipu-cpmem.c
index 883a314cd83a..6494a4d28171 100644
--- a/drivers/gpu/ipu-v3/ipu-cpmem.c
+++ b/drivers/gpu/ipu-v3/ipu-cpmem.c
@@ -395,60 +395,48 @@ void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format)
 EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_interleaved);
 
 void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch,
-                                   u32 pixel_format, int stride,
-                                   int u_offset, int v_offset)
+                                   unsigned int uv_stride,
+                                   unsigned int u_offset, unsigned int v_offset)
 {
-        switch (pixel_format) {
-        case V4L2_PIX_FMT_YUV420:
-        case V4L2_PIX_FMT_YUV422P:
-                ipu_ch_param_write_field(ch, IPU_FIELD_SLUV, (stride / 2) - 1);
-                ipu_ch_param_write_field(ch, IPU_FIELD_UBO, u_offset / 8);
-                ipu_ch_param_write_field(ch, IPU_FIELD_VBO, v_offset / 8);
-                break;
-        case V4L2_PIX_FMT_YVU420:
-                ipu_ch_param_write_field(ch, IPU_FIELD_SLUV, (stride / 2) - 1);
-                ipu_ch_param_write_field(ch, IPU_FIELD_UBO, v_offset / 8);
-                ipu_ch_param_write_field(ch, IPU_FIELD_VBO, u_offset / 8);
-                break;
-        case V4L2_PIX_FMT_NV12:
-        case V4L2_PIX_FMT_NV16:
-                ipu_ch_param_write_field(ch, IPU_FIELD_SLUV, stride - 1);
-                ipu_ch_param_write_field(ch, IPU_FIELD_UBO, u_offset / 8);
-                ipu_ch_param_write_field(ch, IPU_FIELD_VBO, u_offset / 8);
-                break;
-        }
+        ipu_ch_param_write_field(ch, IPU_FIELD_SLUV, uv_stride - 1);
+        ipu_ch_param_write_field(ch, IPU_FIELD_UBO, u_offset / 8);
+        ipu_ch_param_write_field(ch, IPU_FIELD_VBO, v_offset / 8);
 }
 EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_planar_full);
 
 void ipu_cpmem_set_yuv_planar(struct ipuv3_channel *ch,
                               u32 pixel_format, int stride, int height)
 {
-        int u_offset, v_offset;
+        int fourcc, u_offset, v_offset;
         int uv_stride = 0;
 
-        switch (pixel_format) {
-        case V4L2_PIX_FMT_YUV420:
-        case V4L2_PIX_FMT_YVU420:
+        fourcc = v4l2_pix_fmt_to_drm_fourcc(pixel_format);
+        switch (fourcc) {
+        case DRM_FORMAT_YUV420:
                 uv_stride = stride / 2;
                 u_offset = stride * height;
                 v_offset = u_offset + (uv_stride * height / 2);
-                ipu_cpmem_set_yuv_planar_full(ch, pixel_format, stride,
-                                              u_offset, v_offset);
                 break;
-        case V4L2_PIX_FMT_YUV422P:
+        case DRM_FORMAT_YVU420:
+                uv_stride = stride / 2;
+                v_offset = stride * height;
+                u_offset = v_offset + (uv_stride * height / 2);
+                break;
+        case DRM_FORMAT_YUV422:
                 uv_stride = stride / 2;
                 u_offset = stride * height;
                 v_offset = u_offset + (uv_stride * height);
-                ipu_cpmem_set_yuv_planar_full(ch, pixel_format, stride,
-                                              u_offset, v_offset);
                 break;
-        case V4L2_PIX_FMT_NV12:
-        case V4L2_PIX_FMT_NV16:
+        case DRM_FORMAT_NV12:
+        case DRM_FORMAT_NV16:
+                uv_stride = stride;
                 u_offset = stride * height;
-                ipu_cpmem_set_yuv_planar_full(ch, pixel_format, stride,
-                                              u_offset, 0);
+                v_offset = 0;
                 break;
+        default:
+                return;
         }
+        ipu_cpmem_set_yuv_planar_full(ch, uv_stride, u_offset, v_offset);
 }
 EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_planar);
 
@@ -684,17 +672,25 @@ int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image)
 
         switch (pix->pixelformat) {
         case V4L2_PIX_FMT_YUV420:
-        case V4L2_PIX_FMT_YVU420:
                 offset = Y_OFFSET(pix, image->rect.left, image->rect.top);
                 u_offset = U_OFFSET(pix, image->rect.left,
                                     image->rect.top) - offset;
                 v_offset = V_OFFSET(pix, image->rect.left,
                                     image->rect.top) - offset;
 
-                ipu_cpmem_set_yuv_planar_full(ch, pix->pixelformat,
-                                              pix->bytesperline,
+                ipu_cpmem_set_yuv_planar_full(ch, pix->bytesperline / 2,
                                               u_offset, v_offset);
                 break;
+        case V4L2_PIX_FMT_YVU420:
+                offset = Y_OFFSET(pix, image->rect.left, image->rect.top);
+                u_offset = U_OFFSET(pix, image->rect.left,
+                                    image->rect.top) - offset;
+                v_offset = V_OFFSET(pix, image->rect.left,
+                                    image->rect.top) - offset;
+
+                ipu_cpmem_set_yuv_planar_full(ch, pix->bytesperline / 2,
+                                              v_offset, u_offset);
+                break;
         case V4L2_PIX_FMT_YUV422P:
                 offset = Y_OFFSET(pix, image->rect.left, image->rect.top);
                 u_offset = U2_OFFSET(pix, image->rect.left,
@@ -702,8 +698,7 @@ int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image)
                 v_offset = V2_OFFSET(pix, image->rect.left,
                                      image->rect.top) - offset;
 
-                ipu_cpmem_set_yuv_planar_full(ch, pix->pixelformat,
-                                              pix->bytesperline,
+                ipu_cpmem_set_yuv_planar_full(ch, pix->bytesperline / 2,
                                               u_offset, v_offset);
                 break;
         case V4L2_PIX_FMT_NV12:
@@ -712,8 +707,7 @@ int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image)
                                      image->rect.top) - offset;
                 v_offset = 0;
 
-                ipu_cpmem_set_yuv_planar_full(ch, pix->pixelformat,
-                                              pix->bytesperline,
+                ipu_cpmem_set_yuv_planar_full(ch, pix->bytesperline,
                                               u_offset, v_offset);
                 break;
         case V4L2_PIX_FMT_NV16:
@@ -722,8 +716,7 @@ int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image)
                                       image->rect.top) - offset;
                 v_offset = 0;
 
-                ipu_cpmem_set_yuv_planar_full(ch, pix->pixelformat,
-                                              pix->bytesperline,
+                ipu_cpmem_set_yuv_planar_full(ch, pix->bytesperline,
                                               u_offset, v_offset);
                 break;
         case V4L2_PIX_FMT_UYVY:
diff --git a/drivers/gpu/ipu-v3/ipu-dmfc.c b/drivers/gpu/ipu-v3/ipu-dmfc.c
index 042c3958e2a0..837b1ec22800 100644
--- a/drivers/gpu/ipu-v3/ipu-dmfc.c
+++ b/drivers/gpu/ipu-v3/ipu-dmfc.c
@@ -350,11 +350,13 @@ out:
 }
 EXPORT_SYMBOL_GPL(ipu_dmfc_alloc_bandwidth);
 
-int ipu_dmfc_init_channel(struct dmfc_channel *dmfc, int width)
+void ipu_dmfc_config_wait4eot(struct dmfc_channel *dmfc, int width)
 {
         struct ipu_dmfc_priv *priv = dmfc->priv;
         u32 dmfc_gen1;
 
+        mutex_lock(&priv->mutex);
+
         dmfc_gen1 = readl(priv->base + DMFC_GENERAL1);
 
         if ((dmfc->slots * 64 * 4) / width > dmfc->data->max_fifo_lines)
@@ -364,9 +366,9 @@ int ipu_dmfc_init_channel(struct dmfc_channel *dmfc, int width)
 
         writel(dmfc_gen1, priv->base + DMFC_GENERAL1);
 
-        return 0;
+        mutex_unlock(&priv->mutex);
 }
-EXPORT_SYMBOL_GPL(ipu_dmfc_init_channel);
+EXPORT_SYMBOL_GPL(ipu_dmfc_config_wait4eot);
 
 struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipu_channel)
 {