diff options
author | Rex Zhu <Rex.Zhu@amd.com> | 2016-12-21 07:37:49 -0500 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2017-01-27 11:13:12 -0500 |
commit | e31e8a226ac93d3ef89b97715bb478d354f13b39 (patch) | |
tree | c3e0fb869156bad83cb3dc7e134a1212caaa698f /drivers/gpu | |
parent | 8e7afd34fd5fca66f59c959e0d97e57ad2c0b3ef (diff) |
drm/amd/powerplay: Configuring DIDT blocks only SQ enabled on Polaris11.
following firmware's request.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 21 |
1 files changed, 12 insertions, 9 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c index 2f6225e84867..2ea9c0e78689 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | |||
@@ -767,17 +767,10 @@ int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, | |||
767 | 767 | ||
768 | int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr) | 768 | int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr) |
769 | { | 769 | { |
770 | /* power tune caps Assume disabled */ | 770 | |
771 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | 771 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
772 | PHM_PlatformCaps_SQRamping); | 772 | PHM_PlatformCaps_SQRamping); |
773 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | 773 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
774 | PHM_PlatformCaps_DBRamping); | ||
775 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | ||
776 | PHM_PlatformCaps_TDRamping); | ||
777 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | ||
778 | PHM_PlatformCaps_TCPRamping); | ||
779 | |||
780 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | ||
781 | PHM_PlatformCaps_RegulatorHot); | 774 | PHM_PlatformCaps_RegulatorHot); |
782 | 775 | ||
783 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | 776 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
@@ -786,9 +779,19 @@ int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr) | |||
786 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | 779 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
787 | PHM_PlatformCaps_TablelessHardwareInterface); | 780 | PHM_PlatformCaps_TablelessHardwareInterface); |
788 | 781 | ||
789 | if ((hwmgr->chip_id == CHIP_POLARIS11) || (hwmgr->chip_id == CHIP_POLARIS12)) | 782 | |
783 | if (hwmgr->chip_id != CHIP_POLARIS10) | ||
790 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | 784 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
791 | PHM_PlatformCaps_SPLLShutdownSupport); | 785 | PHM_PlatformCaps_SPLLShutdownSupport); |
786 | |||
787 | if (hwmgr->chip_id != CHIP_POLARIS11) { | ||
788 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | ||
789 | PHM_PlatformCaps_DBRamping); | ||
790 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | ||
791 | PHM_PlatformCaps_TDRamping); | ||
792 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | ||
793 | PHM_PlatformCaps_TCPRamping); | ||
794 | } | ||
792 | return 0; | 795 | return 0; |
793 | } | 796 | } |
794 | 797 | ||