Merge branch 'drm-fixes-4.18' of git://people.freedesktop.org/~agd5f/linux into drm-fixes

A few display and GPUVM fixes for 4.18.

A few more fixes for 4.18. Two display fixes and a fix to avoid a segfault if
the GPU does not power up properly on resume.  These are on top of my pull
from earlier this week.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180712043820.2877-1-alexander.deucher@amd.com

9 files changed, 76 insertions, 41 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 82312a7bc6ad..9c85a90be293 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -927,6 +927,10 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
                 r = amdgpu_bo_vm_update_pte(p);
                 if (r)
                         return r;
+
+                r = reservation_object_reserve_shared(vm->root.base.bo->tbo.resv);
+                if (r)
+                        return r;
         }
 
         return amdgpu_cs_sync_rings(p);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index edf16b2b957a..fdcb498f6d19 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -107,6 +107,9 @@ static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
                 return;
         list_add_tail(&base->bo_list, &bo->va);
 
+        if (bo->tbo.type == ttm_bo_type_kernel)
+                list_move(&base->vm_status, &vm->relocated);
+
         if (bo->tbo.resv != vm->root.base.bo->tbo.resv)
                 return;
 
@@ -468,7 +471,6 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev,
                         pt->parent = amdgpu_bo_ref(parent->base.bo);
 
                         amdgpu_vm_bo_base_init(&entry->base, vm, pt);
-                        list_move(&entry->base.vm_status, &vm->relocated);
                 }
 
                 if (level < AMDGPU_VM_PTB) {
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 4304d9e408b8..ace9ad578ca0 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -83,22 +83,21 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
         enum i2c_mot_mode mot = (msg->request & DP_AUX_I2C_MOT) ?
                 I2C_MOT_TRUE : I2C_MOT_FALSE;
         enum ddc_result res;
-        uint32_t read_bytes = msg->size;
+        ssize_t read_bytes;
 
         if (WARN_ON(msg->size > 16))
                 return -E2BIG;
 
         switch (msg->request & ~DP_AUX_I2C_MOT) {
         case DP_AUX_NATIVE_READ:
-                res = dal_ddc_service_read_dpcd_data(
+                read_bytes = dal_ddc_service_read_dpcd_data(
                                 TO_DM_AUX(aux)->ddc_service,
                                 false,
                                 I2C_MOT_UNDEF,
                                 msg->address,
                                 msg->buffer,
-                                msg->size,
-                                &read_bytes);
-                break;
+                                msg->size);
+                return read_bytes;
         case DP_AUX_NATIVE_WRITE:
                 res = dal_ddc_service_write_dpcd_data(
                                 TO_DM_AUX(aux)->ddc_service,
@@ -109,15 +108,14 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
                                 msg->size);
                 break;
         case DP_AUX_I2C_READ:
-                res = dal_ddc_service_read_dpcd_data(
+                read_bytes = dal_ddc_service_read_dpcd_data(
                                 TO_DM_AUX(aux)->ddc_service,
                                 true,
                                 mot,
                                 msg->address,
                                 msg->buffer,
-                                msg->size,
-                                &read_bytes);
-                break;
+                                msg->size);
+                return read_bytes;
         case DP_AUX_I2C_WRITE:
                 res = dal_ddc_service_write_dpcd_data(
                                 TO_DM_AUX(aux)->ddc_service,
@@ -139,9 +137,7 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
                  r == DDC_RESULT_SUCESSFULL);
 #endif
 
-        if (res != DDC_RESULT_SUCESSFULL)
-                return -EIO;
-        return read_bytes;
+        return msg->size;
 }
 
 static enum drm_connector_status
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
index 5a3346124a01..5a2e952c5bea 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
@@ -255,8 +255,9 @@ static void pp_to_dc_clock_levels_with_latency(
                         DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
 
         for (i = 0; i < clk_level_info->num_levels; i++) {
-                DRM_DEBUG("DM_PPLIB:\t %d\n", pp_clks->data[i].clocks_in_khz);
-                clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz;
+                DRM_DEBUG("DM_PPLIB:\t %d in 10kHz\n", pp_clks->data[i].clocks_in_khz);
+                /* translate 10kHz to kHz */
+                clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz * 10;
                 clk_level_info->data[i].latency_in_us = pp_clks->data[i].latency_in_us;
         }
 }
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
index ae48d603ebd6..49c2face1e7a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
@@ -629,14 +629,13 @@ bool dal_ddc_service_query_ddc_data(
         return ret;
 }
 
-enum ddc_result dal_ddc_service_read_dpcd_data(
+ssize_t dal_ddc_service_read_dpcd_data(
         struct ddc_service *ddc,
         bool i2c,
         enum i2c_mot_mode mot,
         uint32_t address,
         uint8_t *data,
-        uint32_t len,
-        uint32_t *read)
+        uint32_t len)
 {
         struct aux_payload read_payload = {
                 .i2c_over_aux = i2c,
@@ -653,8 +652,6 @@ enum ddc_result dal_ddc_service_read_dpcd_data(
                 .mot = mot
         };
 
-        *read = 0;
-
         if (len > DEFAULT_AUX_MAX_DATA_SIZE) {
                 BREAK_TO_DEBUGGER();
                 return DDC_RESULT_FAILED_INVALID_OPERATION;
@@ -664,8 +661,7 @@ enum ddc_result dal_ddc_service_read_dpcd_data(
                 ddc->ctx->i2caux,
                 ddc->ddc_pin,
                 &command)) {
-                *read = command.payloads->length;
-                return DDC_RESULT_SUCESSFULL;
+                return (ssize_t)command.payloads->length;
         }
 
         return DDC_RESULT_FAILED_OPERATION;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
index b235a75355b8..bae752332a9f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
@@ -741,6 +741,29 @@ static struct mem_input_funcs dce_mi_funcs = {
         .mem_input_is_flip_pending = dce_mi_is_flip_pending
 };
 
+static struct mem_input_funcs dce112_mi_funcs = {
+        .mem_input_program_display_marks = dce112_mi_program_display_marks,
+        .allocate_mem_input = dce_mi_allocate_dmif,
+        .free_mem_input = dce_mi_free_dmif,
+        .mem_input_program_surface_flip_and_addr =
+                        dce_mi_program_surface_flip_and_addr,
+        .mem_input_program_pte_vm = dce_mi_program_pte_vm,
+        .mem_input_program_surface_config =
+                        dce_mi_program_surface_config,
+        .mem_input_is_flip_pending = dce_mi_is_flip_pending
+};
+
+static struct mem_input_funcs dce120_mi_funcs = {
+        .mem_input_program_display_marks = dce120_mi_program_display_marks,
+        .allocate_mem_input = dce_mi_allocate_dmif,
+        .free_mem_input = dce_mi_free_dmif,
+        .mem_input_program_surface_flip_and_addr =
+                        dce_mi_program_surface_flip_and_addr,
+        .mem_input_program_pte_vm = dce_mi_program_pte_vm,
+        .mem_input_program_surface_config =
+                        dce_mi_program_surface_config,
+        .mem_input_is_flip_pending = dce_mi_is_flip_pending
+};
 
 void dce_mem_input_construct(
         struct dce_mem_input *dce_mi,
@@ -769,7 +792,7 @@ void dce112_mem_input_construct(
         const struct dce_mem_input_mask *mi_mask)
 {
         dce_mem_input_construct(dce_mi, ctx, inst, regs, mi_shift, mi_mask);
-        dce_mi->base.funcs->mem_input_program_display_marks = dce112_mi_program_display_marks;
+        dce_mi->base.funcs = &dce112_mi_funcs;
 }
 
 void dce120_mem_input_construct(
@@ -781,5 +804,5 @@ void dce120_mem_input_construct(
         const struct dce_mem_input_mask *mi_mask)
 {
         dce_mem_input_construct(dce_mi, ctx, inst, regs, mi_shift, mi_mask);
-        dce_mi->base.funcs->mem_input_program_display_marks = dce120_mi_program_display_marks;
+        dce_mi->base.funcs = &dce120_mi_funcs;
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index 38ec0d609297..344dd2e69e7c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -678,9 +678,22 @@ bool dce100_validate_bandwidth(
         struct dc  *dc,
         struct dc_state *context)
 {
-        /* TODO implement when needed but for now hardcode max value*/
-        context->bw.dce.dispclk_khz = 681000;
-        context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER;
+        int i;
+        bool at_least_one_pipe = false;
+
+        for (i = 0; i < dc->res_pool->pipe_count; i++) {
+                if (context->res_ctx.pipe_ctx[i].stream)
+                        at_least_one_pipe = true;
+        }
+
+        if (at_least_one_pipe) {
+                /* TODO implement when needed but for now hardcode max value*/
+                context->bw.dce.dispclk_khz = 681000;
+                context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER;
+        } else {
+                context->bw.dce.dispclk_khz = 0;
+                context->bw.dce.yclk_khz = 0;
+        }
 
         return true;
 }
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
index 30b3a08b91be..090b7a8dd67b 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
@@ -102,14 +102,13 @@ bool dal_ddc_service_query_ddc_data(
                 uint8_t *read_buf,
                 uint32_t read_size);
 
-enum ddc_result dal_ddc_service_read_dpcd_data(
+ssize_t dal_ddc_service_read_dpcd_data(
                 struct ddc_service *ddc,
                 bool i2c,
                 enum i2c_mot_mode mot,
                 uint32_t address,
                 uint8_t *data,
-                uint32_t len,
-                uint32_t *read);
+                uint32_t len);
 
 enum ddc_result dal_ddc_service_write_dpcd_data(
                 struct ddc_service *ddc,
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
index d644a9bb9078..9f407c48d4f0 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
@@ -381,6 +381,7 @@ int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr)
         uint32_t fw_to_load;
         int result = 0;
         struct SMU_DRAMData_TOC *toc;
+        uint32_t num_entries = 0;
 
         if (!hwmgr->reload_fw) {
                 pr_info("skip reloading...\n");
@@ -422,41 +423,41 @@ int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr)
         }
 
         toc = (struct SMU_DRAMData_TOC *)smu_data->header;
-        toc->num_entries = 0;
         toc->structure_version = 1;
 
         PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-                                UCODE_ID_RLC_G, &toc->entry[toc->num_entries++]),
+                                UCODE_ID_RLC_G, &toc->entry[num_entries++]),
                                 "Failed to Get Firmware Entry.", return -EINVAL);
         PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-                                UCODE_ID_CP_CE, &toc->entry[toc->num_entries++]),
+                                UCODE_ID_CP_CE, &toc->entry[num_entries++]),
                                 "Failed to Get Firmware Entry.", return -EINVAL);
         PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-                                UCODE_ID_CP_PFP, &toc->entry[toc->num_entries++]),
+                                UCODE_ID_CP_PFP, &toc->entry[num_entries++]),
                                 "Failed to Get Firmware Entry.", return -EINVAL);
         PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-                                UCODE_ID_CP_ME, &toc->entry[toc->num_entries++]),
+                                UCODE_ID_CP_ME, &toc->entry[num_entries++]),
                                 "Failed to Get Firmware Entry.", return -EINVAL);
         PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-                                UCODE_ID_CP_MEC, &toc->entry[toc->num_entries++]),
+                                UCODE_ID_CP_MEC, &toc->entry[num_entries++]),
                                 "Failed to Get Firmware Entry.", return -EINVAL);
         PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-                                UCODE_ID_CP_MEC_JT1, &toc->entry[toc->num_entries++]),
+                                UCODE_ID_CP_MEC_JT1, &toc->entry[num_entries++]),
                                 "Failed to Get Firmware Entry.", return -EINVAL);
         PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-                                UCODE_ID_CP_MEC_JT2, &toc->entry[toc->num_entries++]),
+                                UCODE_ID_CP_MEC_JT2, &toc->entry[num_entries++]),
                                 "Failed to Get Firmware Entry.", return -EINVAL);
         PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-                                UCODE_ID_SDMA0, &toc->entry[toc->num_entries++]),
+                                UCODE_ID_SDMA0, &toc->entry[num_entries++]),
                                 "Failed to Get Firmware Entry.", return -EINVAL);
         PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-                                UCODE_ID_SDMA1, &toc->entry[toc->num_entries++]),
+                                UCODE_ID_SDMA1, &toc->entry[num_entries++]),
                                 "Failed to Get Firmware Entry.", return -EINVAL);
         if (!hwmgr->not_vf)
                 PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-                                UCODE_ID_MEC_STORAGE, &toc->entry[toc->num_entries++]),
+                                UCODE_ID_MEC_STORAGE, &toc->entry[num_entries++]),
                                 "Failed to Get Firmware Entry.", return -EINVAL);
 
+        toc->num_entries = num_entries;
         smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, upper_32_bits(smu_data->header_buffer.mc_addr));
         smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, lower_32_bits(smu_data->header_buffer.mc_addr));