diff options
| author | Christian König <christian.koenig@amd.com> | 2017-07-29 07:28:55 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-08-17 15:45:58 -0400 |
| commit | dbcca4aab1b2e1983e5432cb2a1d4f5f1d8b4750 (patch) | |
| tree | 4979072f50463591c9d84bcb3ed4ac9a0bafaad7 /drivers/gpu | |
| parent | a35ebc8c12cc724022f39b32ffb17f63ff16effd (diff) | |
drm/amdgpu: fix Vega10 HW config for 2MB pages
Those values weren't correct. This should result in quite some speedup.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 4 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c index 408723ef157c..6c8040e616c4 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | |||
| @@ -144,8 +144,8 @@ static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev) | |||
| 144 | WREG32_SOC15(GC, 0, mmVM_L2_CNTL2, tmp); | 144 | WREG32_SOC15(GC, 0, mmVM_L2_CNTL2, tmp); |
| 145 | 145 | ||
| 146 | tmp = mmVM_L2_CNTL3_DEFAULT; | 146 | tmp = mmVM_L2_CNTL3_DEFAULT; |
| 147 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); | 147 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); |
| 148 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 9); | 148 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 6); |
| 149 | WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, tmp); | 149 | WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, tmp); |
| 150 | 150 | ||
| 151 | tmp = mmVM_L2_CNTL4_DEFAULT; | 151 | tmp = mmVM_L2_CNTL4_DEFAULT; |
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c index ad8def3cc343..74cb647da30e 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | |||
| @@ -158,8 +158,8 @@ static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev) | |||
| 158 | WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp); | 158 | WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp); |
| 159 | 159 | ||
| 160 | tmp = mmVM_L2_CNTL3_DEFAULT; | 160 | tmp = mmVM_L2_CNTL3_DEFAULT; |
| 161 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); | 161 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); |
| 162 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 9); | 162 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 6); |
| 163 | WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, tmp); | 163 | WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, tmp); |
| 164 | 164 | ||
| 165 | tmp = mmVM_L2_CNTL4_DEFAULT; | 165 | tmp = mmVM_L2_CNTL4_DEFAULT; |