drm/i915/kbl: Add WaForGAMHang

Add this workaround for A0 and B0 revisions

References: HSD#2226935
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465309159-30531-19-git-send-email-mika.kuoppala@intel.com
(cherry picked from commit 0b2d0934edceff9905b1202d0e7e91f1b6228485)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>

1 files changed, 34 insertions, 2 deletions

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index cf18eace6690..3138d2fa6ea5 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1689,9 +1689,10 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
         struct intel_ringbuffer *ringbuf = request->ringbuf;
         struct intel_engine_cs *engine = ringbuf->engine;
         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
-        bool vf_flush_wa = false;
+        bool vf_flush_wa = false, dc_flush_wa = false;
         u32 flags = 0;
         int ret;
+        int len;
 
         flags |= PIPE_CONTROL_CS_STALL;
 
@@ -1718,9 +1719,21 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
                  */
                 if (IS_GEN9(engine->dev))
                         vf_flush_wa = true;
+
+                /* WaForGAMHang:kbl */
+                if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0))
+                        dc_flush_wa = true;
         }
 
-        ret = intel_ring_begin(request, vf_flush_wa ? 12 : 6);
+        len = 6;
+
+        if (vf_flush_wa)
+                len += 6;
+
+        if (dc_flush_wa)
+                len += 12;
+
+        ret = intel_ring_begin(request, len);
         if (ret)
                 return ret;
 
@@ -1733,12 +1746,31 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
                 intel_logical_ring_emit(ringbuf, 0);
         }
 
+        if (dc_flush_wa) {
+                intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
+                intel_logical_ring_emit(ringbuf, PIPE_CONTROL_DC_FLUSH_ENABLE);
+                intel_logical_ring_emit(ringbuf, 0);
+                intel_logical_ring_emit(ringbuf, 0);
+                intel_logical_ring_emit(ringbuf, 0);
+                intel_logical_ring_emit(ringbuf, 0);
+        }
+
         intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
         intel_logical_ring_emit(ringbuf, flags);
         intel_logical_ring_emit(ringbuf, scratch_addr);
         intel_logical_ring_emit(ringbuf, 0);
         intel_logical_ring_emit(ringbuf, 0);
         intel_logical_ring_emit(ringbuf, 0);
+
+        if (dc_flush_wa) {
+                intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
+                intel_logical_ring_emit(ringbuf, PIPE_CONTROL_CS_STALL);
+                intel_logical_ring_emit(ringbuf, 0);
+                intel_logical_ring_emit(ringbuf, 0);
+                intel_logical_ring_emit(ringbuf, 0);
+                intel_logical_ring_emit(ringbuf, 0);
+        }
+
         intel_logical_ring_advance(ringbuf);
 
         return 0;