diff options
author | David Francis <David.Francis@amd.com> | 2018-08-03 13:24:28 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2018-08-27 16:21:11 -0400 |
commit | 9bbf6a5341092e8a9b4e7b02bea6721e29ced9ef (patch) | |
tree | 5ae206b9b1da0be28df5a65e5a24500a868d1f08 /drivers/gpu | |
parent | ad908423ef86f1787b635a8830d49f50ff862295 (diff) |
drm/amd/display: Flatten unnecessary i2c functions
[Why]
The dce_i2c_hw code contained four funtcions that were only
called in one place and did not have a clearly delineated
purpose.
[How]
Inline these functions, keeping the same functionality.
This is not a functional change.
The functions disable_i2c_hw_engine and release_engine_dce_hw were
pulled into their respective callers.
The most interesting part of this change is the acquire functions.
dce_i2c_hw_engine_acquire_engine was pulled into
dce_i2c_engine_acquire_hw, and dce_i2c_engine_acquire_hw was pulled
into acquire_i2c_hw_engine.
Some notes to show that this change is not functional:
-Failure conditions in any function resulted in a cascade of calls that
ended in a 'return NULL'.
Those are replaced with a direct 'return NULL'.
-The variable result is the one from dce_i2c_hw_engine_acquire_engine.
The boolean result used as part of return logic was removed.
-As the second half of dce_i2c_hw_engine_acquire_engine is only executed
if that function is returning true and therefore exiting the do-while
loop in dce_i2c_engine_acquire_hw, those lines were moved outside
of the loop.
Signed-off-by: David Francis <David.Francis@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c | 111 |
1 files changed, 34 insertions, 77 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c index 2800d3fa49da..40f2d6e0b122 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c | |||
@@ -36,12 +36,6 @@ | |||
36 | #define FN(reg_name, field_name) \ | 36 | #define FN(reg_name, field_name) \ |
37 | dce_i2c_hw->shifts->field_name, dce_i2c_hw->masks->field_name | 37 | dce_i2c_hw->shifts->field_name, dce_i2c_hw->masks->field_name |
38 | 38 | ||
39 | static void disable_i2c_hw_engine( | ||
40 | struct dce_i2c_hw *dce_i2c_hw) | ||
41 | { | ||
42 | REG_UPDATE_N(SETUP, 1, FN(SETUP, DC_I2C_DDC1_ENABLE), 0); | ||
43 | } | ||
44 | |||
45 | static void execute_transaction( | 39 | static void execute_transaction( |
46 | struct dce_i2c_hw *dce_i2c_hw) | 40 | struct dce_i2c_hw *dce_i2c_hw) |
47 | { | 41 | { |
@@ -348,60 +342,40 @@ static void release_engine( | |||
348 | REG_UPDATE(DC_I2C_CONTROL, DC_I2C_SW_STATUS_RESET, 1); | 342 | REG_UPDATE(DC_I2C_CONTROL, DC_I2C_SW_STATUS_RESET, 1); |
349 | /* HW I2c engine - clock gating feature */ | 343 | /* HW I2c engine - clock gating feature */ |
350 | if (!dce_i2c_hw->engine_keep_power_up_count) | 344 | if (!dce_i2c_hw->engine_keep_power_up_count) |
351 | disable_i2c_hw_engine(dce_i2c_hw); | 345 | REG_UPDATE_N(SETUP, 1, FN(SETUP, DC_I2C_DDC1_ENABLE), 0); |
352 | 346 | ||
353 | } | 347 | } |
354 | 348 | ||
355 | static void release_engine_dce_hw( | 349 | struct dce_i2c_hw *acquire_i2c_hw_engine( |
356 | struct resource_pool *pool, | 350 | struct resource_pool *pool, |
357 | struct dce_i2c_hw *dce_i2c_hw) | ||
358 | { | ||
359 | pool->i2c_hw_buffer_in_use = false; | ||
360 | |||
361 | release_engine(dce_i2c_hw); | ||
362 | dal_ddc_close(dce_i2c_hw->ddc); | ||
363 | |||
364 | dce_i2c_hw->ddc = NULL; | ||
365 | } | ||
366 | |||
367 | bool dce_i2c_hw_engine_acquire_engine( | ||
368 | struct dce_i2c_hw *dce_i2c_hw, | ||
369 | struct ddc *ddc) | 351 | struct ddc *ddc) |
370 | { | 352 | { |
371 | 353 | uint32_t counter = 0; | |
372 | enum gpio_result result; | 354 | enum gpio_result result; |
373 | uint32_t current_speed; | 355 | uint32_t current_speed; |
356 | struct dce_i2c_hw *dce_i2c_hw = NULL; | ||
374 | 357 | ||
375 | result = dal_ddc_open(ddc, GPIO_MODE_HARDWARE, | 358 | if (!ddc) |
376 | GPIO_DDC_CONFIG_TYPE_MODE_I2C); | 359 | return NULL; |
377 | |||
378 | if (result != GPIO_RESULT_OK) | ||
379 | return false; | ||
380 | |||
381 | dce_i2c_hw->ddc = ddc; | ||
382 | |||
383 | |||
384 | current_speed = get_speed(dce_i2c_hw); | ||
385 | 360 | ||
386 | if (current_speed) | 361 | if (ddc->hw_info.hw_supported) { |
387 | dce_i2c_hw->original_speed = current_speed; | 362 | enum gpio_ddc_line line = dal_ddc_get_line(ddc); |
388 | 363 | ||
389 | return true; | 364 | if (line < pool->pipe_count) |
390 | } | 365 | dce_i2c_hw = pool->hw_i2cs[line]; |
366 | } | ||
391 | 367 | ||
392 | bool dce_i2c_engine_acquire_hw( | 368 | if (!dce_i2c_hw) |
393 | struct dce_i2c_hw *dce_i2c_hw, | 369 | return NULL; |
394 | struct ddc *ddc_handle) | ||
395 | { | ||
396 | 370 | ||
397 | uint32_t counter = 0; | 371 | if (pool->i2c_hw_buffer_in_use) |
398 | bool result; | 372 | return NULL; |
399 | 373 | ||
400 | do { | 374 | do { |
401 | result = dce_i2c_hw_engine_acquire_engine( | 375 | result = dal_ddc_open(ddc, GPIO_MODE_HARDWARE, |
402 | dce_i2c_hw, ddc_handle); | 376 | GPIO_DDC_CONFIG_TYPE_MODE_I2C); |
403 | 377 | ||
404 | if (result) | 378 | if (result == GPIO_RESULT_OK) |
405 | break; | 379 | break; |
406 | 380 | ||
407 | /* i2c_engine is busy by VBios, lets wait and retry */ | 381 | /* i2c_engine is busy by VBios, lets wait and retry */ |
@@ -411,45 +385,23 @@ bool dce_i2c_engine_acquire_hw( | |||
411 | ++counter; | 385 | ++counter; |
412 | } while (counter < 2); | 386 | } while (counter < 2); |
413 | 387 | ||
414 | if (result) { | 388 | if (result != GPIO_RESULT_OK) |
415 | if (!setup_engine(dce_i2c_hw)) { | ||
416 | release_engine(dce_i2c_hw); | ||
417 | result = false; | ||
418 | } | ||
419 | } | ||
420 | |||
421 | return result; | ||
422 | } | ||
423 | |||
424 | struct dce_i2c_hw *acquire_i2c_hw_engine( | ||
425 | struct resource_pool *pool, | ||
426 | struct ddc *ddc) | ||
427 | { | ||
428 | |||
429 | struct dce_i2c_hw *engine = NULL; | ||
430 | |||
431 | if (!ddc) | ||
432 | return NULL; | 389 | return NULL; |
433 | 390 | ||
434 | if (ddc->hw_info.hw_supported) { | 391 | dce_i2c_hw->ddc = ddc; |
435 | enum gpio_ddc_line line = dal_ddc_get_line(ddc); | ||
436 | |||
437 | if (line < pool->pipe_count) | ||
438 | engine = pool->hw_i2cs[line]; | ||
439 | } | ||
440 | 392 | ||
441 | if (!engine) | 393 | current_speed = get_speed(dce_i2c_hw); |
442 | return NULL; | ||
443 | 394 | ||
395 | if (current_speed) | ||
396 | dce_i2c_hw->original_speed = current_speed; | ||
444 | 397 | ||
445 | if (!pool->i2c_hw_buffer_in_use && | 398 | if (!setup_engine(dce_i2c_hw)) { |
446 | dce_i2c_engine_acquire_hw(engine, ddc)) { | 399 | release_engine(dce_i2c_hw); |
447 | pool->i2c_hw_buffer_in_use = true; | 400 | return NULL; |
448 | return engine; | ||
449 | } | 401 | } |
450 | 402 | ||
451 | 403 | pool->i2c_hw_buffer_in_use = true; | |
452 | return NULL; | 404 | return dce_i2c_hw; |
453 | } | 405 | } |
454 | 406 | ||
455 | enum i2c_channel_operation_result dce_i2c_hw_engine_wait_on_operation_result( | 407 | enum i2c_channel_operation_result dce_i2c_hw_engine_wait_on_operation_result( |
@@ -619,7 +571,12 @@ bool dce_i2c_submit_command_hw( | |||
619 | ++index_of_payload; | 571 | ++index_of_payload; |
620 | } | 572 | } |
621 | 573 | ||
622 | release_engine_dce_hw(pool, dce_i2c_hw); | 574 | pool->i2c_hw_buffer_in_use = false; |
575 | |||
576 | release_engine(dce_i2c_hw); | ||
577 | dal_ddc_close(dce_i2c_hw->ddc); | ||
578 | |||
579 | dce_i2c_hw->ddc = NULL; | ||
623 | 580 | ||
624 | return result; | 581 | return result; |
625 | } | 582 | } |