Merge branch 'drm-intel-fixes' into drm-intel-next

7 files changed, 193 insertions, 2 deletions

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index e2662497d50f..5bf7bf57c641 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1338,6 +1338,76 @@ static const struct file_operations i915_wedged_fops = {
         .llseek = default_llseek,
 };
 
+static int
+i915_max_freq_open(struct inode *inode,
+                   struct file *filp)
+{
+        filp->private_data = inode->i_private;
+        return 0;
+}
+
+static ssize_t
+i915_max_freq_read(struct file *filp,
+                   char __user *ubuf,
+                   size_t max,
+                   loff_t *ppos)
+{
+        struct drm_device *dev = filp->private_data;
+        drm_i915_private_t *dev_priv = dev->dev_private;
+        char buf[80];
+        int len;
+
+        len = snprintf(buf, sizeof (buf),
+                       "max freq: %d\n", dev_priv->max_delay * 50);
+
+        if (len > sizeof (buf))
+                len = sizeof (buf);
+
+        return simple_read_from_buffer(ubuf, max, ppos, buf, len);
+}
+
+static ssize_t
+i915_max_freq_write(struct file *filp,
+                  const char __user *ubuf,
+                  size_t cnt,
+                  loff_t *ppos)
+{
+        struct drm_device *dev = filp->private_data;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        char buf[20];
+        int val = 1;
+
+        if (cnt > 0) {
+                if (cnt > sizeof (buf) - 1)
+                        return -EINVAL;
+
+                if (copy_from_user(buf, ubuf, cnt))
+                        return -EFAULT;
+                buf[cnt] = 0;
+
+                val = simple_strtoul(buf, NULL, 0);
+        }
+
+        DRM_DEBUG_DRIVER("Manually setting max freq to %d\n", val);
+
+        /*
+         * Turbo will still be enabled, but won't go above the set value.
+         */
+        dev_priv->max_delay = val / 50;
+
+        gen6_set_rps(dev, val / 50);
+
+        return cnt;
+}
+
+static const struct file_operations i915_max_freq_fops = {
+        .owner = THIS_MODULE,
+        .open = i915_max_freq_open,
+        .read = i915_max_freq_read,
+        .write = i915_max_freq_write,
+        .llseek = default_llseek,
+};
+
 /* As the drm_debugfs_init() routines are called before dev->dev_private is
  * allocated we need to hook into the minor for release. */
 static int
@@ -1437,6 +1507,21 @@ static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
         return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
 }
 
+static int i915_max_freq_create(struct dentry *root, struct drm_minor *minor)
+{
+        struct drm_device *dev = minor->dev;
+        struct dentry *ent;
+
+        ent = debugfs_create_file("i915_max_freq",
+                                  S_IRUGO | S_IWUSR,
+                                  root, dev,
+                                  &i915_max_freq_fops);
+        if (IS_ERR(ent))
+                return PTR_ERR(ent);
+
+        return drm_add_fake_info_node(minor, ent, &i915_max_freq_fops);
+}
+
 static struct drm_info_list i915_debugfs_list[] = {
         {"i915_capabilities", i915_capabilities, 0},
         {"i915_gem_objects", i915_gem_object_info, 0},
@@ -1490,6 +1575,9 @@ int i915_debugfs_init(struct drm_minor *minor)
         ret = i915_forcewake_create(minor->debugfs_root, minor);
         if (ret)
                 return ret;
+        ret = i915_max_freq_create(minor->debugfs_root, minor);
+        if (ret)
+                return ret;
 
         return drm_debugfs_create_files(i915_debugfs_list,
                                         I915_DEBUGFS_ENTRIES,
@@ -1504,6 +1592,8 @@ void i915_debugfs_cleanup(struct drm_minor *minor)
                                  1, minor);
         drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops,
                                  1, minor);
+        drm_debugfs_remove_files((struct drm_info_list *) &i915_max_freq_fops,
+                                 1, minor);
 }
 
 #endif /* CONFIG_DEBUG_FS */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6867e193d85e..feb4f164fd1b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -544,6 +544,7 @@ typedef struct drm_i915_private {
         u32 savePIPEB_LINK_M1;
         u32 savePIPEB_LINK_N1;
         u32 saveMCHBAR_RENDER_STANDBY;
+        u32 savePCH_PORT_HOTPLUG;
 
         struct {
                 /** Bridge to intel-gtt-ko */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a900809baf2a..be67a596eee5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3021,6 +3021,20 @@
 #define _TRANSA_DP_LINK_M2       0xe0048
 #define _TRANSA_DP_LINK_N2       0xe004c
 
+/* Per-transcoder DIP controls */
+
+#define _VIDEO_DIP_CTL_A         0xe0200
+#define _VIDEO_DIP_DATA_A        0xe0208
+#define _VIDEO_DIP_GCP_A         0xe0210
+
+#define _VIDEO_DIP_CTL_B         0xe1200
+#define _VIDEO_DIP_DATA_B        0xe1208
+#define _VIDEO_DIP_GCP_B         0xe1210
+
+#define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
+#define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
+#define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
+
 #define _TRANS_HTOTAL_B          0xe1000
 #define _TRANS_HBLANK_B          0xe1004
 #define _TRANS_HSYNC_B           0xe1008
@@ -3078,6 +3092,11 @@
 #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
 #define   TRANS_AUTOTRAIN_GEN_STALL_DIS (1<<31)
 
+#define SOUTH_CHICKEN1          0xc2000
+#define  FDIA_PHASE_SYNC_SHIFT_OVR      19
+#define  FDIA_PHASE_SYNC_SHIFT_EN       18
+#define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
+#define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
 #define SOUTH_CHICKEN2          0xc2004
 #define  DPLS_EDP_PPS_FIX_DIS   (1<<0)
 
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 285758603ac8..87677d60d0df 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -812,6 +812,7 @@ int i915_save_state(struct drm_device *dev)
                 dev_priv->saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR);
                 dev_priv->saveMCHBAR_RENDER_STANDBY =
                         I915_READ(RSTDBYCTL);
+                dev_priv->savePCH_PORT_HOTPLUG = I915_READ(PCH_PORT_HOTPLUG);
         } else {
                 dev_priv->saveIER = I915_READ(IER);
                 dev_priv->saveIMR = I915_READ(IMR);
@@ -863,6 +864,7 @@ int i915_restore_state(struct drm_device *dev)
                 I915_WRITE(GTIMR, dev_priv->saveGTIMR);
                 I915_WRITE(_FDI_RXA_IMR, dev_priv->saveFDI_RXA_IMR);
                 I915_WRITE(_FDI_RXB_IMR, dev_priv->saveFDI_RXB_IMR);
+                I915_WRITE(PCH_PORT_HOTPLUG, dev_priv->savePCH_PORT_HOTPLUG);
         } else {
                 I915_WRITE(IER, dev_priv->saveIER);
                 I915_WRITE(IMR, dev_priv->saveIMR);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ce908ec02900..2bf5bb63fe41 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2275,6 +2275,18 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
                            FDI_FE_ERRC_ENABLE);
 }
 
+static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        u32 flags = I915_READ(SOUTH_CHICKEN1);
+
+        flags |= FDI_PHASE_SYNC_OVR(pipe);
+        I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
+        flags |= FDI_PHASE_SYNC_EN(pipe);
+        I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
+        POSTING_READ(SOUTH_CHICKEN1);
+}
+
 /* The FDI link training functions for ILK/Ibexpeak. */
 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
 {
@@ -2425,6 +2437,9 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
         POSTING_READ(reg);
         udelay(150);
 
+        if (HAS_PCH_CPT(dev))
+                cpt_phase_pointer_enable(dev, pipe);
+
         for (i = 0; i < 4; i++ ) {
                 reg = FDI_TX_CTL(pipe);
                 temp = I915_READ(reg);
@@ -2541,6 +2556,9 @@ static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
         POSTING_READ(reg);
         udelay(150);
 
+        if (HAS_PCH_CPT(dev))
+                cpt_phase_pointer_enable(dev, pipe);
+
         for (i = 0; i < 4; i++ ) {
                 reg = FDI_TX_CTL(pipe);
                 temp = I915_READ(reg);
@@ -2650,6 +2668,17 @@ static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
         }
 }
 
+static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        u32 flags = I915_READ(SOUTH_CHICKEN1);
+
+        flags &= ~(FDI_PHASE_SYNC_EN(pipe));
+        I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
+        flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
+        I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
+        POSTING_READ(SOUTH_CHICKEN1);
+}
 static void ironlake_fdi_disable(struct drm_crtc *crtc)
 {
         struct drm_device *dev = crtc->dev;
@@ -2679,6 +2708,8 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc)
                 I915_WRITE(FDI_RX_CHICKEN(pipe),
                            I915_READ(FDI_RX_CHICKEN(pipe) &
                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
+        } else if (HAS_PCH_CPT(dev)) {
+                cpt_phase_pointer_disable(dev, pipe);
         }
 
         /* still set train pattern 1 */
@@ -5269,7 +5300,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
         } else if (is_sdvo && is_tv)
                 factor = 20;
 
-        if (clock.m1 < factor * clock.n)
+        if (clock.m < factor * clock.n)
                 fp |= FP_CB_TUNE;
 
         dpll = 0;
@@ -8219,6 +8250,9 @@ struct intel_quirk intel_quirks[] = {
 
         /* Lenovo U160 cannot use SSC on LVDS */
         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
+
+        /* Sony Vaio Y cannot use SSC on LVDS */
+        { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
 };
 
 static void intel_init_quirks(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 1ed8e6903915..105e2b892f3a 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -112,6 +112,40 @@ static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
                    VIDEO_DIP_ENABLE_AVI);
 }
 
+static void intel_ironlake_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
+{
+        struct dip_infoframe avi_if = {
+                .type = DIP_TYPE_AVI,
+                .ver = DIP_VERSION_AVI,
+                .len = DIP_LEN_AVI,
+        };
+        uint32_t *data = (uint32_t *)&avi_if;
+        struct drm_device *dev = encoder->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
+        struct drm_crtc *crtc = encoder->crtc;
+        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+        int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
+        unsigned i;
+
+        if (!intel_hdmi->has_hdmi_sink)
+                return;
+
+        intel_wait_for_vblank(dev, intel_crtc->pipe);
+
+        I915_WRITE(reg, VIDEO_DIP_SELECT_AVI);
+
+        intel_dip_infoframe_csum(&avi_if);
+        for (i = 0; i < sizeof(avi_if); i += 4) {
+                I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
+                data++;
+        }
+
+        I915_WRITE(reg, VIDEO_DIP_ENABLE | VIDEO_DIP_SELECT_AVI |
+                   VIDEO_DIP_FREQ_VSYNC | (DIP_LEN_AVI << 8) |
+                   VIDEO_DIP_ENABLE_AVI);
+}
+
 static void intel_hdmi_mode_set(struct drm_encoder *encoder,
                                 struct drm_display_mode *mode,
                                 struct drm_display_mode *adjusted_mode)
@@ -155,7 +189,10 @@ static void intel_hdmi_mode_set(struct drm_encoder *encoder,
         I915_WRITE(intel_hdmi->sdvox_reg, sdvox);
         POSTING_READ(intel_hdmi->sdvox_reg);
 
-        intel_hdmi_set_avi_infoframe(encoder);
+        if (HAS_PCH_SPLIT(dev))
+                intel_ironlake_hdmi_set_avi_infoframe(encoder);
+        else
+                intel_hdmi_set_avi_infoframe(encoder);
 }
 
 static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode)
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index b28f7bd9f88a..2e8ddfcba40c 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -690,6 +690,14 @@ static const struct dmi_system_id intel_no_lvds[] = {
         },
         {
                 .callback = intel_no_lvds_dmi_callback,
+                .ident = "Dell OptiPlex FX170",
+                .matches = {
+                        DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
+                        DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
+                },
+        },
+        {
+                .callback = intel_no_lvds_dmi_callback,
                 .ident = "AOpen Mini PC",
                 .matches = {
                         DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),