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authorLucas Stach <l.stach@pengutronix.de>2016-08-16 05:48:49 -0400
committerLucas Stach <l.stach@pengutronix.de>2016-09-15 09:29:34 -0400
commit99f861bc83ab87b9ab3a404e7d7befe3837220a5 (patch)
treeae10bb80dec3a2a3fb9a643e83c692db409cb1cd /drivers/gpu
parent99aeeb7c58b24121e7951ef239ccf0626d4d566b (diff)
drm/etnaviv: move linear window setup into etnaviv_iommuv1_restore
It is only relevant for the V1 MMU, so we should not do this in the common code. Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/etnaviv/etnaviv_gpu.c9
-rw-r--r--drivers/gpu/drm/etnaviv/etnaviv_iommu.c7
2 files changed, 8 insertions, 8 deletions
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
index 6828fc17eec3..0dde3f7fc678 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
@@ -568,14 +568,7 @@ static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
568 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config); 568 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config);
569 } 569 }
570 570
571 /* set base addresses */ 571 /* setup the MMU */
572 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_RA, gpu->memory_base);
573 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_FE, gpu->memory_base);
574 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_TX, gpu->memory_base);
575 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PEZ, gpu->memory_base);
576 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PE, gpu->memory_base);
577
578 /* setup the MMU page table pointers */
579 etnaviv_iommuv1_restore(gpu); 572 etnaviv_iommuv1_restore(gpu);
580 573
581 /* Start command processor */ 574 /* Start command processor */
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_iommu.c b/drivers/gpu/drm/etnaviv/etnaviv_iommu.c
index 35f365f50e18..912a290a4e9c 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_iommu.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_iommu.c
@@ -202,6 +202,13 @@ void etnaviv_iommuv1_restore(struct etnaviv_gpu *gpu)
202 to_etnaviv_domain(gpu->mmu->domain); 202 to_etnaviv_domain(gpu->mmu->domain);
203 u32 pgtable; 203 u32 pgtable;
204 204
205 /* set base addresses */
206 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_RA, gpu->memory_base);
207 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_FE, gpu->memory_base);
208 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_TX, gpu->memory_base);
209 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PEZ, gpu->memory_base);
210 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PE, gpu->memory_base);
211
205 /* set page table address in MC */ 212 /* set page table address in MC */
206 pgtable = (u32)etnaviv_domain->pgtable.paddr; 213 pgtable = (u32)etnaviv_domain->pgtable.paddr;
207 214