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authorRex Zhu <Rex.Zhu@amd.com>2018-08-15 23:36:38 -0400
committerAlex Deucher <alexander.deucher@amd.com>2018-08-27 12:09:41 -0400
commit9650205a32e7f69c9846a205351e307ea525c1e7 (patch)
tree40e2846419a1788011722692bb53b1d3a18c18b4 /drivers/gpu
parenta3d9103ebfa03824d255060fc2c11ac94e3ef441 (diff)
drm/amd/display: Fix bug use wrong pp interface
Used wrong pp interface, the original interface is exposed by dpm on SI and paritial CI. Pointed out by Francis David <david.francis@amd.com> v2: dal only need to set min_dcefclk and min_fclk to smu. so use display_clock_voltage_request interface, instand of update all display configuration. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c12
1 files changed, 10 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index fbe878ae1e8c..4ba0003a9d32 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -480,12 +480,20 @@ void pp_rv_set_display_requirement(struct pp_smu *pp,
480{ 480{
481 struct dc_context *ctx = pp->ctx; 481 struct dc_context *ctx = pp->ctx;
482 struct amdgpu_device *adev = ctx->driver_context; 482 struct amdgpu_device *adev = ctx->driver_context;
483 void *pp_handle = adev->powerplay.pp_handle;
483 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 484 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
485 struct pp_display_clock_request clock = {0};
484 486
485 if (!pp_funcs || !pp_funcs->display_configuration_changed) 487 if (!pp_funcs || !pp_funcs->display_clock_voltage_request)
486 return; 488 return;
487 489
488 amdgpu_dpm_display_configuration_changed(adev); 490 clock.clock_type = amd_pp_dcf_clock;
491 clock.clock_freq_in_khz = req->hard_min_dcefclk_khz;
492 pp_funcs->display_clock_voltage_request(pp_handle, &clock);
493
494 clock.clock_type = amd_pp_f_clock;
495 clock.clock_freq_in_khz = req->hard_min_fclk_khz;
496 pp_funcs->display_clock_voltage_request(pp_handle, &clock);
489} 497}
490 498
491void pp_rv_set_wm_ranges(struct pp_smu *pp, 499void pp_rv_set_wm_ranges(struct pp_smu *pp,