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authorXiangliang Yu <Xiangliang.Yu@amd.com>2017-01-08 22:49:27 -0500
committerAlex Deucher <alexander.deucher@amd.com>2017-01-27 11:13:05 -0500
commit91caa081378c612030bfa9762fd7d88036508238 (patch)
tree1404f015f502e25e00f3bd19e8976710c0e501e9 /drivers/gpu
parent5a5099cbf4d8e68bde0554cf6f61bd4adf9fa243 (diff)
drm/amdgpu/vi: move virtualization detection forward
Move the detection forward into vi_set_ip_blocks function, then add ip blocks virtualization need if device is VF. V2: add ip blocks according to asic type. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vi.c24
1 files changed, 13 insertions, 11 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index cff1a0ebe832..0e1b2fd5cf38 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -856,7 +856,6 @@ static const struct amdgpu_asic_funcs vi_asic_funcs =
856{ 856{
857 .read_disabled_bios = &vi_read_disabled_bios, 857 .read_disabled_bios = &vi_read_disabled_bios,
858 .read_bios_from_rom = &vi_read_bios_from_rom, 858 .read_bios_from_rom = &vi_read_bios_from_rom,
859 .detect_hw_virtualization = vi_detect_hw_virtualization,
860 .read_register = &vi_read_register, 859 .read_register = &vi_read_register,
861 .reset = &vi_asic_reset, 860 .reset = &vi_asic_reset,
862 .set_vga_state = &vi_vga_set_state, 861 .set_vga_state = &vi_vga_set_state,
@@ -1048,10 +1047,6 @@ static int vi_common_early_init(void *handle)
1048 return -EINVAL; 1047 return -EINVAL;
1049 } 1048 }
1050 1049
1051 /* in early init stage, vbios code won't work */
1052 if (adev->asic_funcs->detect_hw_virtualization)
1053 amdgpu_asic_detect_hw_virtualization(adev);
1054
1055 if (amdgpu_smc_load_fw && smc_enabled) 1050 if (amdgpu_smc_load_fw && smc_enabled)
1056 adev->firmware.smu_load = true; 1051 adev->firmware.smu_load = true;
1057 1052
@@ -1402,6 +1397,9 @@ static const struct amdgpu_ip_block_version vi_common_ip_block =
1402 1397
1403int vi_set_ip_blocks(struct amdgpu_device *adev) 1398int vi_set_ip_blocks(struct amdgpu_device *adev)
1404{ 1399{
1400 /* in early init stage, vbios code won't work */
1401 vi_detect_hw_virtualization(adev);
1402
1405 switch (adev->asic_type) { 1403 switch (adev->asic_type) {
1406 case CHIP_TOPAZ: 1404 case CHIP_TOPAZ:
1407 /* topaz has no DCE, UVD, VCE */ 1405 /* topaz has no DCE, UVD, VCE */
@@ -1419,28 +1417,32 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
1419 amdgpu_ip_block_add(adev, &gmc_v8_5_ip_block); 1417 amdgpu_ip_block_add(adev, &gmc_v8_5_ip_block);
1420 amdgpu_ip_block_add(adev, &tonga_ih_ip_block); 1418 amdgpu_ip_block_add(adev, &tonga_ih_ip_block);
1421 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); 1419 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1422 if (adev->enable_virtual_display) 1420 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
1423 amdgpu_ip_block_add(adev, &dce_virtual_ip_block); 1421 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1424 else 1422 else
1425 amdgpu_ip_block_add(adev, &dce_v10_1_ip_block); 1423 amdgpu_ip_block_add(adev, &dce_v10_1_ip_block);
1426 amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block); 1424 amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
1427 amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block); 1425 amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block);
1428 amdgpu_ip_block_add(adev, &uvd_v6_0_ip_block); 1426 if (!amdgpu_sriov_vf(adev)) {
1429 amdgpu_ip_block_add(adev, &vce_v3_0_ip_block); 1427 amdgpu_ip_block_add(adev, &uvd_v6_0_ip_block);
1428 amdgpu_ip_block_add(adev, &vce_v3_0_ip_block);
1429 }
1430 break; 1430 break;
1431 case CHIP_TONGA: 1431 case CHIP_TONGA:
1432 amdgpu_ip_block_add(adev, &vi_common_ip_block); 1432 amdgpu_ip_block_add(adev, &vi_common_ip_block);
1433 amdgpu_ip_block_add(adev, &gmc_v8_0_ip_block); 1433 amdgpu_ip_block_add(adev, &gmc_v8_0_ip_block);
1434 amdgpu_ip_block_add(adev, &tonga_ih_ip_block); 1434 amdgpu_ip_block_add(adev, &tonga_ih_ip_block);
1435 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); 1435 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1436 if (adev->enable_virtual_display) 1436 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
1437 amdgpu_ip_block_add(adev, &dce_virtual_ip_block); 1437 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1438 else 1438 else
1439 amdgpu_ip_block_add(adev, &dce_v10_0_ip_block); 1439 amdgpu_ip_block_add(adev, &dce_v10_0_ip_block);
1440 amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block); 1440 amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
1441 amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block); 1441 amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block);
1442 amdgpu_ip_block_add(adev, &uvd_v5_0_ip_block); 1442 if (!amdgpu_sriov_vf(adev)) {
1443 amdgpu_ip_block_add(adev, &vce_v3_0_ip_block); 1443 amdgpu_ip_block_add(adev, &uvd_v5_0_ip_block);
1444 amdgpu_ip_block_add(adev, &vce_v3_0_ip_block);
1445 }
1444 break; 1446 break;
1445 case CHIP_POLARIS11: 1447 case CHIP_POLARIS11:
1446 case CHIP_POLARIS10: 1448 case CHIP_POLARIS10: