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authorBoris Brezillon <boris.brezillon@bootlin.com>2018-12-07 03:36:05 -0500
committerBoris Brezillon <boris.brezillon@bootlin.com>2018-12-08 07:27:36 -0500
commit8e75d582db02bcb171d65ec71eecbd3072a5fd3a (patch)
tree79720cf8d19a5243fc68120cd3de68d9708c946e /drivers/gpu
parentaa5beec32e8b78bfcf621e3c3daebfb1644b6365 (diff)
drm/vc4: Fix negative X/Y positioning on SAND planes
Commit 3e407417b192 ("drm/vc4: Fix X/Y positioning of planes using T_TILES modifier") fixed the problem with T_TILES format, but left things in a non-working state for SAND formats. Address that now. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Reviewed-by: Eric Anholt <eric@anholt.net> Link: https://patchwork.freedesktop.org/patch/msgid/20181207083606.15449-1-boris.brezillon@bootlin.com
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/vc4/vc4_plane.c21
1 files changed, 21 insertions, 0 deletions
diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c
index 75db62cbe468..fb1214b91a25 100644
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
@@ -595,6 +595,7 @@ static int vc4_plane_mode_set(struct drm_plane *plane,
595 case DRM_FORMAT_MOD_BROADCOM_SAND128: 595 case DRM_FORMAT_MOD_BROADCOM_SAND128:
596 case DRM_FORMAT_MOD_BROADCOM_SAND256: { 596 case DRM_FORMAT_MOD_BROADCOM_SAND256: {
597 uint32_t param = fourcc_mod_broadcom_param(fb->modifier); 597 uint32_t param = fourcc_mod_broadcom_param(fb->modifier);
598 u32 tile_w, tile, x_off, pix_per_tile;
598 599
599 /* Column-based NV12 or RGBA. 600 /* Column-based NV12 or RGBA.
600 */ 601 */
@@ -614,12 +615,15 @@ static int vc4_plane_mode_set(struct drm_plane *plane,
614 switch (base_format_mod) { 615 switch (base_format_mod) {
615 case DRM_FORMAT_MOD_BROADCOM_SAND64: 616 case DRM_FORMAT_MOD_BROADCOM_SAND64:
616 tiling = SCALER_CTL0_TILING_64B; 617 tiling = SCALER_CTL0_TILING_64B;
618 tile_w = 64;
617 break; 619 break;
618 case DRM_FORMAT_MOD_BROADCOM_SAND128: 620 case DRM_FORMAT_MOD_BROADCOM_SAND128:
619 tiling = SCALER_CTL0_TILING_128B; 621 tiling = SCALER_CTL0_TILING_128B;
622 tile_w = 128;
620 break; 623 break;
621 case DRM_FORMAT_MOD_BROADCOM_SAND256: 624 case DRM_FORMAT_MOD_BROADCOM_SAND256:
622 tiling = SCALER_CTL0_TILING_256B_OR_T; 625 tiling = SCALER_CTL0_TILING_256B_OR_T;
626 tile_w = 256;
623 break; 627 break;
624 default: 628 default:
625 break; 629 break;
@@ -630,6 +634,23 @@ static int vc4_plane_mode_set(struct drm_plane *plane,
630 return -EINVAL; 634 return -EINVAL;
631 } 635 }
632 636
637 pix_per_tile = tile_w / fb->format->cpp[0];
638 tile = vc4_state->src_x / pix_per_tile;
639 x_off = vc4_state->src_x % pix_per_tile;
640
641 /* Adjust the base pointer to the first pixel to be scanned
642 * out.
643 */
644 for (i = 0; i < num_planes; i++) {
645 vc4_state->offsets[i] += param * tile_w * tile;
646 vc4_state->offsets[i] += vc4_state->src_y /
647 (i ? v_subsample : 1) *
648 tile_w;
649 vc4_state->offsets[i] += x_off /
650 (i ? h_subsample : 1) *
651 fb->format->cpp[i];
652 }
653
633 pitch0 = VC4_SET_FIELD(param, SCALER_TILE_HEIGHT); 654 pitch0 = VC4_SET_FIELD(param, SCALER_TILE_HEIGHT);
634 break; 655 break;
635 } 656 }