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authorHarry Wentland <harry.wentland@amd.com>2016-11-28 16:30:24 -0500
committerAlex Deucher <alexander.deucher@amd.com>2017-01-27 11:12:43 -0500
commit8c27f5c1fda5e06405d9c3092735fbc5ec2b1dfa (patch)
treec1c7c82ac5425b858023965226a555c36f6c066f /drivers/gpu
parent9e4bd4ca621d722b9783484cc323cd843d74027d (diff)
drm/amd/amdgpu: Add HDMI_DATA_SCRAMBLE register definition
This is required by HDMI 2.0 Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h2
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h2
2 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h
index a438c2b6e280..a645ec135fd8 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h
@@ -6004,6 +6004,8 @@
6004#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK__SHIFT 0xc 6004#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK__SHIFT 0xc
6005#define HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x1 6005#define HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x1
6006#define HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 6006#define HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0
6007#define HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x2
6008#define HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1
6007#define HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x4 6009#define HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x4
6008#define HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 6010#define HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2
6009#define HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x8 6011#define HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x8
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h
index 1ddc4183a1c9..d6d737931542 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h
@@ -7088,6 +7088,8 @@
7088#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK__SHIFT 0xc 7088#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK__SHIFT 0xc
7089#define HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x1 7089#define HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x1
7090#define HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 7090#define HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0
7091#define HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x2
7092#define HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1
7091#define HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x4 7093#define HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x4
7092#define HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 7094#define HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2
7093#define HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x8 7095#define HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x8