diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2014-08-09 14:10:25 -0400 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2014-08-09 15:28:05 -0400 |
commit | 867920f8c920bcaa5a6fa5ebad4596669b82ba80 (patch) | |
tree | 063aebcdfdeba309f3921d9fe2a8463aec64ff7c /drivers/gpu | |
parent | 6c6ae061b61c1fd0d1823765299bcc009ddc21c8 (diff) |
drm/nouveau/fifo: implement nvif event source
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/fifo/base.c | 44 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c | 16 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c | 17 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c | 17 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/include/engine/fifo.h | 5 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_fence.c | 23 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nvif/class.h | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nvif/event.h | 8 |
13 files changed, 89 insertions, 50 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/base.c b/drivers/gpu/drm/nouveau/core/engine/fifo/base.c index 0def249b1b43..0f999fc45ab9 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/base.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/base.c | |||
@@ -28,6 +28,7 @@ | |||
28 | #include <core/event.h> | 28 | #include <core/event.h> |
29 | #include <nvif/unpack.h> | 29 | #include <nvif/unpack.h> |
30 | #include <nvif/class.h> | 30 | #include <nvif/class.h> |
31 | #include <nvif/event.h> | ||
31 | 32 | ||
32 | #include <engine/dmaobj.h> | 33 | #include <engine/dmaobj.h> |
33 | #include <engine/fifo.h> | 34 | #include <engine/fifo.h> |
@@ -168,6 +169,49 @@ _nouveau_fifo_channel_wr32(struct nouveau_object *object, u64 addr, u32 data) | |||
168 | iowrite32_native(data, chan->user + addr); | 169 | iowrite32_native(data, chan->user + addr); |
169 | } | 170 | } |
170 | 171 | ||
172 | int | ||
173 | nouveau_fifo_uevent_ctor(void *data, u32 size, struct nvkm_notify *notify) | ||
174 | { | ||
175 | union { | ||
176 | struct nvif_notify_uevent_req none; | ||
177 | } *req = data; | ||
178 | int ret; | ||
179 | |||
180 | if (nvif_unvers(req->none)) { | ||
181 | notify->size = sizeof(struct nvif_notify_uevent_rep); | ||
182 | notify->types = 1; | ||
183 | notify->index = 0; | ||
184 | } | ||
185 | |||
186 | return ret; | ||
187 | } | ||
188 | |||
189 | void | ||
190 | nouveau_fifo_uevent(struct nouveau_fifo *fifo) | ||
191 | { | ||
192 | struct nvif_notify_uevent_rep rep = { | ||
193 | }; | ||
194 | nvkm_event_send(&fifo->uevent, 1, 0, &rep, sizeof(rep)); | ||
195 | } | ||
196 | |||
197 | int | ||
198 | _nouveau_fifo_channel_ntfy(struct nouveau_object *object, u32 type, | ||
199 | struct nvkm_event **event) | ||
200 | { | ||
201 | struct nouveau_fifo *fifo = (void *)object->engine; | ||
202 | switch (type) { | ||
203 | case G82_CHANNEL_DMA_V0_NTFY_UEVENT: | ||
204 | if (nv_mclass(object) >= G82_CHANNEL_DMA) { | ||
205 | *event = &fifo->uevent; | ||
206 | return 0; | ||
207 | } | ||
208 | break; | ||
209 | default: | ||
210 | break; | ||
211 | } | ||
212 | return -EINVAL; | ||
213 | } | ||
214 | |||
171 | static int | 215 | static int |
172 | nouveau_fifo_chid(struct nouveau_fifo *priv, struct nouveau_object *object) | 216 | nouveau_fifo_chid(struct nouveau_fifo *priv, struct nouveau_object *object) |
173 | { | 217 | { |
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c index 347b381e2dcf..5ae6a43893b5 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c | |||
@@ -255,6 +255,7 @@ nv04_fifo_ofuncs = { | |||
255 | .map = _nouveau_fifo_channel_map, | 255 | .map = _nouveau_fifo_channel_map, |
256 | .rd32 = _nouveau_fifo_channel_rd32, | 256 | .rd32 = _nouveau_fifo_channel_rd32, |
257 | .wr32 = _nouveau_fifo_channel_wr32, | 257 | .wr32 = _nouveau_fifo_channel_wr32, |
258 | .ntfy = _nouveau_fifo_channel_ntfy | ||
258 | }; | 259 | }; |
259 | 260 | ||
260 | static struct nouveau_oclass | 261 | static struct nouveau_oclass |
@@ -550,7 +551,7 @@ nv04_fifo_intr(struct nouveau_subdev *subdev) | |||
550 | } | 551 | } |
551 | 552 | ||
552 | if (status & 0x40000000) { | 553 | if (status & 0x40000000) { |
553 | nvkm_event_send(&priv->base.uevent, 1, 0, NULL, 0); | 554 | nouveau_fifo_uevent(&priv->base); |
554 | nv_wr32(priv, 0x002100, 0x40000000); | 555 | nv_wr32(priv, 0x002100, 0x40000000); |
555 | status &= ~0x40000000; | 556 | status &= ~0x40000000; |
556 | } | 557 | } |
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c index d8dac2fc6a3b..2a32add51c81 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c | |||
@@ -113,6 +113,7 @@ nv10_fifo_ofuncs = { | |||
113 | .map = _nouveau_fifo_channel_map, | 113 | .map = _nouveau_fifo_channel_map, |
114 | .rd32 = _nouveau_fifo_channel_rd32, | 114 | .rd32 = _nouveau_fifo_channel_rd32, |
115 | .wr32 = _nouveau_fifo_channel_wr32, | 115 | .wr32 = _nouveau_fifo_channel_wr32, |
116 | .ntfy = _nouveau_fifo_channel_ntfy | ||
116 | }; | 117 | }; |
117 | 118 | ||
118 | static struct nouveau_oclass | 119 | static struct nouveau_oclass |
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c index c424aab0e041..12d76c8adb23 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c | |||
@@ -120,6 +120,7 @@ nv17_fifo_ofuncs = { | |||
120 | .map = _nouveau_fifo_channel_map, | 120 | .map = _nouveau_fifo_channel_map, |
121 | .rd32 = _nouveau_fifo_channel_rd32, | 121 | .rd32 = _nouveau_fifo_channel_rd32, |
122 | .wr32 = _nouveau_fifo_channel_wr32, | 122 | .wr32 = _nouveau_fifo_channel_wr32, |
123 | .ntfy = _nouveau_fifo_channel_ntfy | ||
123 | }; | 124 | }; |
124 | 125 | ||
125 | static struct nouveau_oclass | 126 | static struct nouveau_oclass |
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c index 17d14d9e02ca..9f49c3a24dc6 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c | |||
@@ -239,6 +239,7 @@ nv40_fifo_ofuncs = { | |||
239 | .map = _nouveau_fifo_channel_map, | 239 | .map = _nouveau_fifo_channel_map, |
240 | .rd32 = _nouveau_fifo_channel_rd32, | 240 | .rd32 = _nouveau_fifo_channel_rd32, |
241 | .wr32 = _nouveau_fifo_channel_wr32, | 241 | .wr32 = _nouveau_fifo_channel_wr32, |
242 | .ntfy = _nouveau_fifo_channel_ntfy | ||
242 | }; | 243 | }; |
243 | 244 | ||
244 | static struct nouveau_oclass | 245 | static struct nouveau_oclass |
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c index 2db67a207b4a..5d1e86bc244c 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c | |||
@@ -366,6 +366,7 @@ nv50_fifo_ofuncs_dma = { | |||
366 | .map = _nouveau_fifo_channel_map, | 366 | .map = _nouveau_fifo_channel_map, |
367 | .rd32 = _nouveau_fifo_channel_rd32, | 367 | .rd32 = _nouveau_fifo_channel_rd32, |
368 | .wr32 = _nouveau_fifo_channel_wr32, | 368 | .wr32 = _nouveau_fifo_channel_wr32, |
369 | .ntfy = _nouveau_fifo_channel_ntfy | ||
369 | }; | 370 | }; |
370 | 371 | ||
371 | static struct nouveau_ofuncs | 372 | static struct nouveau_ofuncs |
@@ -377,6 +378,7 @@ nv50_fifo_ofuncs_ind = { | |||
377 | .map = _nouveau_fifo_channel_map, | 378 | .map = _nouveau_fifo_channel_map, |
378 | .rd32 = _nouveau_fifo_channel_rd32, | 379 | .rd32 = _nouveau_fifo_channel_rd32, |
379 | .wr32 = _nouveau_fifo_channel_wr32, | 380 | .wr32 = _nouveau_fifo_channel_wr32, |
381 | .ntfy = _nouveau_fifo_channel_ntfy | ||
380 | }; | 382 | }; |
381 | 383 | ||
382 | static struct nouveau_oclass | 384 | static struct nouveau_oclass |
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c index a2acf3f78b56..1f42996b354a 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c | |||
@@ -327,6 +327,7 @@ nv84_fifo_ofuncs_dma = { | |||
327 | .map = _nouveau_fifo_channel_map, | 327 | .map = _nouveau_fifo_channel_map, |
328 | .rd32 = _nouveau_fifo_channel_rd32, | 328 | .rd32 = _nouveau_fifo_channel_rd32, |
329 | .wr32 = _nouveau_fifo_channel_wr32, | 329 | .wr32 = _nouveau_fifo_channel_wr32, |
330 | .ntfy = _nouveau_fifo_channel_ntfy | ||
330 | }; | 331 | }; |
331 | 332 | ||
332 | static struct nouveau_ofuncs | 333 | static struct nouveau_ofuncs |
@@ -338,6 +339,7 @@ nv84_fifo_ofuncs_ind = { | |||
338 | .map = _nouveau_fifo_channel_map, | 339 | .map = _nouveau_fifo_channel_map, |
339 | .rd32 = _nouveau_fifo_channel_rd32, | 340 | .rd32 = _nouveau_fifo_channel_rd32, |
340 | .wr32 = _nouveau_fifo_channel_wr32, | 341 | .wr32 = _nouveau_fifo_channel_wr32, |
342 | .ntfy = _nouveau_fifo_channel_ntfy | ||
341 | }; | 343 | }; |
342 | 344 | ||
343 | static struct nouveau_oclass | 345 | static struct nouveau_oclass |
@@ -424,21 +426,9 @@ nv84_fifo_uevent_fini(struct nvkm_event *event, int type, int index) | |||
424 | nv_mask(fifo, 0x002140, 0x40000000, 0x00000000); | 426 | nv_mask(fifo, 0x002140, 0x40000000, 0x00000000); |
425 | } | 427 | } |
426 | 428 | ||
427 | static int | ||
428 | nv84_fifo_uevent_ctor(void *data, u32 size, struct nvkm_notify *notify) | ||
429 | { | ||
430 | if (size == 0) { | ||
431 | notify->size = 0; | ||
432 | notify->types = 1; | ||
433 | notify->index = 0; | ||
434 | return 0; | ||
435 | } | ||
436 | return -ENOSYS; | ||
437 | } | ||
438 | |||
439 | static const struct nvkm_event_func | 429 | static const struct nvkm_event_func |
440 | nv84_fifo_uevent_func = { | 430 | nv84_fifo_uevent_func = { |
441 | .ctor = nv84_fifo_uevent_ctor, | 431 | .ctor = nouveau_fifo_uevent_ctor, |
442 | .init = nv84_fifo_uevent_init, | 432 | .init = nv84_fifo_uevent_init, |
443 | .fini = nv84_fifo_uevent_fini, | 433 | .fini = nv84_fifo_uevent_fini, |
444 | }; | 434 | }; |
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c index f76ed10d8db0..1fe1f8fbda0c 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c | |||
@@ -305,6 +305,7 @@ nvc0_fifo_ofuncs = { | |||
305 | .map = _nouveau_fifo_channel_map, | 305 | .map = _nouveau_fifo_channel_map, |
306 | .rd32 = _nouveau_fifo_channel_rd32, | 306 | .rd32 = _nouveau_fifo_channel_rd32, |
307 | .wr32 = _nouveau_fifo_channel_wr32, | 307 | .wr32 = _nouveau_fifo_channel_wr32, |
308 | .ntfy = _nouveau_fifo_channel_ntfy | ||
308 | }; | 309 | }; |
309 | 310 | ||
310 | static struct nouveau_oclass | 311 | static struct nouveau_oclass |
@@ -742,7 +743,7 @@ nvc0_fifo_intr_engine_unit(struct nvc0_fifo_priv *priv, int engn) | |||
742 | for (unkn = 0; unkn < 8; unkn++) { | 743 | for (unkn = 0; unkn < 8; unkn++) { |
743 | u32 ints = (intr >> (unkn * 0x04)) & inte; | 744 | u32 ints = (intr >> (unkn * 0x04)) & inte; |
744 | if (ints & 0x1) { | 745 | if (ints & 0x1) { |
745 | nvkm_event_send(&priv->base.uevent, 1, 0, NULL, 0); | 746 | nouveau_fifo_uevent(&priv->base); |
746 | ints &= ~1; | 747 | ints &= ~1; |
747 | } | 748 | } |
748 | if (ints) { | 749 | if (ints) { |
@@ -852,21 +853,9 @@ nvc0_fifo_uevent_fini(struct nvkm_event *event, int type, int index) | |||
852 | nv_mask(fifo, 0x002140, 0x80000000, 0x00000000); | 853 | nv_mask(fifo, 0x002140, 0x80000000, 0x00000000); |
853 | } | 854 | } |
854 | 855 | ||
855 | static int | ||
856 | nvc0_fifo_uevent_ctor(void *data, u32 size, struct nvkm_notify *notify) | ||
857 | { | ||
858 | if (size == 0) { | ||
859 | notify->size = 0; | ||
860 | notify->types = 1; | ||
861 | notify->index = 0; | ||
862 | return 0; | ||
863 | } | ||
864 | return -ENOSYS; | ||
865 | } | ||
866 | |||
867 | static const struct nvkm_event_func | 856 | static const struct nvkm_event_func |
868 | nvc0_fifo_uevent_func = { | 857 | nvc0_fifo_uevent_func = { |
869 | .ctor = nvc0_fifo_uevent_ctor, | 858 | .ctor = nouveau_fifo_uevent_ctor, |
870 | .init = nvc0_fifo_uevent_init, | 859 | .init = nvc0_fifo_uevent_init, |
871 | .fini = nvc0_fifo_uevent_fini, | 860 | .fini = nvc0_fifo_uevent_fini, |
872 | }; | 861 | }; |
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c index ef730b52ce0d..d2f0fd39c145 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c | |||
@@ -339,6 +339,7 @@ nve0_fifo_ofuncs = { | |||
339 | .map = _nouveau_fifo_channel_map, | 339 | .map = _nouveau_fifo_channel_map, |
340 | .rd32 = _nouveau_fifo_channel_rd32, | 340 | .rd32 = _nouveau_fifo_channel_rd32, |
341 | .wr32 = _nouveau_fifo_channel_wr32, | 341 | .wr32 = _nouveau_fifo_channel_wr32, |
342 | .ntfy = _nouveau_fifo_channel_ntfy | ||
342 | }; | 343 | }; |
343 | 344 | ||
344 | static struct nouveau_oclass | 345 | static struct nouveau_oclass |
@@ -871,7 +872,7 @@ nve0_fifo_intr_runlist(struct nve0_fifo_priv *priv) | |||
871 | static void | 872 | static void |
872 | nve0_fifo_intr_engine(struct nve0_fifo_priv *priv) | 873 | nve0_fifo_intr_engine(struct nve0_fifo_priv *priv) |
873 | { | 874 | { |
874 | nvkm_event_send(&priv->base.uevent, 1, 0, NULL, 0); | 875 | nouveau_fifo_uevent(&priv->base); |
875 | } | 876 | } |
876 | 877 | ||
877 | static void | 878 | static void |
@@ -977,21 +978,9 @@ nve0_fifo_uevent_fini(struct nvkm_event *event, int type, int index) | |||
977 | nv_mask(fifo, 0x002140, 0x80000000, 0x00000000); | 978 | nv_mask(fifo, 0x002140, 0x80000000, 0x00000000); |
978 | } | 979 | } |
979 | 980 | ||
980 | static int | ||
981 | nve0_fifo_uevent_ctor(void *data, u32 size, struct nvkm_notify *notify) | ||
982 | { | ||
983 | if (size == 0) { | ||
984 | notify->size = 0; | ||
985 | notify->types = 1; | ||
986 | notify->index = 0; | ||
987 | return 0; | ||
988 | } | ||
989 | return -ENOSYS; | ||
990 | } | ||
991 | |||
992 | static const struct nvkm_event_func | 981 | static const struct nvkm_event_func |
993 | nve0_fifo_uevent_func = { | 982 | nve0_fifo_uevent_func = { |
994 | .ctor = nve0_fifo_uevent_ctor, | 983 | .ctor = nouveau_fifo_uevent_ctor, |
995 | .init = nve0_fifo_uevent_init, | 984 | .init = nve0_fifo_uevent_init, |
996 | .fini = nve0_fifo_uevent_fini, | 985 | .fini = nve0_fifo_uevent_fini, |
997 | }; | 986 | }; |
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/fifo.h b/drivers/gpu/drm/nouveau/core/include/engine/fifo.h index b53f9d8022fe..e5e4d930b2c2 100644 --- a/drivers/gpu/drm/nouveau/core/include/engine/fifo.h +++ b/drivers/gpu/drm/nouveau/core/include/engine/fifo.h | |||
@@ -4,6 +4,7 @@ | |||
4 | #include <core/namedb.h> | 4 | #include <core/namedb.h> |
5 | #include <core/gpuobj.h> | 5 | #include <core/gpuobj.h> |
6 | #include <core/engine.h> | 6 | #include <core/engine.h> |
7 | #include <core/event.h> | ||
7 | 8 | ||
8 | struct nouveau_fifo_chan { | 9 | struct nouveau_fifo_chan { |
9 | struct nouveau_namedb base; | 10 | struct nouveau_namedb base; |
@@ -44,6 +45,7 @@ void _nouveau_fifo_channel_dtor(struct nouveau_object *); | |||
44 | int _nouveau_fifo_channel_map(struct nouveau_object *, u64 *, u32 *); | 45 | int _nouveau_fifo_channel_map(struct nouveau_object *, u64 *, u32 *); |
45 | u32 _nouveau_fifo_channel_rd32(struct nouveau_object *, u64); | 46 | u32 _nouveau_fifo_channel_rd32(struct nouveau_object *, u64); |
46 | void _nouveau_fifo_channel_wr32(struct nouveau_object *, u64, u32); | 47 | void _nouveau_fifo_channel_wr32(struct nouveau_object *, u64, u32); |
48 | int _nouveau_fifo_channel_ntfy(struct nouveau_object *, u32, struct nvkm_event **); | ||
47 | 49 | ||
48 | struct nouveau_fifo_base { | 50 | struct nouveau_fifo_base { |
49 | struct nouveau_gpuobj base; | 51 | struct nouveau_gpuobj base; |
@@ -114,6 +116,9 @@ extern struct nouveau_oclass *nve0_fifo_oclass; | |||
114 | extern struct nouveau_oclass *gk20a_fifo_oclass; | 116 | extern struct nouveau_oclass *gk20a_fifo_oclass; |
115 | extern struct nouveau_oclass *nv108_fifo_oclass; | 117 | extern struct nouveau_oclass *nv108_fifo_oclass; |
116 | 118 | ||
119 | int nouveau_fifo_uevent_ctor(void *, u32, struct nvkm_notify *); | ||
120 | void nouveau_fifo_uevent(struct nouveau_fifo *); | ||
121 | |||
117 | void nv04_fifo_intr(struct nouveau_subdev *); | 122 | void nv04_fifo_intr(struct nouveau_subdev *); |
118 | int nv04_fifo_context_attach(struct nouveau_object *, struct nouveau_object *); | 123 | int nv04_fifo_context_attach(struct nouveau_object *, struct nouveau_object *); |
119 | 124 | ||
diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.c b/drivers/gpu/drm/nouveau/nouveau_fence.c index ace42ec92a72..0a93114158cd 100644 --- a/drivers/gpu/drm/nouveau/nouveau_fence.c +++ b/drivers/gpu/drm/nouveau/nouveau_fence.c | |||
@@ -29,6 +29,9 @@ | |||
29 | #include <linux/ktime.h> | 29 | #include <linux/ktime.h> |
30 | #include <linux/hrtimer.h> | 30 | #include <linux/hrtimer.h> |
31 | 31 | ||
32 | #include <nvif/notify.h> | ||
33 | #include <nvif/event.h> | ||
34 | |||
32 | #include "nouveau_drm.h" | 35 | #include "nouveau_drm.h" |
33 | #include "nouveau_dma.h" | 36 | #include "nouveau_dma.h" |
34 | #include "nouveau_fence.h" | 37 | #include "nouveau_fence.h" |
@@ -165,16 +168,16 @@ nouveau_fence_done(struct nouveau_fence *fence) | |||
165 | 168 | ||
166 | struct nouveau_fence_wait { | 169 | struct nouveau_fence_wait { |
167 | struct nouveau_fence_priv *priv; | 170 | struct nouveau_fence_priv *priv; |
168 | struct nvkm_notify notify; | 171 | struct nvif_notify notify; |
169 | }; | 172 | }; |
170 | 173 | ||
171 | static int | 174 | static int |
172 | nouveau_fence_wait_uevent_handler(struct nvkm_notify *notify) | 175 | nouveau_fence_wait_uevent_handler(struct nvif_notify *notify) |
173 | { | 176 | { |
174 | struct nouveau_fence_wait *wait = | 177 | struct nouveau_fence_wait *wait = |
175 | container_of(notify, typeof(*wait), notify); | 178 | container_of(notify, typeof(*wait), notify); |
176 | wake_up_all(&wait->priv->waiting); | 179 | wake_up_all(&wait->priv->waiting); |
177 | return NVKM_NOTIFY_KEEP; | 180 | return NVIF_NOTIFY_KEEP; |
178 | } | 181 | } |
179 | 182 | ||
180 | static int | 183 | static int |
@@ -182,18 +185,22 @@ nouveau_fence_wait_uevent(struct nouveau_fence *fence, bool intr) | |||
182 | 185 | ||
183 | { | 186 | { |
184 | struct nouveau_channel *chan = fence->channel; | 187 | struct nouveau_channel *chan = fence->channel; |
185 | struct nouveau_fifo *pfifo = nvkm_fifo(chan->device); | ||
186 | struct nouveau_fence_priv *priv = chan->drm->fence; | 188 | struct nouveau_fence_priv *priv = chan->drm->fence; |
187 | struct nouveau_fence_wait wait = { .priv = priv }; | 189 | struct nouveau_fence_wait wait = { .priv = priv }; |
188 | int ret = 0; | 190 | int ret = 0; |
189 | 191 | ||
190 | ret = nvkm_notify_init(&pfifo->uevent, | 192 | ret = nvif_notify_init(chan->object, NULL, |
191 | nouveau_fence_wait_uevent_handler, false, | 193 | nouveau_fence_wait_uevent_handler, false, |
192 | NULL, 0, 0, &wait.notify); | 194 | G82_CHANNEL_DMA_V0_NTFY_UEVENT, |
195 | &(struct nvif_notify_uevent_req) { | ||
196 | }, | ||
197 | sizeof(struct nvif_notify_uevent_req), | ||
198 | sizeof(struct nvif_notify_uevent_rep), | ||
199 | &wait.notify); | ||
193 | if (ret) | 200 | if (ret) |
194 | return ret; | 201 | return ret; |
195 | 202 | ||
196 | nvkm_notify_get(&wait.notify); | 203 | nvif_notify_get(&wait.notify); |
197 | 204 | ||
198 | if (fence->timeout) { | 205 | if (fence->timeout) { |
199 | unsigned long timeout = fence->timeout - jiffies; | 206 | unsigned long timeout = fence->timeout - jiffies; |
@@ -225,7 +232,7 @@ nouveau_fence_wait_uevent(struct nouveau_fence *fence, bool intr) | |||
225 | } | 232 | } |
226 | } | 233 | } |
227 | 234 | ||
228 | nvkm_notify_fini(&wait.notify); | 235 | nvif_notify_fini(&wait.notify); |
229 | if (unlikely(ret < 0)) | 236 | if (unlikely(ret < 0)) |
230 | return ret; | 237 | return ret; |
231 | 238 | ||
diff --git a/drivers/gpu/drm/nouveau/nvif/class.h b/drivers/gpu/drm/nouveau/nvif/class.h index 476d57a1ed6e..50c5413ff523 100644 --- a/drivers/gpu/drm/nouveau/nvif/class.h +++ b/drivers/gpu/drm/nouveau/nvif/class.h | |||
@@ -258,6 +258,7 @@ struct nv03_channel_dma_v0 { | |||
258 | __u64 offset; | 258 | __u64 offset; |
259 | }; | 259 | }; |
260 | 260 | ||
261 | #define G82_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 | ||
261 | 262 | ||
262 | /******************************************************************************* | 263 | /******************************************************************************* |
263 | * GPFIFO channels | 264 | * GPFIFO channels |
diff --git a/drivers/gpu/drm/nouveau/nvif/event.h b/drivers/gpu/drm/nouveau/nvif/event.h index cef3ef103be5..21764499b4be 100644 --- a/drivers/gpu/drm/nouveau/nvif/event.h +++ b/drivers/gpu/drm/nouveau/nvif/event.h | |||
@@ -51,4 +51,12 @@ struct nvif_notify_conn_rep_v0 { | |||
51 | __u8 pad02[6]; | 51 | __u8 pad02[6]; |
52 | }; | 52 | }; |
53 | 53 | ||
54 | struct nvif_notify_uevent_req { | ||
55 | /* nvif_notify_req ... */ | ||
56 | }; | ||
57 | |||
58 | struct nvif_notify_uevent_rep { | ||
59 | /* nvif_notify_rep ... */ | ||
60 | }; | ||
61 | |||
54 | #endif | 62 | #endif |