drm/amd/powerplay: set UVD clocks bypass mode for Polaris10

Saves power when not in use.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2 files changed, 8 insertions, 1 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 670413fc37d0..b5f3b8ea12fe 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -858,7 +858,8 @@ static int uvd_v6_0_set_clockgating_state(void *handle,
         bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
         static int curstate = -1;
 
-        if (adev->asic_type == CHIP_FIJI)
+        if (adev->asic_type == CHIP_FIJI ||
+                        adev->asic_type == CHIP_POLARIS10)
                 uvd_v6_set_bypass_mode(adev, enable);
 
         if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c
index 8f142a74ad08..aeec25c66aa8 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c
@@ -106,11 +106,17 @@ int polaris10_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
         data->uvd_power_gated = bgate;
 
         if (bgate) {
+                cgs_set_clockgating_state(hwmgr->device,
+                                AMD_IP_BLOCK_TYPE_UVD,
+                                AMD_CG_STATE_GATE);
                 polaris10_update_uvd_dpm(hwmgr, true);
                 polaris10_phm_powerdown_uvd(hwmgr);
         } else {
                 polaris10_phm_powerup_uvd(hwmgr);
                 polaris10_update_uvd_dpm(hwmgr, false);
+                cgs_set_clockgating_state(hwmgr->device,
+                                AMD_IP_BLOCK_TYPE_UVD,
+                                AMD_PG_STATE_UNGATE);
         }
 
         return 0;