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authorRodrigo Vivi <rodrigo.vivi@gmail.com>2013-02-25 17:55:16 -0500
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-03-03 12:24:52 -0500
commit7d9bcebe13397f6621a44b998860ae0c8049b10c (patch)
tree0f98dc57b6b2c8f4a1a6974d1c7f58382ea52251 /drivers/gpu
parent46c06a30dfd63b1200dda2337c145e262798b9cf (diff)
drm/i915: Use cpu_transcoder for HSW_TVIDEO_DIP_* instead of pipe
While old platforms had 3 transcoders and 3 pipes (1:1), HSW has 4 transcoders and 3 pipes. These regs were being used only by HDMI code where pipe is always the same thing as cpu_transcoder. This patch allow us to use them for DP, specially for TRANSCODER_EDP. v2: Adding HSW_TVIDEO_DIP_VSC_DATA to transmit vsc to eDP. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h18
-rw-r--r--drivers/gpu/drm/i915/intel_hdmi.c13
2 files changed, 17 insertions, 14 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cd226c21e156..c6d482fdf89b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3758,14 +3758,16 @@
3758#define HSW_VIDEO_DIP_VSC_ECC_B 0x61344 3758#define HSW_VIDEO_DIP_VSC_ECC_B 0x61344
3759#define HSW_VIDEO_DIP_GCP_B 0x61210 3759#define HSW_VIDEO_DIP_GCP_B 0x61210
3760 3760
3761#define HSW_TVIDEO_DIP_CTL(pipe) \ 3761#define HSW_TVIDEO_DIP_CTL(trans) \
3762 _PIPE(pipe, HSW_VIDEO_DIP_CTL_A, HSW_VIDEO_DIP_CTL_B) 3762 _TRANSCODER(trans, HSW_VIDEO_DIP_CTL_A, HSW_VIDEO_DIP_CTL_B)
3763#define HSW_TVIDEO_DIP_AVI_DATA(pipe) \ 3763#define HSW_TVIDEO_DIP_AVI_DATA(trans) \
3764 _PIPE(pipe, HSW_VIDEO_DIP_AVI_DATA_A, HSW_VIDEO_DIP_AVI_DATA_B) 3764 _TRANSCODER(trans, HSW_VIDEO_DIP_AVI_DATA_A, HSW_VIDEO_DIP_AVI_DATA_B)
3765#define HSW_TVIDEO_DIP_SPD_DATA(pipe) \ 3765#define HSW_TVIDEO_DIP_SPD_DATA(trans) \
3766 _PIPE(pipe, HSW_VIDEO_DIP_SPD_DATA_A, HSW_VIDEO_DIP_SPD_DATA_B) 3766 _TRANSCODER(trans, HSW_VIDEO_DIP_SPD_DATA_A, HSW_VIDEO_DIP_SPD_DATA_B)
3767#define HSW_TVIDEO_DIP_GCP(pipe) \ 3767#define HSW_TVIDEO_DIP_GCP(trans) \
3768 _PIPE(pipe, HSW_VIDEO_DIP_GCP_A, HSW_VIDEO_DIP_GCP_B) 3768 _TRANSCODER(trans, HSW_VIDEO_DIP_GCP_A, HSW_VIDEO_DIP_GCP_B)
3769#define HSW_TVIDEO_DIP_VSC_DATA(trans) \
3770 _TRANSCODER(trans, HSW_VIDEO_DIP_VSC_DATA_A, HSW_VIDEO_DIP_VSC_DATA_B)
3769 3771
3770#define _TRANS_HTOTAL_B 0xe1000 3772#define _TRANS_HTOTAL_B 0xe1000
3771#define _TRANS_HBLANK_B 0xe1004 3773#define _TRANS_HBLANK_B 0xe1004
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index fcb36c6b4434..6046db0e9f8a 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -120,13 +120,14 @@ static u32 hsw_infoframe_enable(struct dip_infoframe *frame)
120 } 120 }
121} 121}
122 122
123static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame, enum pipe pipe) 123static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame,
124 enum transcoder cpu_transcoder)
124{ 125{
125 switch (frame->type) { 126 switch (frame->type) {
126 case DIP_TYPE_AVI: 127 case DIP_TYPE_AVI:
127 return HSW_TVIDEO_DIP_AVI_DATA(pipe); 128 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);
128 case DIP_TYPE_SPD: 129 case DIP_TYPE_SPD:
129 return HSW_TVIDEO_DIP_SPD_DATA(pipe); 130 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);
130 default: 131 default:
131 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); 132 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
132 return 0; 133 return 0;
@@ -293,8 +294,8 @@ static void hsw_write_infoframe(struct drm_encoder *encoder,
293 struct drm_device *dev = encoder->dev; 294 struct drm_device *dev = encoder->dev;
294 struct drm_i915_private *dev_priv = dev->dev_private; 295 struct drm_i915_private *dev_priv = dev->dev_private;
295 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 296 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
296 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe); 297 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->cpu_transcoder);
297 u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->pipe); 298 u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->cpu_transcoder);
298 unsigned int i, len = DIP_HEADER_SIZE + frame->len; 299 unsigned int i, len = DIP_HEADER_SIZE + frame->len;
299 u32 val = I915_READ(ctl_reg); 300 u32 val = I915_READ(ctl_reg);
300 301
@@ -568,7 +569,7 @@ static void hsw_set_infoframes(struct drm_encoder *encoder,
568 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 569 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
569 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 570 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
570 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 571 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
571 u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe); 572 u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->cpu_transcoder);
572 u32 val = I915_READ(reg); 573 u32 val = I915_READ(reg);
573 574
574 assert_hdmi_port_disabled(intel_hdmi); 575 assert_hdmi_port_disabled(intel_hdmi);