diff options
author | Dave Airlie <airlied@redhat.com> | 2018-05-29 21:05:26 -0400 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2018-05-29 21:05:35 -0400 |
commit | 74860cbfdd41e7490f506eae08a0e633be95cc0f (patch) | |
tree | 4503cbedab99007c8eb5a1b433ea55e6c86a30dd /drivers/gpu | |
parent | dd41fb8547c2422f3a3a75e7226525e8bba9381c (diff) | |
parent | 19832055e2bf5e67f506bac62e4e07326fb545b7 (diff) |
Merge tag 'exynos-drm-next-for-v4.18-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next
Add more HW overlays support
- It enables hardware overlay number 4 and 5. For this,
this patch series adds required clocks.
Several fixups
- Fix default value of zpos according to real hardware overlay number.
- Fix error value of exynos_Drm_crtc_get_by_type function correctly.
- Fix static checker warning of scaler_task_done function.
- Fix signedness bug in fimc_setup_clocks function.
One cleanup
- Disable framedone interrupt of DSI device which is not required.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1527229919-25665-1-git-send-email-inki.dae@samsung.com
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 21 | ||||
-rw-r--r-- | drivers/gpu/drm/exynos/exynos_drm_crtc.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/exynos/exynos_drm_dsi.c | 6 | ||||
-rw-r--r-- | drivers/gpu/drm/exynos/exynos_drm_fimc.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/exynos/exynos_drm_plane.c | 9 | ||||
-rw-r--r-- | drivers/gpu/drm/exynos/exynos_drm_scaler.c | 2 |
6 files changed, 22 insertions, 20 deletions
diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c index 1c330f2a7a5d..82c95c34447f 100644 --- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c +++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c | |||
@@ -31,7 +31,10 @@ | |||
31 | #define DSD_CFG_MUX 0x1004 | 31 | #define DSD_CFG_MUX 0x1004 |
32 | #define DSD_CFG_MUX_TE_UNMASK_GLOBAL BIT(13) | 32 | #define DSD_CFG_MUX_TE_UNMASK_GLOBAL BIT(13) |
33 | 33 | ||
34 | #define WINDOWS_NR 3 | 34 | #define WINDOWS_NR 5 |
35 | #define PRIMARY_WIN 2 | ||
36 | #define CURSON_WIN 4 | ||
37 | |||
35 | #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 | 38 | #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 |
36 | 39 | ||
37 | #define I80_HW_TRG (1 << 0) | 40 | #define I80_HW_TRG (1 << 0) |
@@ -43,6 +46,9 @@ static const char * const decon_clks_name[] = { | |||
43 | "aclk_smmu_decon0x", | 46 | "aclk_smmu_decon0x", |
44 | "aclk_xiu_decon0x", | 47 | "aclk_xiu_decon0x", |
45 | "pclk_smmu_decon0x", | 48 | "pclk_smmu_decon0x", |
49 | "aclk_smmu_decon1x", | ||
50 | "aclk_xiu_decon1x", | ||
51 | "pclk_smmu_decon1x", | ||
46 | "sclk_decon_vclk", | 52 | "sclk_decon_vclk", |
47 | "sclk_decon_eclk", | 53 | "sclk_decon_eclk", |
48 | }; | 54 | }; |
@@ -74,9 +80,8 @@ static const uint32_t decon_formats[] = { | |||
74 | }; | 80 | }; |
75 | 81 | ||
76 | static const enum drm_plane_type decon_win_types[WINDOWS_NR] = { | 82 | static const enum drm_plane_type decon_win_types[WINDOWS_NR] = { |
77 | DRM_PLANE_TYPE_PRIMARY, | 83 | [PRIMARY_WIN] = DRM_PLANE_TYPE_PRIMARY, |
78 | DRM_PLANE_TYPE_OVERLAY, | 84 | [CURSON_WIN] = DRM_PLANE_TYPE_CURSOR, |
79 | DRM_PLANE_TYPE_CURSOR, | ||
80 | }; | 85 | }; |
81 | 86 | ||
82 | static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask, | 87 | static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask, |
@@ -552,12 +557,10 @@ static int decon_bind(struct device *dev, struct device *master, void *data) | |||
552 | drm_dev->max_vblank_count = 0xffffffff; | 557 | drm_dev->max_vblank_count = 0xffffffff; |
553 | 558 | ||
554 | for (win = ctx->first_win; win < WINDOWS_NR; win++) { | 559 | for (win = ctx->first_win; win < WINDOWS_NR; win++) { |
555 | int tmp = (win == ctx->first_win) ? 0 : win; | ||
556 | |||
557 | ctx->configs[win].pixel_formats = decon_formats; | 560 | ctx->configs[win].pixel_formats = decon_formats; |
558 | ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats); | 561 | ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats); |
559 | ctx->configs[win].zpos = win; | 562 | ctx->configs[win].zpos = win - ctx->first_win; |
560 | ctx->configs[win].type = decon_win_types[tmp]; | 563 | ctx->configs[win].type = decon_win_types[win]; |
561 | 564 | ||
562 | ret = exynos_plane_init(drm_dev, &ctx->planes[win], win, | 565 | ret = exynos_plane_init(drm_dev, &ctx->planes[win], win, |
563 | &ctx->configs[win]); | 566 | &ctx->configs[win]); |
@@ -565,7 +568,7 @@ static int decon_bind(struct device *dev, struct device *master, void *data) | |||
565 | return ret; | 568 | return ret; |
566 | } | 569 | } |
567 | 570 | ||
568 | exynos_plane = &ctx->planes[ctx->first_win]; | 571 | exynos_plane = &ctx->planes[PRIMARY_WIN]; |
569 | out_type = (ctx->out_type & IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI | 572 | out_type = (ctx->out_type & IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI |
570 | : EXYNOS_DISPLAY_TYPE_LCD; | 573 | : EXYNOS_DISPLAY_TYPE_LCD; |
571 | ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, | 574 | ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, |
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c b/drivers/gpu/drm/exynos/exynos_drm_crtc.c index dc01342e759a..eea90251808f 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c +++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c | |||
@@ -228,7 +228,7 @@ struct exynos_drm_crtc *exynos_drm_crtc_get_by_type(struct drm_device *drm_dev, | |||
228 | if (to_exynos_crtc(crtc)->type == out_type) | 228 | if (to_exynos_crtc(crtc)->type == out_type) |
229 | return to_exynos_crtc(crtc); | 229 | return to_exynos_crtc(crtc); |
230 | 230 | ||
231 | return ERR_PTR(-EPERM); | 231 | return ERR_PTR(-ENODEV); |
232 | } | 232 | } |
233 | 233 | ||
234 | int exynos_drm_set_possible_crtcs(struct drm_encoder *encoder, | 234 | int exynos_drm_set_possible_crtcs(struct drm_encoder *encoder, |
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index eae44fd714f0..7c3030b7e586 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c | |||
@@ -1264,15 +1264,15 @@ static irqreturn_t exynos_dsi_irq(int irq, void *dev_id) | |||
1264 | 1264 | ||
1265 | if (status & DSIM_INT_SW_RST_RELEASE) { | 1265 | if (status & DSIM_INT_SW_RST_RELEASE) { |
1266 | u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY | | 1266 | u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY | |
1267 | DSIM_INT_SFR_HDR_FIFO_EMPTY | DSIM_INT_FRAME_DONE | | 1267 | DSIM_INT_SFR_HDR_FIFO_EMPTY | DSIM_INT_RX_ECC_ERR | |
1268 | DSIM_INT_RX_ECC_ERR | DSIM_INT_SW_RST_RELEASE); | 1268 | DSIM_INT_SW_RST_RELEASE); |
1269 | exynos_dsi_write(dsi, DSIM_INTMSK_REG, mask); | 1269 | exynos_dsi_write(dsi, DSIM_INTMSK_REG, mask); |
1270 | complete(&dsi->completed); | 1270 | complete(&dsi->completed); |
1271 | return IRQ_HANDLED; | 1271 | return IRQ_HANDLED; |
1272 | } | 1272 | } |
1273 | 1273 | ||
1274 | if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY | | 1274 | if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY | |
1275 | DSIM_INT_FRAME_DONE | DSIM_INT_PLL_STABLE))) | 1275 | DSIM_INT_PLL_STABLE))) |
1276 | return IRQ_HANDLED; | 1276 | return IRQ_HANDLED; |
1277 | 1277 | ||
1278 | if (exynos_dsi_transfer_finish(dsi)) | 1278 | if (exynos_dsi_transfer_finish(dsi)) |
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimc.c b/drivers/gpu/drm/exynos/exynos_drm_fimc.c index 4dfbfc7f3b84..5ce84025d1cb 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimc.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimc.c | |||
@@ -1200,7 +1200,7 @@ e_clk_free: | |||
1200 | 1200 | ||
1201 | int exynos_drm_check_fimc_device(struct device *dev) | 1201 | int exynos_drm_check_fimc_device(struct device *dev) |
1202 | { | 1202 | { |
1203 | unsigned int id = of_alias_get_id(dev->of_node, "fimc"); | 1203 | int id = of_alias_get_id(dev->of_node, "fimc"); |
1204 | 1204 | ||
1205 | if (id >= 0 && (BIT(id) & fimc_mask)) | 1205 | if (id >= 0 && (BIT(id) & fimc_mask)) |
1206 | return 0; | 1206 | return 0; |
diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c b/drivers/gpu/drm/exynos/exynos_drm_plane.c index d2a90dae5c71..38a2a7f1204b 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_plane.c +++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c | |||
@@ -289,13 +289,12 @@ static const struct drm_plane_helper_funcs plane_helper_funcs = { | |||
289 | }; | 289 | }; |
290 | 290 | ||
291 | static void exynos_plane_attach_zpos_property(struct drm_plane *plane, | 291 | static void exynos_plane_attach_zpos_property(struct drm_plane *plane, |
292 | bool immutable) | 292 | int zpos, bool immutable) |
293 | { | 293 | { |
294 | /* FIXME */ | ||
295 | if (immutable) | 294 | if (immutable) |
296 | drm_plane_create_zpos_immutable_property(plane, 0); | 295 | drm_plane_create_zpos_immutable_property(plane, zpos); |
297 | else | 296 | else |
298 | drm_plane_create_zpos_property(plane, 0, 0, MAX_PLANE - 1); | 297 | drm_plane_create_zpos_property(plane, zpos, 0, MAX_PLANE - 1); |
299 | } | 298 | } |
300 | 299 | ||
301 | int exynos_plane_init(struct drm_device *dev, | 300 | int exynos_plane_init(struct drm_device *dev, |
@@ -320,7 +319,7 @@ int exynos_plane_init(struct drm_device *dev, | |||
320 | exynos_plane->index = index; | 319 | exynos_plane->index = index; |
321 | exynos_plane->config = config; | 320 | exynos_plane->config = config; |
322 | 321 | ||
323 | exynos_plane_attach_zpos_property(&exynos_plane->base, | 322 | exynos_plane_attach_zpos_property(&exynos_plane->base, config->zpos, |
324 | !(config->capabilities & EXYNOS_DRM_PLANE_CAP_ZPOS)); | 323 | !(config->capabilities & EXYNOS_DRM_PLANE_CAP_ZPOS)); |
325 | 324 | ||
326 | return 0; | 325 | return 0; |
diff --git a/drivers/gpu/drm/exynos/exynos_drm_scaler.c b/drivers/gpu/drm/exynos/exynos_drm_scaler.c index 63b05b7c846a..91d4382343d0 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_scaler.c +++ b/drivers/gpu/drm/exynos/exynos_drm_scaler.c | |||
@@ -397,7 +397,7 @@ static inline u32 scaler_get_int_status(struct scaler_context *scaler) | |||
397 | return scaler_read(SCALER_INT_STATUS); | 397 | return scaler_read(SCALER_INT_STATUS); |
398 | } | 398 | } |
399 | 399 | ||
400 | static inline bool scaler_task_done(u32 val) | 400 | static inline int scaler_task_done(u32 val) |
401 | { | 401 | { |
402 | return val & SCALER_INT_STATUS_FRAME_END ? 0 : -EINVAL; | 402 | return val & SCALER_INT_STATUS_FRAME_END ? 0 : -EINVAL; |
403 | } | 403 | } |