diff options
author | Alex Deucher <alexander.deucher@amd.com> | 2017-06-07 13:31:32 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2017-06-07 18:20:41 -0400 |
commit | 71c37505e7eaa01fa259debad1a71a7ae061039d (patch) | |
tree | 2c8be48756c40c0407ba35f579d7f33d38aefc85 /drivers/gpu | |
parent | 2db0cdbe2879f424e28f69755a16344348247d44 (diff) |
drm/amdgpu/gfx: move more common KIQ code to amdgpu_gfx.c
Lots more common stuff.
Reviewed-by: Alex Xie <AlexBin.Xie@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 103 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 11 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 110 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 109 |
4 files changed, 122 insertions, 211 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index 51a9708290dc..c5aa465231c4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | |||
@@ -145,3 +145,106 @@ void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev) | |||
145 | if (WARN_ON(adev->gfx.num_compute_rings > AMDGPU_MAX_COMPUTE_RINGS)) | 145 | if (WARN_ON(adev->gfx.num_compute_rings > AMDGPU_MAX_COMPUTE_RINGS)) |
146 | adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS; | 146 | adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS; |
147 | } | 147 | } |
148 | |||
149 | static int amdgpu_gfx_kiq_acquire(struct amdgpu_device *adev, | ||
150 | struct amdgpu_ring *ring) | ||
151 | { | ||
152 | int queue_bit; | ||
153 | int mec, pipe, queue; | ||
154 | |||
155 | queue_bit = adev->gfx.mec.num_mec | ||
156 | * adev->gfx.mec.num_pipe_per_mec | ||
157 | * adev->gfx.mec.num_queue_per_pipe; | ||
158 | |||
159 | while (queue_bit-- >= 0) { | ||
160 | if (test_bit(queue_bit, adev->gfx.mec.queue_bitmap)) | ||
161 | continue; | ||
162 | |||
163 | amdgpu_gfx_bit_to_queue(adev, queue_bit, &mec, &pipe, &queue); | ||
164 | |||
165 | /* Using pipes 2/3 from MEC 2 seems cause problems */ | ||
166 | if (mec == 1 && pipe > 1) | ||
167 | continue; | ||
168 | |||
169 | ring->me = mec + 1; | ||
170 | ring->pipe = pipe; | ||
171 | ring->queue = queue; | ||
172 | |||
173 | return 0; | ||
174 | } | ||
175 | |||
176 | dev_err(adev->dev, "Failed to find a queue for KIQ\n"); | ||
177 | return -EINVAL; | ||
178 | } | ||
179 | |||
180 | int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, | ||
181 | struct amdgpu_ring *ring, | ||
182 | struct amdgpu_irq_src *irq) | ||
183 | { | ||
184 | struct amdgpu_kiq *kiq = &adev->gfx.kiq; | ||
185 | int r = 0; | ||
186 | |||
187 | mutex_init(&kiq->ring_mutex); | ||
188 | |||
189 | r = amdgpu_wb_get(adev, &adev->virt.reg_val_offs); | ||
190 | if (r) | ||
191 | return r; | ||
192 | |||
193 | ring->adev = NULL; | ||
194 | ring->ring_obj = NULL; | ||
195 | ring->use_doorbell = true; | ||
196 | ring->doorbell_index = AMDGPU_DOORBELL_KIQ; | ||
197 | |||
198 | r = amdgpu_gfx_kiq_acquire(adev, ring); | ||
199 | if (r) | ||
200 | return r; | ||
201 | |||
202 | ring->eop_gpu_addr = kiq->eop_gpu_addr; | ||
203 | sprintf(ring->name, "kiq %d.%d.%d", ring->me, ring->pipe, ring->queue); | ||
204 | r = amdgpu_ring_init(adev, ring, 1024, | ||
205 | irq, AMDGPU_CP_KIQ_IRQ_DRIVER0); | ||
206 | if (r) | ||
207 | dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r); | ||
208 | |||
209 | return r; | ||
210 | } | ||
211 | |||
212 | void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring, | ||
213 | struct amdgpu_irq_src *irq) | ||
214 | { | ||
215 | amdgpu_wb_free(ring->adev, ring->adev->virt.reg_val_offs); | ||
216 | amdgpu_ring_fini(ring); | ||
217 | } | ||
218 | |||
219 | void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev) | ||
220 | { | ||
221 | struct amdgpu_kiq *kiq = &adev->gfx.kiq; | ||
222 | |||
223 | amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq->eop_gpu_addr, NULL); | ||
224 | } | ||
225 | |||
226 | int amdgpu_gfx_kiq_init(struct amdgpu_device *adev, | ||
227 | unsigned hpd_size) | ||
228 | { | ||
229 | int r; | ||
230 | u32 *hpd; | ||
231 | struct amdgpu_kiq *kiq = &adev->gfx.kiq; | ||
232 | |||
233 | r = amdgpu_bo_create_kernel(adev, hpd_size, PAGE_SIZE, | ||
234 | AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj, | ||
235 | &kiq->eop_gpu_addr, (void **)&hpd); | ||
236 | if (r) { | ||
237 | dev_warn(adev->dev, "failed to create KIQ bo (%d).\n", r); | ||
238 | return r; | ||
239 | } | ||
240 | |||
241 | memset(hpd, 0, hpd_size); | ||
242 | |||
243 | r = amdgpu_bo_reserve(kiq->eop_obj, true); | ||
244 | if (unlikely(r != 0)) | ||
245 | dev_warn(adev->dev, "(%d) reserve kiq eop bo failed\n", r); | ||
246 | amdgpu_bo_kunmap(kiq->eop_obj); | ||
247 | amdgpu_bo_unreserve(kiq->eop_obj); | ||
248 | |||
249 | return 0; | ||
250 | } | ||
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h index fa20438a7b4f..b1766fa4f29c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | |||
@@ -32,6 +32,17 @@ void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, | |||
32 | 32 | ||
33 | void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev); | 33 | void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev); |
34 | 34 | ||
35 | int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, | ||
36 | struct amdgpu_ring *ring, | ||
37 | struct amdgpu_irq_src *irq); | ||
38 | |||
39 | void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring, | ||
40 | struct amdgpu_irq_src *irq); | ||
41 | |||
42 | void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev); | ||
43 | int amdgpu_gfx_kiq_init(struct amdgpu_device *adev, | ||
44 | unsigned hpd_size); | ||
45 | |||
35 | /** | 46 | /** |
36 | * amdgpu_gfx_create_bitmask - create a bitmask | 47 | * amdgpu_gfx_create_bitmask - create a bitmask |
37 | * | 48 | * |
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index fc8e03bf7f41..8a9d35a9e02e 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | |||
@@ -1379,76 +1379,6 @@ static void gfx_v8_0_mec_fini(struct amdgpu_device *adev) | |||
1379 | } | 1379 | } |
1380 | } | 1380 | } |
1381 | 1381 | ||
1382 | static int gfx_v8_0_kiq_acquire(struct amdgpu_device *adev, | ||
1383 | struct amdgpu_ring *ring) | ||
1384 | { | ||
1385 | int queue_bit; | ||
1386 | int mec, pipe, queue; | ||
1387 | |||
1388 | queue_bit = adev->gfx.mec.num_mec | ||
1389 | * adev->gfx.mec.num_pipe_per_mec | ||
1390 | * adev->gfx.mec.num_queue_per_pipe; | ||
1391 | |||
1392 | while (queue_bit-- >= 0) { | ||
1393 | if (test_bit(queue_bit, adev->gfx.mec.queue_bitmap)) | ||
1394 | continue; | ||
1395 | |||
1396 | amdgpu_gfx_bit_to_queue(adev, queue_bit, &mec, &pipe, &queue); | ||
1397 | |||
1398 | /* Using pipes 2/3 from MEC 2 seems cause problems */ | ||
1399 | if (mec == 1 && pipe > 1) | ||
1400 | continue; | ||
1401 | |||
1402 | ring->me = mec + 1; | ||
1403 | ring->pipe = pipe; | ||
1404 | ring->queue = queue; | ||
1405 | |||
1406 | return 0; | ||
1407 | } | ||
1408 | |||
1409 | dev_err(adev->dev, "Failed to find a queue for KIQ\n"); | ||
1410 | return -EINVAL; | ||
1411 | } | ||
1412 | |||
1413 | static int gfx_v8_0_kiq_init_ring(struct amdgpu_device *adev, | ||
1414 | struct amdgpu_ring *ring, | ||
1415 | struct amdgpu_irq_src *irq) | ||
1416 | { | ||
1417 | struct amdgpu_kiq *kiq = &adev->gfx.kiq; | ||
1418 | int r = 0; | ||
1419 | |||
1420 | mutex_init(&kiq->ring_mutex); | ||
1421 | |||
1422 | r = amdgpu_wb_get(adev, &adev->virt.reg_val_offs); | ||
1423 | if (r) | ||
1424 | return r; | ||
1425 | |||
1426 | ring->adev = NULL; | ||
1427 | ring->ring_obj = NULL; | ||
1428 | ring->use_doorbell = true; | ||
1429 | ring->doorbell_index = AMDGPU_DOORBELL_KIQ; | ||
1430 | |||
1431 | r = gfx_v8_0_kiq_acquire(adev, ring); | ||
1432 | if (r) | ||
1433 | return r; | ||
1434 | |||
1435 | ring->eop_gpu_addr = kiq->eop_gpu_addr; | ||
1436 | sprintf(ring->name, "kiq %d.%d.%d", ring->me, ring->pipe, ring->queue); | ||
1437 | r = amdgpu_ring_init(adev, ring, 1024, | ||
1438 | irq, AMDGPU_CP_KIQ_IRQ_DRIVER0); | ||
1439 | if (r) | ||
1440 | dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r); | ||
1441 | |||
1442 | return r; | ||
1443 | } | ||
1444 | |||
1445 | static void gfx_v8_0_kiq_free_ring(struct amdgpu_ring *ring, | ||
1446 | struct amdgpu_irq_src *irq) | ||
1447 | { | ||
1448 | amdgpu_wb_free(ring->adev, ring->adev->virt.reg_val_offs); | ||
1449 | amdgpu_ring_fini(ring); | ||
1450 | } | ||
1451 | |||
1452 | static int gfx_v8_0_mec_init(struct amdgpu_device *adev) | 1382 | static int gfx_v8_0_mec_init(struct amdgpu_device *adev) |
1453 | { | 1383 | { |
1454 | int r; | 1384 | int r; |
@@ -1520,38 +1450,6 @@ static int gfx_v8_0_mec_init(struct amdgpu_device *adev) | |||
1520 | return 0; | 1450 | return 0; |
1521 | } | 1451 | } |
1522 | 1452 | ||
1523 | static void gfx_v8_0_kiq_fini(struct amdgpu_device *adev) | ||
1524 | { | ||
1525 | struct amdgpu_kiq *kiq = &adev->gfx.kiq; | ||
1526 | |||
1527 | amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq->eop_gpu_addr, NULL); | ||
1528 | } | ||
1529 | |||
1530 | static int gfx_v8_0_kiq_init(struct amdgpu_device *adev) | ||
1531 | { | ||
1532 | int r; | ||
1533 | u32 *hpd; | ||
1534 | struct amdgpu_kiq *kiq = &adev->gfx.kiq; | ||
1535 | |||
1536 | r = amdgpu_bo_create_kernel(adev, GFX8_MEC_HPD_SIZE, PAGE_SIZE, | ||
1537 | AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj, | ||
1538 | &kiq->eop_gpu_addr, (void **)&hpd); | ||
1539 | if (r) { | ||
1540 | dev_warn(adev->dev, "failed to create KIQ bo (%d).\n", r); | ||
1541 | return r; | ||
1542 | } | ||
1543 | |||
1544 | memset(hpd, 0, GFX8_MEC_HPD_SIZE); | ||
1545 | |||
1546 | r = amdgpu_bo_reserve(kiq->eop_obj, true); | ||
1547 | if (unlikely(r != 0)) | ||
1548 | dev_warn(adev->dev, "(%d) reserve kiq eop bo failed\n", r); | ||
1549 | amdgpu_bo_kunmap(kiq->eop_obj); | ||
1550 | amdgpu_bo_unreserve(kiq->eop_obj); | ||
1551 | |||
1552 | return 0; | ||
1553 | } | ||
1554 | |||
1555 | static const u32 vgpr_init_compute_shader[] = | 1453 | static const u32 vgpr_init_compute_shader[] = |
1556 | { | 1454 | { |
1557 | 0x7e000209, 0x7e020208, | 1455 | 0x7e000209, 0x7e020208, |
@@ -2192,14 +2090,14 @@ static int gfx_v8_0_sw_init(void *handle) | |||
2192 | } | 2090 | } |
2193 | } | 2091 | } |
2194 | 2092 | ||
2195 | r = gfx_v8_0_kiq_init(adev); | 2093 | r = amdgpu_gfx_kiq_init(adev, GFX8_MEC_HPD_SIZE); |
2196 | if (r) { | 2094 | if (r) { |
2197 | DRM_ERROR("Failed to init KIQ BOs!\n"); | 2095 | DRM_ERROR("Failed to init KIQ BOs!\n"); |
2198 | return r; | 2096 | return r; |
2199 | } | 2097 | } |
2200 | 2098 | ||
2201 | kiq = &adev->gfx.kiq; | 2099 | kiq = &adev->gfx.kiq; |
2202 | r = gfx_v8_0_kiq_init_ring(adev, &kiq->ring, &kiq->irq); | 2100 | r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); |
2203 | if (r) | 2101 | if (r) |
2204 | return r; | 2102 | return r; |
2205 | 2103 | ||
@@ -2251,8 +2149,8 @@ static int gfx_v8_0_sw_fini(void *handle) | |||
2251 | amdgpu_ring_fini(&adev->gfx.compute_ring[i]); | 2149 | amdgpu_ring_fini(&adev->gfx.compute_ring[i]); |
2252 | 2150 | ||
2253 | gfx_v8_0_compute_mqd_sw_fini(adev); | 2151 | gfx_v8_0_compute_mqd_sw_fini(adev); |
2254 | gfx_v8_0_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq); | 2152 | amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq); |
2255 | gfx_v8_0_kiq_fini(adev); | 2153 | amdgpu_gfx_kiq_fini(adev); |
2256 | 2154 | ||
2257 | gfx_v8_0_mec_fini(adev); | 2155 | gfx_v8_0_mec_fini(adev); |
2258 | gfx_v8_0_rlc_fini(adev); | 2156 | gfx_v8_0_rlc_fini(adev); |
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 6d30476f8a43..fbb9d208494b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | |||
@@ -969,107 +969,6 @@ static int gfx_v9_0_mec_init(struct amdgpu_device *adev) | |||
969 | return 0; | 969 | return 0; |
970 | } | 970 | } |
971 | 971 | ||
972 | static void gfx_v9_0_kiq_fini(struct amdgpu_device *adev) | ||
973 | { | ||
974 | struct amdgpu_kiq *kiq = &adev->gfx.kiq; | ||
975 | |||
976 | amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq->eop_gpu_addr, NULL); | ||
977 | } | ||
978 | |||
979 | static int gfx_v9_0_kiq_init(struct amdgpu_device *adev) | ||
980 | { | ||
981 | int r; | ||
982 | u32 *hpd; | ||
983 | struct amdgpu_kiq *kiq = &adev->gfx.kiq; | ||
984 | |||
985 | r = amdgpu_bo_create_kernel(adev, GFX9_MEC_HPD_SIZE, PAGE_SIZE, | ||
986 | AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj, | ||
987 | &kiq->eop_gpu_addr, (void **)&hpd); | ||
988 | if (r) { | ||
989 | dev_warn(adev->dev, "failed to create KIQ bo (%d).\n", r); | ||
990 | return r; | ||
991 | } | ||
992 | |||
993 | memset(hpd, 0, GFX9_MEC_HPD_SIZE); | ||
994 | |||
995 | r = amdgpu_bo_reserve(kiq->eop_obj, true); | ||
996 | if (unlikely(r != 0)) | ||
997 | dev_warn(adev->dev, "(%d) reserve kiq eop bo failed\n", r); | ||
998 | amdgpu_bo_kunmap(kiq->eop_obj); | ||
999 | amdgpu_bo_unreserve(kiq->eop_obj); | ||
1000 | |||
1001 | return 0; | ||
1002 | } | ||
1003 | |||
1004 | static int gfx_v9_0_kiq_acquire(struct amdgpu_device *adev, | ||
1005 | struct amdgpu_ring *ring) | ||
1006 | { | ||
1007 | int queue_bit; | ||
1008 | int mec, pipe, queue; | ||
1009 | |||
1010 | queue_bit = adev->gfx.mec.num_mec | ||
1011 | * adev->gfx.mec.num_pipe_per_mec | ||
1012 | * adev->gfx.mec.num_queue_per_pipe; | ||
1013 | |||
1014 | while (queue_bit-- >= 0) { | ||
1015 | if (test_bit(queue_bit, adev->gfx.mec.queue_bitmap)) | ||
1016 | continue; | ||
1017 | |||
1018 | amdgpu_gfx_bit_to_queue(adev, queue_bit, &mec, &pipe, &queue); | ||
1019 | |||
1020 | /* Using pipes 2/3 from MEC 2 seems cause problems */ | ||
1021 | if (mec == 1 && pipe > 1) | ||
1022 | continue; | ||
1023 | |||
1024 | ring->me = mec + 1; | ||
1025 | ring->pipe = pipe; | ||
1026 | ring->queue = queue; | ||
1027 | |||
1028 | return 0; | ||
1029 | } | ||
1030 | |||
1031 | dev_err(adev->dev, "Failed to find a queue for KIQ\n"); | ||
1032 | return -EINVAL; | ||
1033 | } | ||
1034 | |||
1035 | static int gfx_v9_0_kiq_init_ring(struct amdgpu_device *adev, | ||
1036 | struct amdgpu_ring *ring, | ||
1037 | struct amdgpu_irq_src *irq) | ||
1038 | { | ||
1039 | struct amdgpu_kiq *kiq = &adev->gfx.kiq; | ||
1040 | int r = 0; | ||
1041 | |||
1042 | mutex_init(&kiq->ring_mutex); | ||
1043 | |||
1044 | r = amdgpu_wb_get(adev, &adev->virt.reg_val_offs); | ||
1045 | if (r) | ||
1046 | return r; | ||
1047 | |||
1048 | ring->adev = NULL; | ||
1049 | ring->ring_obj = NULL; | ||
1050 | ring->use_doorbell = true; | ||
1051 | ring->doorbell_index = AMDGPU_DOORBELL_KIQ; | ||
1052 | |||
1053 | r = gfx_v9_0_kiq_acquire(adev, ring); | ||
1054 | if (r) | ||
1055 | return r; | ||
1056 | |||
1057 | ring->eop_gpu_addr = kiq->eop_gpu_addr; | ||
1058 | sprintf(ring->name, "kiq %d.%d.%d", ring->me, ring->pipe, ring->queue); | ||
1059 | r = amdgpu_ring_init(adev, ring, 1024, | ||
1060 | irq, AMDGPU_CP_KIQ_IRQ_DRIVER0); | ||
1061 | if (r) | ||
1062 | dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r); | ||
1063 | |||
1064 | return r; | ||
1065 | } | ||
1066 | static void gfx_v9_0_kiq_free_ring(struct amdgpu_ring *ring, | ||
1067 | struct amdgpu_irq_src *irq) | ||
1068 | { | ||
1069 | amdgpu_wb_free(ring->adev, ring->adev->virt.reg_val_offs); | ||
1070 | amdgpu_ring_fini(ring); | ||
1071 | } | ||
1072 | |||
1073 | /* create MQD for each compute queue */ | 972 | /* create MQD for each compute queue */ |
1074 | static int gfx_v9_0_compute_mqd_sw_init(struct amdgpu_device *adev) | 973 | static int gfx_v9_0_compute_mqd_sw_init(struct amdgpu_device *adev) |
1075 | { | 974 | { |
@@ -1570,14 +1469,14 @@ static int gfx_v9_0_sw_init(void *handle) | |||
1570 | } | 1469 | } |
1571 | } | 1470 | } |
1572 | 1471 | ||
1573 | r = gfx_v9_0_kiq_init(adev); | 1472 | r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE); |
1574 | if (r) { | 1473 | if (r) { |
1575 | DRM_ERROR("Failed to init KIQ BOs!\n"); | 1474 | DRM_ERROR("Failed to init KIQ BOs!\n"); |
1576 | return r; | 1475 | return r; |
1577 | } | 1476 | } |
1578 | 1477 | ||
1579 | kiq = &adev->gfx.kiq; | 1478 | kiq = &adev->gfx.kiq; |
1580 | r = gfx_v9_0_kiq_init_ring(adev, &kiq->ring, &kiq->irq); | 1479 | r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); |
1581 | if (r) | 1480 | if (r) |
1582 | return r; | 1481 | return r; |
1583 | 1482 | ||
@@ -1632,8 +1531,8 @@ static int gfx_v9_0_sw_fini(void *handle) | |||
1632 | amdgpu_ring_fini(&adev->gfx.compute_ring[i]); | 1531 | amdgpu_ring_fini(&adev->gfx.compute_ring[i]); |
1633 | 1532 | ||
1634 | gfx_v9_0_compute_mqd_sw_fini(adev); | 1533 | gfx_v9_0_compute_mqd_sw_fini(adev); |
1635 | gfx_v9_0_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq); | 1534 | amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq); |
1636 | gfx_v9_0_kiq_fini(adev); | 1535 | amdgpu_gfx_kiq_fini(adev); |
1637 | 1536 | ||
1638 | gfx_v9_0_mec_fini(adev); | 1537 | gfx_v9_0_mec_fini(adev); |
1639 | gfx_v9_0_ngg_fini(adev); | 1538 | gfx_v9_0_ngg_fini(adev); |