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authorMonk Liu <Monk.Liu@amd.com>2017-10-17 02:39:23 -0400
committerAlex Deucher <alexander.deucher@amd.com>2017-12-04 16:33:11 -0500
commit668ca1b44de16a8182419cc1a5913d33cc6263bd (patch)
tree3f2068533efc7277604de16abc11727e39323233 /drivers/gpu
parenta4176cb484ac457a08b44c93da06fce09c6e281c (diff)
drm/amdgpu:don't change ctx->reset_couner upon query
reset_counter marks the reset counter number once the context is created, shouldn't be changed due to query. To keep U/K interface on the ctx_query and keep ctx's reset_counter logic compatible with GPU RESET feature, now use another var named "reset_counter_query" to replace the original checked & updated in amdgpu_ctx_query. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu.h1
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c5
2 files changed, 4 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 64a0d384171b..34268aac6b9a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -735,6 +735,7 @@ struct amdgpu_ctx {
735 struct amdgpu_device *adev; 735 struct amdgpu_device *adev;
736 struct amdgpu_queue_mgr queue_mgr; 736 struct amdgpu_queue_mgr queue_mgr;
737 unsigned reset_counter; 737 unsigned reset_counter;
738 unsigned reset_counter_query;
738 uint32_t vram_lost_counter; 739 uint32_t vram_lost_counter;
739 spinlock_t ring_lock; 740 spinlock_t ring_lock;
740 struct dma_fence **fences; 741 struct dma_fence **fences;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 1bf4cdc597aa..c539fb6a597e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -75,6 +75,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
75 } 75 }
76 76
77 ctx->reset_counter = atomic_read(&adev->gpu_reset_counter); 77 ctx->reset_counter = atomic_read(&adev->gpu_reset_counter);
78 ctx->reset_counter_query = ctx->reset_counter;
78 ctx->vram_lost_counter = atomic_read(&adev->vram_lost_counter); 79 ctx->vram_lost_counter = atomic_read(&adev->vram_lost_counter);
79 ctx->init_priority = priority; 80 ctx->init_priority = priority;
80 ctx->override_priority = AMD_SCHED_PRIORITY_UNSET; 81 ctx->override_priority = AMD_SCHED_PRIORITY_UNSET;
@@ -216,11 +217,11 @@ static int amdgpu_ctx_query(struct amdgpu_device *adev,
216 /* determine if a GPU reset has occured since the last call */ 217 /* determine if a GPU reset has occured since the last call */
217 reset_counter = atomic_read(&adev->gpu_reset_counter); 218 reset_counter = atomic_read(&adev->gpu_reset_counter);
218 /* TODO: this should ideally return NO, GUILTY, or INNOCENT. */ 219 /* TODO: this should ideally return NO, GUILTY, or INNOCENT. */
219 if (ctx->reset_counter == reset_counter) 220 if (ctx->reset_counter_query == reset_counter)
220 out->state.reset_status = AMDGPU_CTX_NO_RESET; 221 out->state.reset_status = AMDGPU_CTX_NO_RESET;
221 else 222 else
222 out->state.reset_status = AMDGPU_CTX_UNKNOWN_RESET; 223 out->state.reset_status = AMDGPU_CTX_UNKNOWN_RESET;
223 ctx->reset_counter = reset_counter; 224 ctx->reset_counter_query = reset_counter;
224 225
225 mutex_unlock(&mgr->lock); 226 mutex_unlock(&mgr->lock);
226 return 0; 227 return 0;