drm/amd/powerplay: use smu7 common functions and data on Fiji.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

3 files changed, 68 insertions, 635 deletions

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
index fd0c00173cce..76310ac7ef0d 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
@@ -42,6 +42,7 @@
 #include "bif/bif_5_0_sh_mask.h"
 #include "dce/dce_10_0_d.h"
 #include "dce/dce_10_0_sh_mask.h"
+#include "smu7_smumgr.h"
 
 #define VOLTAGE_SCALE 4
 #define POWERTUNE_DEFAULT_SET_MAX    1
@@ -337,7 +338,7 @@ static int fiji_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
         const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults;
         uint32_t temp;
 
-        if (fiji_read_smc_sram_dword(hwmgr->smumgr,
+        if (smu7_read_smc_sram_dword(hwmgr->smumgr,
                         fuse_table_offset +
                         offsetof(SMU73_Discrete_PmFuses, TdcWaterfallCtl),
                         (uint32_t *)&temp, SMC_RAM_END))
@@ -429,7 +430,7 @@ static int fiji_populate_pm_fuses(struct pp_hwmgr *hwmgr)
 
         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
                         PHM_PlatformCaps_PowerContainment)) {
-                if (fiji_read_smc_sram_dword(hwmgr->smumgr,
+                if (smu7_read_smc_sram_dword(hwmgr->smumgr,
                                 SMU7_FIRMWARE_HEADER_LOCATION +
                                 offsetof(SMU73_Firmware_Header, PmFuseTable),
                                 &pm_fuse_table_offset, SMC_RAM_END))
@@ -483,7 +484,7 @@ static int fiji_populate_pm_fuses(struct pp_hwmgr *hwmgr)
                                         "Attempt to populate BapmVddCBaseLeakage Hi and Lo "
                                         "Sidd Failed!", return -EINVAL);
 
-                if (fiji_copy_bytes_to_smc(hwmgr->smumgr, pm_fuse_table_offset,
+                if (smu7_copy_bytes_to_smc(hwmgr->smumgr, pm_fuse_table_offset,
                                 (uint8_t *)&smu_data->power_tune_table,
                                 sizeof(struct SMU73_Discrete_PmFuses), SMC_RAM_END))
                         PP_ASSERT_WITH_CODE(false,
@@ -781,7 +782,7 @@ int fiji_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
         struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
         uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count;
         int result = 0;
-        uint32_t array = smu_data->dpm_table_start +
+        uint32_t array = smu_data->smu7_data.dpm_table_start +
                         offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);
         uint32_t array_size = sizeof(struct SMU73_Discrete_GraphicsLevel) *
                         SMU73_MAX_LEVELS_GRAPHICS;
@@ -858,7 +859,7 @@ int fiji_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
                 levels[1].pcieDpmLevel = mid_pcie_level_enabled;
         }
         /* level count will send to smc once at init smc table and never change */
-        result = fiji_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
+        result = smu7_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
                         (uint32_t)array_size, SMC_RAM_END);
 
         return result;
@@ -1003,7 +1004,7 @@ int fiji_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
         struct smu7_dpm_table *dpm_table = &data->dpm_table;
         int result;
         /* populate MCLK dpm table to SMU7 */
-        uint32_t array = smu_data->dpm_table_start +
+        uint32_t array = smu_data->smu7_data.dpm_table_start +
                         offsetof(SMU73_Discrete_DpmTable, MemoryLevel);
         uint32_t array_size = sizeof(SMU73_Discrete_MemoryLevel) *
                         SMU73_MAX_LEVELS_MEMORY;
@@ -1042,7 +1043,7 @@ int fiji_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
                         PPSMC_DISPLAY_WATERMARK_HIGH;
 
         /* level count will send to smc once at init smc table and never change */
-        result = fiji_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
+        result = smu7_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
                         (uint32_t)array_size, SMC_RAM_END);
 
         return result;
@@ -1368,9 +1369,9 @@ static int fiji_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
         }
 
         if (!result)
-                result = fiji_copy_bytes_to_smc(
+                result = smu7_copy_bytes_to_smc(
                                 hwmgr->smumgr,
-                                smu_data->arb_table_start,
+                                smu_data->smu7_data.arb_table_start,
                                 (uint8_t *)&arb_regs,
                                 sizeof(SMU73_Discrete_MCArbDramTimingTable),
                                 SMC_RAM_END);
@@ -1707,8 +1708,8 @@ static int fiji_init_arb_table_index(struct pp_smumgr *smumgr)
          * In reality this field should not be in that structure
          * but in a soft register.
          */
-        result = fiji_read_smc_sram_dword(smumgr,
-                        smu_data->arb_table_start, &tmp, SMC_RAM_END);
+        result = smu7_read_smc_sram_dword(smumgr,
+                        smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END);
 
         if (result)
                 return result;
@@ -1716,8 +1717,8 @@ static int fiji_init_arb_table_index(struct pp_smumgr *smumgr)
         tmp &= 0x00FFFFFF;
         tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
 
-        return fiji_write_smc_sram_dword(smumgr,
-                        smu_data->arb_table_start,  tmp, SMC_RAM_END);
+        return smu7_write_smc_sram_dword(smumgr,
+                        smu_data->smu7_data.arb_table_start,  tmp, SMC_RAM_END);
 }
 
 /**
@@ -1917,8 +1918,8 @@ int fiji_init_smc_table(struct pp_hwmgr *hwmgr)
         CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
 
         /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
-        result = fiji_copy_bytes_to_smc(hwmgr->smumgr,
-                        smu_data->dpm_table_start +
+        result = smu7_copy_bytes_to_smc(hwmgr->smumgr,
+                        smu_data->smu7_data.dpm_table_start +
                         offsetof(SMU73_Discrete_DpmTable, SystemFlags),
                         (uint8_t *)&(table->SystemFlags),
                         sizeof(SMU73_Discrete_DpmTable) - 3 * sizeof(SMU73_PIDController),
@@ -1957,7 +1958,7 @@ int fiji_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
         int res;
         uint64_t tmp64;
 
-        if (smu_data->fan_table_start == 0) {
+        if (smu_data->smu7_data.fan_table_start == 0) {
                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
                                 PHM_PlatformCaps_MicrocodeFanControl);
                 return 0;
@@ -2023,7 +2024,7 @@ int fiji_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
                         hwmgr->device, CGS_IND_REG__SMC,
                         CG_MULT_THERMAL_CTRL, TEMP_SEL);
 
-        res = fiji_copy_bytes_to_smc(hwmgr->smumgr, smu_data->fan_table_start,
+        res = smu7_copy_bytes_to_smc(hwmgr->smumgr, smu_data->smu7_data.fan_table_start,
                         (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table),
                         SMC_RAM_END);
 
@@ -2078,9 +2079,9 @@ int fiji_update_sclk_threshold(struct pp_hwmgr *hwmgr)
 
                 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
 
-                result = fiji_copy_bytes_to_smc(
+                result = smu7_copy_bytes_to_smc(
                                 hwmgr->smumgr,
-                                smu_data->dpm_table_start +
+                                smu_data->smu7_data.dpm_table_start +
                                 offsetof(SMU73_Discrete_DpmTable,
                                         LowSclkInterruptThreshold),
                                 (uint8_t *)&low_sclk_interrupt_threshold,
@@ -2109,6 +2110,8 @@ uint32_t fiji_get_offsetof(uint32_t type, uint32_t member)
                         return offsetof(SMU73_SoftRegisters, PreVBlankGap);
                 case VBlankTimeout:
                         return offsetof(SMU73_SoftRegisters, VBlankTimeout);
+                case UcodeLoadStatus:
+                        return offsetof(SMU73_SoftRegisters, UcodeLoadStatus);
                 }
         case SMU_Discrete_DpmTable:
                 switch (member) {
@@ -2163,7 +2166,7 @@ static int fiji_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
         if (table_info->mm_dep_table->count > 0)
                 smu_data->smc_state_table.UvdBootLevel =
                                 (uint8_t) (table_info->mm_dep_table->count - 1);
-        mm_boot_level_offset = smu_data->dpm_table_start + offsetof(SMU73_Discrete_DpmTable,
+        mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU73_Discrete_DpmTable,
                                                 UvdBootLevel);
         mm_boot_level_offset /= 4;
         mm_boot_level_offset *= 4;
@@ -2198,7 +2201,7 @@ static int fiji_update_vce_smc_table(struct pp_hwmgr *hwmgr)
         else
                 smu_data->smc_state_table.VceBootLevel = 0;
 
-        mm_boot_level_offset = smu_data->dpm_table_start +
+        mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
                                         offsetof(SMU73_Discrete_DpmTable, VceBootLevel);
         mm_boot_level_offset /= 4;
         mm_boot_level_offset *= 4;
@@ -2223,7 +2226,7 @@ static int fiji_update_samu_smc_table(struct pp_hwmgr *hwmgr)
 
 
         smu_data->smc_state_table.SamuBootLevel = 0;
-        mm_boot_level_offset = smu_data->dpm_table_start +
+        mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
                                 offsetof(SMU73_Discrete_DpmTable, SamuBootLevel);
 
         mm_boot_level_offset /= 4;
@@ -2276,57 +2279,57 @@ int fiji_process_firmware_header(struct pp_hwmgr *hwmgr)
         int result;
         bool error = false;
 
-        result = fiji_read_smc_sram_dword(hwmgr->smumgr,
+        result = smu7_read_smc_sram_dword(hwmgr->smumgr,
                         SMU7_FIRMWARE_HEADER_LOCATION +
                         offsetof(SMU73_Firmware_Header, DpmTable),
                         &tmp, SMC_RAM_END);
 
         if (0 == result)
-                smu_data->dpm_table_start = tmp;
+                smu_data->smu7_data.dpm_table_start = tmp;
 
         error |= (0 != result);
 
-        result = fiji_read_smc_sram_dword(hwmgr->smumgr,
+        result = smu7_read_smc_sram_dword(hwmgr->smumgr,
                         SMU7_FIRMWARE_HEADER_LOCATION +
                         offsetof(SMU73_Firmware_Header, SoftRegisters),
                         &tmp, SMC_RAM_END);
 
         if (!result) {
                 data->soft_regs_start = tmp;
-                smu_data->soft_regs_start = tmp;
+                smu_data->smu7_data.soft_regs_start = tmp;
         }
 
         error |= (0 != result);
 
-        result = fiji_read_smc_sram_dword(hwmgr->smumgr,
+        result = smu7_read_smc_sram_dword(hwmgr->smumgr,
                         SMU7_FIRMWARE_HEADER_LOCATION +
                         offsetof(SMU73_Firmware_Header, mcRegisterTable),
                         &tmp, SMC_RAM_END);
 
         if (!result)
-                smu_data->mc_reg_table_start = tmp;
+                smu_data->smu7_data.mc_reg_table_start = tmp;
 
-        result = fiji_read_smc_sram_dword(hwmgr->smumgr,
+        result = smu7_read_smc_sram_dword(hwmgr->smumgr,
                         SMU7_FIRMWARE_HEADER_LOCATION +
                         offsetof(SMU73_Firmware_Header, FanTable),
                         &tmp, SMC_RAM_END);
 
         if (!result)
-                smu_data->fan_table_start = tmp;
+                smu_data->smu7_data.fan_table_start = tmp;
 
         error |= (0 != result);
 
-        result = fiji_read_smc_sram_dword(hwmgr->smumgr,
+        result = smu7_read_smc_sram_dword(hwmgr->smumgr,
                         SMU7_FIRMWARE_HEADER_LOCATION +
                         offsetof(SMU73_Firmware_Header, mcArbDramTimingTable),
                         &tmp, SMC_RAM_END);
 
         if (!result)
-                smu_data->arb_table_start = tmp;
+                smu_data->smu7_data.arb_table_start = tmp;
 
         error |= (0 != result);
 
-        result = fiji_read_smc_sram_dword(hwmgr->smumgr,
+        result = smu7_read_smc_sram_dword(hwmgr->smumgr,
                         SMU7_FIRMWARE_HEADER_LOCATION +
                         offsetof(SMU73_Firmware_Header, Version),
                         &tmp, SMC_RAM_END);
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
index 82a8be4af63b..02fe1df855a9 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
@@ -58,520 +58,6 @@ static const struct SMU73_Discrete_GraphicsLevel avfs_graphics_level[8] = {
                 { 0xf811d047, 0x80380100,   0x01,     0x00,   0x1e00, 0x00000610, 0x87020000, 0x21680000, 0x12000000,   0,      0,   0x0c,   0x01,       0x01,        0x01,      0x00,   0x00,      0x00,     0x00 }
 };
 
-static enum cgs_ucode_id fiji_convert_fw_type_to_cgs(uint32_t fw_type)
-{
-        enum cgs_ucode_id result = CGS_UCODE_ID_MAXIMUM;
-
-        switch (fw_type) {
-        case UCODE_ID_SMU:
-                result = CGS_UCODE_ID_SMU;
-                break;
-        case UCODE_ID_SDMA0:
-                result = CGS_UCODE_ID_SDMA0;
-                break;
-        case UCODE_ID_SDMA1:
-                result = CGS_UCODE_ID_SDMA1;
-                break;
-        case UCODE_ID_CP_CE:
-                result = CGS_UCODE_ID_CP_CE;
-                break;
-        case UCODE_ID_CP_PFP:
-                result = CGS_UCODE_ID_CP_PFP;
-                break;
-        case UCODE_ID_CP_ME:
-                result = CGS_UCODE_ID_CP_ME;
-                break;
-        case UCODE_ID_CP_MEC:
-                result = CGS_UCODE_ID_CP_MEC;
-                break;
-        case UCODE_ID_CP_MEC_JT1:
-                result = CGS_UCODE_ID_CP_MEC_JT1;
-                break;
-        case UCODE_ID_CP_MEC_JT2:
-                result = CGS_UCODE_ID_CP_MEC_JT2;
-                break;
-        case UCODE_ID_RLC_G:
-                result = CGS_UCODE_ID_RLC_G;
-                break;
-        default:
-                break;
-        }
-
-        return result;
-}
-/**
-* Set the address for reading/writing the SMC SRAM space.
-* @param    smumgr  the address of the powerplay hardware manager.
-* @param    smc_addr the address in the SMC RAM to access.
-*/
-static int fiji_set_smc_sram_address(struct pp_smumgr *smumgr,
-                uint32_t smc_addr, uint32_t limit)
-{
-        PP_ASSERT_WITH_CODE((0 == (3 & smc_addr)),
-                        "SMC address must be 4 byte aligned.", return -EINVAL;);
-        PP_ASSERT_WITH_CODE((limit > (smc_addr + 3)),
-                        "SMC address is beyond the SMC RAM area.", return -EINVAL;);
-
-        cgs_write_register(smumgr->device, mmSMC_IND_INDEX_0, smc_addr);
-        SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
-
-        return 0;
-}
-
-/**
-* Copy bytes from an array into the SMC RAM space.
-*
-* @param    smumgr  the address of the powerplay SMU manager.
-* @param    smcStartAddress the start address in the SMC RAM to copy bytes to.
-* @param    src the byte array to copy the bytes from.
-* @param    byteCount the number of bytes to copy.
-*/
-int fiji_copy_bytes_to_smc(struct pp_smumgr *smumgr,
-                uint32_t smcStartAddress, const uint8_t *src,
-                uint32_t byteCount, uint32_t limit)
-{
-        int result;
-        uint32_t data, originalData;
-        uint32_t addr, extraShift;
-
-        PP_ASSERT_WITH_CODE((0 == (3 & smcStartAddress)),
-                        "SMC address must be 4 byte aligned.", return -EINVAL;);
-        PP_ASSERT_WITH_CODE((limit > (smcStartAddress + byteCount)),
-                        "SMC address is beyond the SMC RAM area.", return -EINVAL;);
-
-        addr = smcStartAddress;
-
-        while (byteCount >= 4) {
-                /* Bytes are written into the SMC addres space with the MSB first. */
-                data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3];
-
-                result = fiji_set_smc_sram_address(smumgr, addr, limit);
-                if (result)
-                        return result;
-
-                cgs_write_register(smumgr->device, mmSMC_IND_DATA_0, data);
-
-                src += 4;
-                byteCount -= 4;
-                addr += 4;
-        }
-
-        if (byteCount) {
-                /* Now write the odd bytes left.
-                 * Do a read modify write cycle.
-                 */
-                data = 0;
-
-                result = fiji_set_smc_sram_address(smumgr, addr, limit);
-                if (result)
-                        return result;
-
-                originalData = cgs_read_register(smumgr->device, mmSMC_IND_DATA_0);
-                extraShift = 8 * (4 - byteCount);
-
-                while (byteCount > 0) {
-                        /* Bytes are written into the SMC addres
-                         * space with the MSB first.
-                         */
-                        data = (0x100 * data) + *src++;
-                        byteCount--;
-                }
-                data <<= extraShift;
-                data |= (originalData & ~((~0UL) << extraShift));
-
-                result = fiji_set_smc_sram_address(smumgr, addr, limit);
-                if (!result)
-                        return result;
-
-                cgs_write_register(smumgr->device, mmSMC_IND_DATA_0, data);
-        }
-        return 0;
-}
-
-int fiji_program_jump_on_start(struct pp_smumgr *smumgr)
-{
-        static const unsigned char data[] = { 0xE0, 0x00, 0x80, 0x40 };
-
-        fiji_copy_bytes_to_smc(smumgr, 0x0, data, 4, sizeof(data) + 1);
-
-        return 0;
-}
-
-/**
-* Return if the SMC is currently running.
-*
-* @param    smumgr  the address of the powerplay hardware manager.
-*/
-bool fiji_is_smc_ram_running(struct pp_smumgr *smumgr)
-{
-        return ((0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device,
-                        CGS_IND_REG__SMC,
-                        SMC_SYSCON_CLOCK_CNTL_0, ck_disable))
-                        && (0x20100 <= cgs_read_ind_register(smumgr->device,
-                                        CGS_IND_REG__SMC, ixSMC_PC_C)));
-}
-
-/**
-* Send a message to the SMC, and wait for its response.
-*
-* @param    smumgr  the address of the powerplay hardware manager.
-* @param    msg the message to send.
-* @return   The response that came from the SMC.
-*/
-int fiji_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
-{
-        int ret;
-
-        if (!fiji_is_smc_ram_running(smumgr))
-                return -1;
-
-
-        SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
-
-        ret = SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP);
-
-        if (ret != 1)
-                printk("\n failed to send pre message %x ret is %d \n",  msg, ret);
-
-        cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg);
-
-        SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
-
-        ret = SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP);
-
-        if (ret != 1)
-                printk("\n failed to send message %x ret is %d \n",  msg, ret);
-
-        return 0;
-}
-
-/**
- * Send a message to the SMC with parameter
- * @param    smumgr:  the address of the powerplay hardware manager.
- * @param    msg: the message to send.
- * @param    parameter: the parameter to send
- * @return   The response that came from the SMC.
- */
-int fiji_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
-                uint16_t msg, uint32_t parameter)
-{
-        if (!fiji_is_smc_ram_running(smumgr))
-                return -1;
-
-        if (1 != SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP)) {
-                printk(KERN_ERR "Failed to send Previous Message.");
-                SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
-        }
-
-        cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter);
-        cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg);
-        SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
-
-        return 0;
-}
-
-
-/**
-* Send a message to the SMC with parameter, do not wait for response
-*
-* @param    smumgr:  the address of the powerplay hardware manager.
-* @param    msg: the message to send.
-* @param    parameter: the parameter to send
-* @return   The response that came from the SMC.
-*/
-int fiji_send_msg_to_smc_with_parameter_without_waiting(
-                struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter)
-{
-        if (1 != SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP)) {
-                printk(KERN_ERR "Failed to send Previous Message.");
-                SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
-        }
-        cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter);
-        cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg);
-
-        return 0;
-}
-
-/**
-* Uploads the SMU firmware from .hex file
-*
-* @param    smumgr  the address of the powerplay SMU manager.
-* @return   0 or -1.
-*/
-
-static int fiji_upload_smu_firmware_image(struct pp_smumgr *smumgr)
-{
-        const uint8_t *src;
-        uint32_t byte_count;
-        uint32_t *data;
-        struct cgs_firmware_info info = {0};
-
-        cgs_get_firmware_info(smumgr->device,
-                        fiji_convert_fw_type_to_cgs(UCODE_ID_SMU), &info);
-
-        if (info.image_size & 3) {
-                printk(KERN_ERR "SMC ucode is not 4 bytes aligned\n");
-                return -EINVAL;
-        }
-
-        if (info.image_size > FIJI_SMC_SIZE) {
-                printk(KERN_ERR "SMC address is beyond the SMC RAM area\n");
-                return -EINVAL;
-        }
-
-        cgs_write_register(smumgr->device, mmSMC_IND_INDEX_0, 0x20000);
-        SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1);
-
-        byte_count = info.image_size;
-        src = (const uint8_t *)info.kptr;
-
-        data = (uint32_t *)src;
-        for (; byte_count >= 4; data++, byte_count -= 4)
-                cgs_write_register(smumgr->device, mmSMC_IND_DATA_0, data[0]);
-
-        SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
-        return 0;
-}
-
-/**
-* Read a 32bit value from the SMC SRAM space.
-* ALL PARAMETERS ARE IN HOST BYTE ORDER.
-* @param    smumgr  the address of the powerplay hardware manager.
-* @param    smc_addr the address in the SMC RAM to access.
-* @param    value and output parameter for the data read from the SMC SRAM.
-*/
-int fiji_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr,
-                uint32_t *value, uint32_t limit)
-{
-        int     result = fiji_set_smc_sram_address(smumgr, smc_addr, limit);
-
-        if (result)
-                return result;
-
-        *value = cgs_read_register(smumgr->device, mmSMC_IND_DATA_0);
-        return 0;
-}
-
-/**
-* Write a 32bit value to the SMC SRAM space.
-* ALL PARAMETERS ARE IN HOST BYTE ORDER.
-* @param    smumgr  the address of the powerplay hardware manager.
-* @param    smc_addr the address in the SMC RAM to access.
-* @param    value to write to the SMC SRAM.
-*/
-int fiji_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr,
-                uint32_t value, uint32_t limit)
-{
-        int result;
-
-        result = fiji_set_smc_sram_address(smumgr, smc_addr, limit);
-
-        if (result)
-                return result;
-
-        cgs_write_register(smumgr->device, mmSMC_IND_DATA_0, value);
-        return 0;
-}
-
-static uint32_t fiji_get_mask_for_firmware_type(uint32_t fw_type)
-{
-        uint32_t result = 0;
-
-        switch (fw_type) {
-        case UCODE_ID_SDMA0:
-                result = UCODE_ID_SDMA0_MASK;
-                break;
-        case UCODE_ID_SDMA1:
-                result = UCODE_ID_SDMA1_MASK;
-                break;
-        case UCODE_ID_CP_CE:
-                result = UCODE_ID_CP_CE_MASK;
-                break;
-        case UCODE_ID_CP_PFP:
-                result = UCODE_ID_CP_PFP_MASK;
-                break;
-        case UCODE_ID_CP_ME:
-                result = UCODE_ID_CP_ME_MASK;
-                break;
-        case UCODE_ID_CP_MEC_JT1:
-                result = UCODE_ID_CP_MEC_MASK | UCODE_ID_CP_MEC_JT1_MASK;
-                break;
-        case UCODE_ID_CP_MEC_JT2:
-                result = UCODE_ID_CP_MEC_MASK | UCODE_ID_CP_MEC_JT2_MASK;
-                break;
-        case UCODE_ID_RLC_G:
-                result = UCODE_ID_RLC_G_MASK;
-                break;
-        default:
-                printk(KERN_ERR "UCode type is out of range!");
-                result = 0;
-        }
-
-        return result;
-}
-
-/* Populate one firmware image to the data structure */
-static int fiji_populate_single_firmware_entry(struct pp_smumgr *smumgr,
-                uint32_t fw_type, struct SMU_Entry *entry)
-{
-        int result;
-        struct cgs_firmware_info info = {0};
-
-        result = cgs_get_firmware_info(
-                        smumgr->device,
-                        fiji_convert_fw_type_to_cgs(fw_type),
-                        &info);
-
-        if (!result) {
-                entry->version = 0;
-                entry->id = (uint16_t)fw_type;
-                entry->image_addr_high = smu_upper_32_bits(info.mc_addr);
-                entry->image_addr_low = smu_lower_32_bits(info.mc_addr);
-                entry->meta_data_addr_high = 0;
-                entry->meta_data_addr_low = 0;
-                entry->data_size_byte = info.image_size;
-                entry->num_register_entries = 0;
-
-                if (fw_type == UCODE_ID_RLC_G)
-                        entry->flags = 1;
-                else
-                        entry->flags = 0;
-        }
-
-        return result;
-}
-
-static int fiji_request_smu_load_fw(struct pp_smumgr *smumgr)
-{
-        struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend);
-        uint32_t fw_to_load;
-        struct SMU_DRAMData_TOC *toc;
-
-        if (priv->soft_regs_start)
-                cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
-                                priv->soft_regs_start +
-                                offsetof(SMU73_SoftRegisters, UcodeLoadStatus),
-                                0x0);
-
-        toc = (struct SMU_DRAMData_TOC *)priv->header;
-        toc->num_entries = 0;
-        toc->structure_version = 1;
-
-        PP_ASSERT_WITH_CODE(
-                        0 == fiji_populate_single_firmware_entry(smumgr,
-                                        UCODE_ID_RLC_G, &toc->entry[toc->num_entries++]),
-                        "Failed to Get Firmware Entry.\n" , return -1 );
-        PP_ASSERT_WITH_CODE(
-                        0 == fiji_populate_single_firmware_entry(smumgr,
-                                        UCODE_ID_CP_CE, &toc->entry[toc->num_entries++]),
-                        "Failed to Get Firmware Entry.\n" , return -1 );
-        PP_ASSERT_WITH_CODE(
-                        0 == fiji_populate_single_firmware_entry(smumgr,
-                                        UCODE_ID_CP_PFP, &toc->entry[toc->num_entries++]),
-                        "Failed to Get Firmware Entry.\n" , return -1 );
-        PP_ASSERT_WITH_CODE(
-                        0 == fiji_populate_single_firmware_entry(smumgr,
-                                        UCODE_ID_CP_ME, &toc->entry[toc->num_entries++]),
-                        "Failed to Get Firmware Entry.\n" , return -1 );
-        PP_ASSERT_WITH_CODE(
-                        0 == fiji_populate_single_firmware_entry(smumgr,
-                                        UCODE_ID_CP_MEC, &toc->entry[toc->num_entries++]),
-                        "Failed to Get Firmware Entry.\n" , return -1 );
-        PP_ASSERT_WITH_CODE(
-                        0 == fiji_populate_single_firmware_entry(smumgr,
-                                        UCODE_ID_CP_MEC_JT1, &toc->entry[toc->num_entries++]),
-                                        "Failed to Get Firmware Entry.\n" , return -1 );
-        PP_ASSERT_WITH_CODE(
-                        0 == fiji_populate_single_firmware_entry(smumgr,
-                                        UCODE_ID_CP_MEC_JT2, &toc->entry[toc->num_entries++]),
-                                        "Failed to Get Firmware Entry.\n" , return -1 );
-        PP_ASSERT_WITH_CODE(
-                        0 == fiji_populate_single_firmware_entry(smumgr,
-                                        UCODE_ID_SDMA0, &toc->entry[toc->num_entries++]),
-                                        "Failed to Get Firmware Entry.\n" , return -1 );
-        PP_ASSERT_WITH_CODE(
-                        0 == fiji_populate_single_firmware_entry(smumgr,
-                                        UCODE_ID_SDMA1, &toc->entry[toc->num_entries++]),
-                                        "Failed to Get Firmware Entry.\n" , return -1 );
-
-        fiji_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_HI,
-                        priv->header_buffer.mc_addr_high);
-        fiji_send_msg_to_smc_with_parameter(smumgr,PPSMC_MSG_DRV_DRAM_ADDR_LO,
-                        priv->header_buffer.mc_addr_low);
-
-        fw_to_load = UCODE_ID_RLC_G_MASK
-                        + UCODE_ID_SDMA0_MASK
-                        + UCODE_ID_SDMA1_MASK
-                        + UCODE_ID_CP_CE_MASK
-                        + UCODE_ID_CP_ME_MASK
-                        + UCODE_ID_CP_PFP_MASK
-                        + UCODE_ID_CP_MEC_MASK
-                        + UCODE_ID_CP_MEC_JT1_MASK
-                        + UCODE_ID_CP_MEC_JT2_MASK;
-
-        if (fiji_send_msg_to_smc_with_parameter(smumgr,
-                        PPSMC_MSG_LoadUcodes, fw_to_load))
-                printk(KERN_ERR "Fail to Request SMU Load uCode");
-
-        return 0;
-}
-
-
-/* Check if the FW has been loaded, SMU will not return
- * if loading has not finished.
- */
-static int fiji_check_fw_load_finish(struct pp_smumgr *smumgr,
-                uint32_t fw_type)
-{
-        struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend);
-        uint32_t mask = fiji_get_mask_for_firmware_type(fw_type);
-
-        /* Check SOFT_REGISTERS_TABLE_28.UcodeLoadStatus */
-        if (smum_wait_on_indirect_register(smumgr, mmSMC_IND_INDEX,
-                        priv->soft_regs_start +
-                        offsetof(SMU73_SoftRegisters, UcodeLoadStatus),
-                        mask, mask)) {
-                printk(KERN_ERR "check firmware loading failed\n");
-                return -EINVAL;
-        }
-        return 0;
-}
-
-
-static int fiji_reload_firmware(struct pp_smumgr *smumgr)
-{
-        return smumgr->smumgr_funcs->start_smu(smumgr);
-}
-
-static bool fiji_is_hw_virtualization_enabled(struct pp_smumgr *smumgr)
-{
-        uint32_t value;
-
-        value = cgs_read_register(smumgr->device, mmBIF_IOV_FUNC_IDENTIFIER);
-        if (value & BIF_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK) {
-                /* driver reads on SR-IOV enabled PF: 0x80000000
-                 * driver reads on SR-IOV enabled VF: 0x80000001
-                 * driver reads on SR-IOV disabled:   0x00000000
-                 */
-                return true;
-        }
-        return false;
-}
-
-static int fiji_request_smu_specific_fw_load(struct pp_smumgr *smumgr, uint32_t fw_type)
-{
-        if (fiji_is_hw_virtualization_enabled(smumgr)) {
-                uint32_t masks = fiji_get_mask_for_firmware_type(fw_type);
-                if (fiji_send_msg_to_smc_with_parameter_without_waiting(smumgr,
-                                PPSMC_MSG_LoadUcodes, masks))
-                        printk(KERN_ERR "Fail to Request SMU Load uCode");
-        }
-        /* For non-virtualization cases,
-         * SMU loads all FWs at once in fiji_request_smu_load_fw.
-         */
-        return 0;
-}
-
 static int fiji_start_smu_in_protection_mode(struct pp_smumgr *smumgr)
 {
         int result = 0;
@@ -583,7 +69,7 @@ static int fiji_start_smu_in_protection_mode(struct pp_smumgr *smumgr)
         SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
                         SMC_SYSCON_RESET_CNTL, rst_reg, 1);
 
-        result = fiji_upload_smu_firmware_image(smumgr);
+        result = smu7_upload_smu_firmware_image(smumgr);
         if (result)
                 return result;
 
@@ -622,8 +108,8 @@ static int fiji_start_smu_in_protection_mode(struct pp_smumgr *smumgr)
                         SMU_STATUS, SMU_DONE, 0);
 
         /* Check pass/failed indicator */
-        if (1 != SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-                        SMU_STATUS, SMU_PASS)) {
+        if (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
+                        SMU_STATUS, SMU_PASS) != 1) {
                 PP_ASSERT_WITH_CODE(false,
                                 "SMU Firmware start failed!", return -1);
         }
@@ -651,12 +137,12 @@ static int fiji_start_smu_in_non_protection_mode(struct pp_smumgr *smumgr)
         SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
                         SMC_SYSCON_RESET_CNTL, rst_reg, 1);
 
-        result = fiji_upload_smu_firmware_image(smumgr);
+        result = smu7_upload_smu_firmware_image(smumgr);
         if (result)
                 return result;
 
         /* Set smc instruct start point at 0x0 */
-        fiji_program_jump_on_start(smumgr);
+        smu7_program_jump_on_start(smumgr);
 
         /* Enable clock */
         SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
@@ -710,15 +196,15 @@ static int fiji_start_avfs_btc(struct pp_smumgr *smumgr)
 
         priv->avfs.AvfsBtcStatus = AVFS_BTC_STARTED;
         if (priv->avfs.AvfsBtcParam) {
-                if (!fiji_send_msg_to_smc_with_parameter(smumgr,
+                if (!smum_send_msg_to_smc_with_parameter(smumgr,
                                 PPSMC_MSG_PerformBtc, priv->avfs.AvfsBtcParam)) {
-                        if (!fiji_send_msg_to_smc(smumgr, PPSMC_MSG_EnableAvfs)) {
+                        if (!smum_send_msg_to_smc(smumgr, PPSMC_MSG_EnableAvfs)) {
                                 priv->avfs.AvfsBtcStatus = AVFS_BTC_COMPLETED_UNSAVED;
                                 result = 0;
                         } else {
                                 printk(KERN_ERR "[AVFS][fiji_start_avfs_btc] Attempt"
                                                 " to Enable AVFS Failed!");
-                                fiji_send_msg_to_smc(smumgr, PPSMC_MSG_DisableAvfs);
+                                smum_send_msg_to_smc(smumgr, PPSMC_MSG_DisableAvfs);
                                 result = -1;
                         }
                 } else {
@@ -748,7 +234,7 @@ int fiji_setup_pm_fuse_for_avfs(struct pp_smumgr *smumgr)
         charz_freq = 0x30750000; /* In 10KHz units 0x00007530 Actual value */
         inversion_voltage = 0x1A04; /* mV Q14.2 0x41A Actual value */
 
-        PP_ASSERT_WITH_CODE(0 == fiji_read_smc_sram_dword(smumgr,
+        PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(smumgr,
                         SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU73_Firmware_Header,
                                         PmFuseTable), &table_start, 0x40000),
                         "[AVFS][Fiji_SetupGfxLvlStruct] SMU could not communicate "
@@ -760,13 +246,13 @@ int fiji_setup_pm_fuse_for_avfs(struct pp_smumgr *smumgr)
         inversion_voltage_addr = table_start +
                         offsetof(struct SMU73_Discrete_PmFuses, InversionVoltage);
 
-        result = fiji_copy_bytes_to_smc(smumgr, charz_freq_addr,
+        result = smu7_copy_bytes_to_smc(smumgr, charz_freq_addr,
                         (uint8_t *)(&charz_freq), sizeof(charz_freq), 0x40000);
         PP_ASSERT_WITH_CODE(0 == result,
                         "[AVFS][fiji_setup_pm_fuse_for_avfs] charz_freq could not "
                         "be populated.", return -1;);
 
-        result = fiji_copy_bytes_to_smc(smumgr, inversion_voltage_addr,
+        result = smu7_copy_bytes_to_smc(smumgr, inversion_voltage_addr,
                         (uint8_t *)(&inversion_voltage), sizeof(inversion_voltage), 0x40000);
         PP_ASSERT_WITH_CODE(0 == result, "[AVFS][fiji_setup_pm_fuse_for_avfs] "
                         "charz_freq could not be populated.", return -1;);
@@ -781,7 +267,7 @@ int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr)
         uint32_t level_addr, vr_config_addr;
         uint32_t level_size = sizeof(avfs_graphics_level);
 
-        PP_ASSERT_WITH_CODE(0 == fiji_read_smc_sram_dword(smumgr,
+        PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(smumgr,
                         SMU7_FIRMWARE_HEADER_LOCATION +
                         offsetof(SMU73_Firmware_Header, DpmTable),
                         &table_start, 0x40000),
@@ -796,7 +282,7 @@ int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr)
         vr_config_addr = table_start +
                         offsetof(SMU73_Discrete_DpmTable, VRConfig);
 
-        PP_ASSERT_WITH_CODE(0 == fiji_copy_bytes_to_smc(smumgr, vr_config_addr,
+        PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, vr_config_addr,
                         (uint8_t *)&vr_config, sizeof(int32_t), 0x40000),
                         "[AVFS][Fiji_SetupGfxLvlStruct] Problems copying "
                         "vr_config value over to SMC",
@@ -804,7 +290,7 @@ int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr)
 
         level_addr = table_start + offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);
 
-        PP_ASSERT_WITH_CODE(0 == fiji_copy_bytes_to_smc(smumgr, level_addr,
+        PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, level_addr,
                         (uint8_t *)(&avfs_graphics_level), level_size, 0x40000),
                         "[AVFS][Fiji_SetupGfxLvlStruct] Copying of DPM table failed!",
                         return -1;);
@@ -851,13 +337,13 @@ int fiji_avfs_event_mgr(struct pp_smumgr *smumgr, bool smu_started)
                 break;
         case AVFS_BTC_COMPLETED_RESTORED: /*S3 State - Post SMU Start*/
                 priv->avfs.AvfsBtcStatus = AVFS_BTC_SMUMSG_ERROR;
-                PP_ASSERT_WITH_CODE(0 == fiji_send_msg_to_smc(smumgr,
+                PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(smumgr,
                                 0x666),
                                 "[AVFS][fiji_avfs_event_mgr] SMU did not respond "
                                 "correctly to VftTableIsValid Msg",
                                 return -1;);
                 priv->avfs.AvfsBtcStatus = AVFS_BTC_SMUMSG_ERROR;
-                PP_ASSERT_WITH_CODE(0 == fiji_send_msg_to_smc(smumgr,
+                PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(smumgr,
                                 PPSMC_MSG_EnableAvfs),
                                 "[AVFS][fiji_avfs_event_mgr] SMU did not respond "
                                 "correctly to EnableAvfs Message Msg",
@@ -910,7 +396,7 @@ static int fiji_start_smu(struct pp_smumgr *smumgr)
         struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend);
 
         /* Only start SMC if SMC RAM is not running */
-        if (!fiji_is_smc_ram_running(smumgr)) {
+        if (!smu7_is_smc_ram_running(smumgr)) {
                 fiji_avfs_event_mgr(smumgr, false);
 
                 /* Check if SMU is running in protected mode */
@@ -941,12 +427,12 @@ static int fiji_start_smu(struct pp_smumgr *smumgr)
         /* Setup SoftRegsStart here for register lookup in case
          * DummyBackEnd is used and ProcessFirmwareHeader is not executed
          */
-        fiji_read_smc_sram_dword(smumgr,
+        smu7_read_smc_sram_dword(smumgr,
                         SMU7_FIRMWARE_HEADER_LOCATION +
                         offsetof(SMU73_Firmware_Header, SoftRegisters),
-                        &(priv->soft_regs_start), 0x40000);
+                        &(priv->smu7_data.soft_regs_start), 0x40000);
 
-        result = fiji_request_smu_load_fw(smumgr);
+        result = smu7_request_smu_load_fw(smumgr);
 
         return result;
 }
@@ -975,29 +461,10 @@ static bool fiji_is_hw_avfs_present(struct pp_smumgr *smumgr)
 static int fiji_smu_init(struct pp_smumgr *smumgr)
 {
         struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend);
-        uint64_t mc_addr;
         int i;
 
-        priv->header_buffer.data_size =
-                        ((sizeof(struct SMU_DRAMData_TOC) / 4096) + 1) * 4096;
-        smu_allocate_memory(smumgr->device,
-                        priv->header_buffer.data_size,
-                        CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
-                        PAGE_SIZE,
-                        &mc_addr,
-                        &priv->header_buffer.kaddr,
-                        &priv->header_buffer.handle);
-
-        priv->header = priv->header_buffer.kaddr;
-        priv->header_buffer.mc_addr_high = smu_upper_32_bits(mc_addr);
-        priv->header_buffer.mc_addr_low = smu_lower_32_bits(mc_addr);
-
-        PP_ASSERT_WITH_CODE((NULL != priv->header),
-                        "Out of memory.",
-                        kfree(smumgr->backend);
-                        cgs_free_gpu_mem(smumgr->device,
-                        (cgs_handle_t)priv->header_buffer.handle);
-                        return -1);
+        if (smu7_init(smumgr))
+                return -EINVAL;
 
         priv->avfs.AvfsBtcStatus = AVFS_BTC_BOOT;
         if (fiji_is_hw_avfs_present(smumgr))
@@ -1012,38 +479,22 @@ static int fiji_smu_init(struct pp_smumgr *smumgr)
         else
                 priv->avfs.AvfsBtcStatus = AVFS_BTC_NOTSUPPORTED;
 
-        priv->acpi_optimization = 1;
-
         for (i = 0; i < SMU73_MAX_LEVELS_GRAPHICS; i++)
                 priv->activity_target[i] = 30;
 
         return 0;
 }
 
-static int fiji_smu_fini(struct pp_smumgr *smumgr)
-{
-        struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend);
-
-        smu_free_memory(smumgr->device, (void *)priv->header_buffer.handle);
-
-        if (smumgr->backend) {
-                kfree(smumgr->backend);
-                smumgr->backend = NULL;
-        }
-
-        cgs_rel_firmware(smumgr->device, CGS_UCODE_ID_SMU);
-        return 0;
-}
 
 static const struct pp_smumgr_func fiji_smu_funcs = {
         .smu_init = &fiji_smu_init,
-        .smu_fini = &fiji_smu_fini,
+        .smu_fini = &smu7_smu_fini,
         .start_smu = &fiji_start_smu,
-        .check_fw_load_finish = &fiji_check_fw_load_finish,
-        .request_smu_load_fw = &fiji_reload_firmware,
-        .request_smu_load_specific_fw = &fiji_request_smu_specific_fw_load,
-        .send_msg_to_smc = &fiji_send_msg_to_smc,
-        .send_msg_to_smc_with_parameter = &fiji_send_msg_to_smc_with_parameter,
+        .check_fw_load_finish = &smu7_check_fw_load_finish,
+        .request_smu_load_fw = &smu7_reload_firmware,
+        .request_smu_load_specific_fw = NULL,
+        .send_msg_to_smc = &smu7_send_msg_to_smc,
+        .send_msg_to_smc_with_parameter = &smu7_send_msg_to_smc_with_parameter,
         .download_pptable_settings = NULL,
         .upload_pptable_settings = NULL,
         .update_smc_table = fiji_update_smc_table,
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.h
index 291f7042a585..adcbdfb209be 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.h
@@ -25,35 +25,20 @@
 
 #include "smu73_discrete.h"
 #include <pp_endian.h>
+#include "smu7_smumgr.h"
+
 
-#define SMC_RAM_END             0x40000
 
 struct fiji_smu_avfs {
         enum AVFS_BTC_STATUS AvfsBtcStatus;
         uint32_t           AvfsBtcParam;
 };
 
-struct fiji_buffer_entry {
-        uint32_t data_size;
-        uint32_t mc_addr_low;
-        uint32_t mc_addr_high;
-        void *kaddr;
-        unsigned long  handle;
-};
 
 struct fiji_smumgr {
-        uint8_t        *header;
-        uint8_t        *mec_image;
+        struct smu7_smumgr                   smu7_data;
 
-        uint32_t                             soft_regs_start;
-        uint32_t                             dpm_table_start;
-        uint32_t                             mc_reg_table_start;
-        uint32_t                             fan_table_start;
-        uint32_t                             arb_table_start;
         struct fiji_smu_avfs avfs;
-        uint32_t        acpi_optimization;
-        struct fiji_buffer_entry header_buffer;
-
         struct SMU73_Discrete_DpmTable       smc_state_table;
         struct SMU73_Discrete_Ulv            ulv_setting;
         struct SMU73_Discrete_PmFuses  power_tune_table;
@@ -62,13 +47,7 @@ struct fiji_smumgr {
 
 };
 
-int fiji_smum_init(struct pp_smumgr *smumgr);
-int fiji_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smcAddress,
-                uint32_t *value, uint32_t limit);
-int fiji_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr,
-                uint32_t value, uint32_t limit);
-int fiji_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smcStartAddress,
-                const uint8_t *src,     uint32_t byteCount, uint32_t limit);
+
 
 #endif