drm/amd/pp: Delete dead code in powerplay

As not support per DPM level optimization,
so delete activity_target array.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

12 files changed, 15 insertions, 45 deletions

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
index f68dd084efae..dec8dd9d2c96 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
@@ -173,16 +173,12 @@ static uint32_t cz_get_max_sclk_level(struct pp_hwmgr *hwmgr)
 static int cz_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
 {
         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
-        uint32_t i;
         struct cgs_system_info sys_info = {0};
         int result;
 
         cz_hwmgr->gfx_ramp_step = 256*25/100;
         cz_hwmgr->gfx_ramp_delay = 1; /* by default, we delay 1us */
 
-        for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++)
-                cz_hwmgr->activity_target[i] = CZ_AT_DFLT;
-
         cz_hwmgr->mgcg_cgtt_local0 = 0x00000000;
         cz_hwmgr->mgcg_cgtt_local1 = 0x00000000;
         cz_hwmgr->clock_slow_down_freq = 25000;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h
index 508b422d6159..468c739a4299 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h
@@ -30,7 +30,6 @@
 #define CZ_NUM_NBPSTATES               4
 #define CZ_NUM_NBPMEMORYCLOCK          2
 #define MAX_DISPLAY_CLOCK_LEVEL        8
-#define CZ_AT_DFLT                     30
 #define CZ_MAX_HARDWARE_POWERLEVELS    8
 #define PPCZ_VOTINGRIGHTSCLIENTS_DFLT0   0x3FFFC102
 #define CZ_MIN_DEEP_SLEEP_SCLK         800
@@ -185,7 +184,6 @@ struct cc6_settings {
 };
 
 struct cz_hwmgr {
-        uint32_t activity_target[CZ_MAX_HARDWARE_POWERLEVELS];
         uint32_t dpm_interval;
 
         uint32_t voltage_drop_threshold;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
index a626a3eafc23..375fa10942f8 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
@@ -289,7 +289,7 @@ struct smu7_hwmgr {
         struct smu7_pcie_perf_range          pcie_lane_power_saving;
         bool                                      use_pcie_performance_levels;
         bool                                      use_pcie_power_saving_levels;
-        uint32_t                                  mclk_activity_target;
+        uint16_t                                  mclk_activity_target;
         uint16_t                                  sclk_activity_target;
         uint32_t                                  mclk_dpm0_activity_target;
         uint32_t                                  low_sclk_interrupt_threshold;
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
index 98be1277ef21..01cf32ccab5e 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
@@ -492,7 +492,7 @@ static int ci_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
         for (i = 0; i < dpm_table->sclk_table.count; i++) {
                 result = ci_populate_single_graphic_level(hwmgr,
                                 dpm_table->sclk_table.dpm_levels[i].value,
-                                (uint16_t)smu_data->activity_target[i],
+                                data->sclk_activity_target,
                                 &levels[i]);
                 if (result)
                         return result;
@@ -1231,7 +1231,7 @@ static int ci_populate_single_memory_level(
         memory_level->VoltageDownH = 0;
 
         /* Indicates maximum activity level for this performance level.*/
-        memory_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
+        memory_level->ActivityLevel = data->mclk_activity_target;
         memory_level->StutterEnable = 0;
         memory_level->StrobeEnable = 0;
         memory_level->EdcReadEnable = 0;
@@ -1515,7 +1515,7 @@ static int ci_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
         table->MemoryACPILevel.DownH = 100;
         table->MemoryACPILevel.VoltageDownH = 0;
         /* Indicates maximum activity level for this performance level.*/
-        table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
+        table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US(data->mclk_activity_target);
 
         table->MemoryACPILevel.StutterEnable = 0;
         table->MemoryACPILevel.StrobeEnable = 0;
@@ -2802,7 +2802,6 @@ static int ci_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
 
 static int ci_smu_init(struct pp_hwmgr *hwmgr)
 {
-        int i;
         struct ci_smumgr *ci_priv = NULL;
 
         ci_priv = kzalloc(sizeof(struct ci_smumgr), GFP_KERNEL);
@@ -2810,9 +2809,6 @@ static int ci_smu_init(struct pp_hwmgr *hwmgr)
         if (ci_priv == NULL)
                 return -ENOMEM;
 
-        for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++)
-                ci_priv->activity_target[i] = 30;
-
         hwmgr->smu_backend = ci_priv;
 
         return 0;
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.h
index 8189cfa17c46..a8282705c569 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.h
@@ -70,8 +70,6 @@ struct ci_smumgr {
         const struct ci_pt_defaults  *power_tune_defaults;
         SMU7_Discrete_MCRegisters      mc_regs;
         struct ci_mc_reg_table mc_reg_table;
-        uint32_t        activity_target[SMU7_MAX_LEVELS_GRAPHICS];
-
 };
 
 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
index 73c6020bab76..e54038075886 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
@@ -368,7 +368,6 @@ static bool fiji_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
 
 static int fiji_smu_init(struct pp_hwmgr *hwmgr)
 {
-        int i;
         struct fiji_smumgr *fiji_priv = NULL;
 
         fiji_priv = kzalloc(sizeof(struct fiji_smumgr), GFP_KERNEL);
@@ -381,9 +380,6 @@ static int fiji_smu_init(struct pp_hwmgr *hwmgr)
         if (smu7_init(hwmgr))
                 return -EINVAL;
 
-        for (i = 0; i < SMU73_MAX_LEVELS_GRAPHICS; i++)
-                fiji_priv->activity_target[i] = 30;
-
         return 0;
 }
 
@@ -1063,7 +1059,7 @@ static int fiji_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
         for (i = 0; i < dpm_table->sclk_table.count; i++) {
                 result = fiji_populate_single_graphic_level(hwmgr,
                                 dpm_table->sclk_table.dpm_levels[i].value,
-                                (uint16_t)smu_data->activity_target[i],
+                                data->sclk_activity_target,
                                 &levels[i]);
                 if (result)
                         return result;
@@ -1229,7 +1225,7 @@ static int fiji_populate_single_memory_level(struct pp_hwmgr *hwmgr,
         mem_level->UpHyst = 0;
         mem_level->DownHyst = 100;
         mem_level->VoltageDownHyst = 0;
-        mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
+        mem_level->ActivityLevel = data->mclk_activity_target;
         mem_level->StutterEnable = false;
 
         mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
@@ -1447,7 +1443,7 @@ static int fiji_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
         table->MemoryACPILevel.DownHyst = 100;
         table->MemoryACPILevel.VoltageDownHyst = 0;
         table->MemoryACPILevel.ActivityLevel =
-                        PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
+                        PP_HOST_TO_SMC_US(data->mclk_activity_target);
 
         table->MemoryACPILevel.StutterEnable = false;
         CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.h
index 279647772578..6d3746268ccf 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.h
@@ -43,8 +43,6 @@ struct fiji_smumgr {
         struct SMU73_Discrete_Ulv            ulv_setting;
         struct SMU73_Discrete_PmFuses  power_tune_table;
         const struct fiji_pt_defaults  *power_tune_defaults;
-        uint32_t        activity_target[SMU73_MAX_LEVELS_GRAPHICS];
-
 };
 
 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
index 6400065a8710..5cf588d6660c 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
@@ -262,7 +262,6 @@ static int iceland_start_smu(struct pp_hwmgr *hwmgr)
 
 static int iceland_smu_init(struct pp_hwmgr *hwmgr)
 {
-        int i;
         struct iceland_smumgr *iceland_priv = NULL;
 
         iceland_priv = kzalloc(sizeof(struct iceland_smumgr), GFP_KERNEL);
@@ -275,9 +274,6 @@ static int iceland_smu_init(struct pp_hwmgr *hwmgr)
         if (smu7_init(hwmgr))
                 return -EINVAL;
 
-        for (i = 0; i < SMU71_MAX_LEVELS_GRAPHICS; i++)
-                iceland_priv->activity_target[i] = 30;
-
         return 0;
 }
 
@@ -989,7 +985,7 @@ static int iceland_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
         for (i = 0; i < dpm_table->sclk_table.count; i++) {
                 result = iceland_populate_single_graphic_level(hwmgr,
                                         dpm_table->sclk_table.dpm_levels[i].value,
-                                        (uint16_t)smu_data->activity_target[i],
+                                        data->sclk_activity_target,
                                         &(smu_data->smc_state_table.GraphicsLevel[i]));
                 if (result != 0)
                         return result;
@@ -1280,7 +1276,7 @@ static int iceland_populate_single_memory_level(
         memory_level->VoltageDownHyst = 0;
 
         /* Indicates maximum activity level for this performance level.*/
-        memory_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
+        memory_level->ActivityLevel = data->mclk_activity_target;
         memory_level->StutterEnable = 0;
         memory_level->StrobeEnable = 0;
         memory_level->EdcReadEnable = 0;
@@ -1561,7 +1557,7 @@ static int iceland_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
         table->MemoryACPILevel.DownHyst = 100;
         table->MemoryACPILevel.VoltageDownHyst = 0;
         /* Indicates maximum activity level for this performance level.*/
-        table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
+        table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US(data->mclk_activity_target);
 
         table->MemoryACPILevel.StutterEnable = 0;
         table->MemoryACPILevel.StrobeEnable = 0;
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.h
index 802472530d34..f32c506779c9 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.h
@@ -65,7 +65,6 @@ struct iceland_smumgr {
         const struct iceland_pt_defaults  *power_tune_defaults;
         SMU71_Discrete_MCRegisters      mc_regs;
         struct iceland_mc_reg_table mc_reg_table;
-        uint32_t        activity_target[SMU71_MAX_LEVELS_GRAPHICS];
 };
 
 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
index 356f60ed28f4..f9856e1c89ff 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
@@ -1133,7 +1133,7 @@ static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
         mem_level->UpHyst = 0;
         mem_level->DownHyst = 100;
         mem_level->VoltageDownHyst = 0;
-        mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
+        mem_level->ActivityLevel = data->mclk_activity_target;
         mem_level->StutterEnable = false;
         mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
 
@@ -1314,7 +1314,7 @@ static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
         table->MemoryACPILevel.DownHyst = 100;
         table->MemoryACPILevel.VoltageDownHyst = 0;
         table->MemoryACPILevel.ActivityLevel =
-                        PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
+                        PP_HOST_TO_SMC_US(data->mclk_activity_target);
 
         CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
         CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
index 4b3fd04780d5..ce6e740074af 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
@@ -222,7 +222,6 @@ static int tonga_start_smu(struct pp_hwmgr *hwmgr)
 static int tonga_smu_init(struct pp_hwmgr *hwmgr)
 {
         struct tonga_smumgr *tonga_priv = NULL;
-        int  i;
 
         tonga_priv = kzalloc(sizeof(struct tonga_smumgr), GFP_KERNEL);
         if (tonga_priv == NULL)
@@ -233,9 +232,6 @@ static int tonga_smu_init(struct pp_hwmgr *hwmgr)
         if (smu7_init(hwmgr))
                 return -EINVAL;
 
-        for (i = 0; i < SMU72_MAX_LEVELS_GRAPHICS; i++)
-                tonga_priv->activity_target[i] = 30;
-
         return 0;
 }
 
@@ -708,7 +704,7 @@ static int tonga_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
         for (i = 0; i < dpm_table->sclk_table.count; i++) {
                 result = tonga_populate_single_graphic_level(hwmgr,
                                         dpm_table->sclk_table.dpm_levels[i].value,
-                                        (uint16_t)smu_data->activity_target[i],
+                                        data->sclk_activity_target,
                                         &(smu_data->smc_state_table.GraphicsLevel[i]));
                 if (result != 0)
                         return result;
@@ -1003,7 +999,7 @@ static int tonga_populate_single_memory_level(
         memory_level->VoltageDownHyst = 0;
 
         /* Indicates maximum activity level for this performance level.*/
-        memory_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
+        memory_level->ActivityLevel = data->mclk_activity_target;
         memory_level->StutterEnable = 0;
         memory_level->StrobeEnable = 0;
         memory_level->EdcReadEnable = 0;
@@ -1293,7 +1289,7 @@ static int tonga_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
         table->MemoryACPILevel.VoltageDownHyst = 0;
         /* Indicates maximum activity level for this performance level.*/
         table->MemoryACPILevel.ActivityLevel =
-                        PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
+                        PP_HOST_TO_SMC_US(data->mclk_activity_target);
 
         table->MemoryACPILevel.StutterEnable = 0;
         table->MemoryACPILevel.StrobeEnable = 0;
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.h
index 5d70a00348e2..d664fedd3d85 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.h
@@ -69,9 +69,6 @@ struct tonga_smumgr {
         const struct tonga_pt_defaults  *power_tune_defaults;
         SMU72_Discrete_MCRegisters      mc_regs;
         struct tonga_mc_reg_table mc_reg_table;
-
-        uint32_t        activity_target[SMU72_MAX_LEVELS_GRAPHICS];
-
 };
 
 #endif