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authorAlex Deucher <alexander.deucher@amd.com>2015-04-16 15:34:40 -0400
committerAlex Deucher <alexander.deucher@amd.com>2015-06-03 21:03:08 -0400
commit3b1e08cb29565d30d3bb87b26fefb126c1e00d89 (patch)
tree6d204a533cf233ebcbcedbf9e32ea314f7c25730 /drivers/gpu
parent7aa27c37739c1bea219b744b351c3a74f6eb6674 (diff)
drm/amdgpu: add UVD 6.0 register headers
These are register headers for the UVD (Universal Video Decoder) block on the GPU. Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h115
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_enum.h1081
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h1034
3 files changed, 2230 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h
new file mode 100644
index 000000000000..b2d4aaf045bc
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h
@@ -0,0 +1,115 @@
1/*
2 * UVD_6_0 Register documentation
3 *
4 * Copyright (C) 2014 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#ifndef UVD_6_0_D_H
25#define UVD_6_0_D_H
26
27#define mmUVD_SEMA_ADDR_LOW 0x3bc0
28#define mmUVD_SEMA_ADDR_HIGH 0x3bc1
29#define mmUVD_SEMA_CMD 0x3bc2
30#define mmUVD_GPCOM_VCPU_CMD 0x3bc3
31#define mmUVD_GPCOM_VCPU_DATA0 0x3bc4
32#define mmUVD_GPCOM_VCPU_DATA1 0x3bc5
33#define mmUVD_ENGINE_CNTL 0x3bc6
34#define mmUVD_UDEC_ADDR_CONFIG 0x3bd3
35#define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4
36#define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5
37#define mmUVD_POWER_STATUS_U 0x3bfd
38#define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW 0x3c69
39#define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH 0x3c68
40#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x3c67
41#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH 0x3c66
42#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x3c5f
43#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x3c5e
44#define mmUVD_SEMA_CNTL 0x3d00
45#define mmUVD_LMI_EXT40_ADDR 0x3d26
46#define mmUVD_CTX_INDEX 0x3d28
47#define mmUVD_CTX_DATA 0x3d29
48#define mmUVD_CGC_GATE 0x3d2a
49#define mmUVD_CGC_STATUS 0x3d2b
50#define mmUVD_CGC_CTRL 0x3d2c
51#define mmUVD_CGC_UDEC_STATUS 0x3d2d
52#define mmUVD_LMI_CTRL2 0x3d3d
53#define mmUVD_MASTINT_EN 0x3d40
54#define mmUVD_LMI_ADDR_EXT 0x3d65
55#define mmUVD_LMI_CTRL 0x3d66
56#define mmUVD_LMI_STATUS 0x3d67
57#define mmUVD_LMI_SWAP_CNTL 0x3d6d
58#define mmUVD_MP_SWAP_CNTL 0x3d6f
59#define mmUVD_MPC_CNTL 0x3d77
60#define mmUVD_MPC_SET_MUXA0 0x3d79
61#define mmUVD_MPC_SET_MUXA1 0x3d7a
62#define mmUVD_MPC_SET_MUXB0 0x3d7b
63#define mmUVD_MPC_SET_MUXB1 0x3d7c
64#define mmUVD_MPC_SET_MUX 0x3d7d
65#define mmUVD_MPC_SET_ALU 0x3d7e
66#define mmUVD_VCPU_CACHE_OFFSET0 0x3d82
67#define mmUVD_VCPU_CACHE_SIZE0 0x3d83
68#define mmUVD_VCPU_CACHE_OFFSET1 0x3d84
69#define mmUVD_VCPU_CACHE_SIZE1 0x3d85
70#define mmUVD_VCPU_CACHE_OFFSET2 0x3d86
71#define mmUVD_VCPU_CACHE_SIZE2 0x3d87
72#define mmUVD_VCPU_CNTL 0x3d98
73#define mmUVD_SOFT_RESET 0x3da0
74#define mmUVD_LMI_RBC_IB_VMID 0x3da1
75#define mmUVD_RBC_IB_SIZE 0x3da2
76#define mmUVD_LMI_RBC_RB_VMID 0x3da3
77#define mmUVD_RBC_RB_RPTR 0x3da4
78#define mmUVD_RBC_RB_WPTR 0x3da5
79#define mmUVD_RBC_RB_WPTR_CNTL 0x3da6
80#define mmUVD_RBC_RB_CNTL 0x3da9
81#define mmUVD_RBC_RB_RPTR_ADDR 0x3daa
82#define mmUVD_STATUS 0x3daf
83#define mmUVD_SEMA_TIMEOUT_STATUS 0x3db0
84#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0x3db1
85#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x3db2
86#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x3db3
87#define mmUVD_CONTEXT_ID 0x3dbd
88#define mmUVD_RBC_IB_SIZE_UPDATE 0x3df1
89#define mmUVD_SUVD_CGC_GATE 0x3be4
90#define mmUVD_SUVD_CGC_STATUS 0x3be5
91#define mmUVD_SUVD_CGC_CTRL 0x3be6
92#define ixUVD_LMI_VMID_INTERNAL 0x99
93#define ixUVD_LMI_VMID_INTERNAL2 0x9a
94#define ixUVD_LMI_CACHE_CTRL 0x9b
95#define ixUVD_LMI_SWAP_CNTL2 0xaa
96#define ixUVD_LMI_ADDR_EXT2 0xab
97#define ixUVD_CGC_MEM_CTRL 0xc0
98#define ixUVD_CGC_CTRL2 0xc1
99#define ixUVD_LMI_VMID_INTERNAL3 0x162
100#define mmUVD_PGFSM_CONFIG 0x38c0
101#define mmUVD_PGFSM_READ_TILE1 0x38c2
102#define mmUVD_PGFSM_READ_TILE2 0x38c3
103#define mmUVD_POWER_STATUS 0x38c4
104#define mmUVD_PGFSM_READ_TILE3 0x38c5
105#define mmUVD_PGFSM_READ_TILE4 0x38c6
106#define mmUVD_PGFSM_READ_TILE5 0x38c8
107#define mmUVD_PGFSM_READ_TILE6 0x38ee
108#define mmUVD_PGFSM_READ_TILE7 0x38ef
109#define mmUVD_MIF_CURR_ADDR_CONFIG 0x3992
110#define mmUVD_MIF_REF_ADDR_CONFIG 0x3993
111#define mmUVD_MIF_RECON1_ADDR_CONFIG 0x39c5
112#define ixUVD_MIF_SCLR_ADDR_CONFIG 0x4
113#define mmUVD_JPEG_ADDR_CONFIG 0x3a1f
114
115#endif /* UVD_6_0_D_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_enum.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_enum.h
new file mode 100644
index 000000000000..ecf47ba55c2d
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_enum.h
@@ -0,0 +1,1081 @@
1/*
2 * UVD_6_0 Register documentation
3 *
4 * Copyright (C) 2014 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#ifndef UVD_6_0_ENUM_H
25#define UVD_6_0_ENUM_H
26
27typedef enum UVDFirmwareCommand {
28 UVDFC_FENCE = 0x0,
29 UVDFC_TRAP = 0x1,
30 UVDFC_DECODED_ADDR = 0x2,
31 UVDFC_MBLOCK_ADDR = 0x3,
32 UVDFC_ITBUF_ADDR = 0x4,
33 UVDFC_DISPLAY_ADDR = 0x5,
34 UVDFC_EOD = 0x6,
35 UVDFC_DISPLAY_PITCH = 0x7,
36 UVDFC_DISPLAY_TILING = 0x8,
37 UVDFC_BITSTREAM_ADDR = 0x9,
38 UVDFC_BITSTREAM_SIZE = 0xa,
39} UVDFirmwareCommand;
40typedef enum DebugBlockId {
41 DBG_BLOCK_ID_RESERVED = 0x0,
42 DBG_BLOCK_ID_DBG = 0x1,
43 DBG_BLOCK_ID_VMC = 0x2,
44 DBG_BLOCK_ID_PDMA = 0x3,
45 DBG_BLOCK_ID_CG = 0x4,
46 DBG_BLOCK_ID_SRBM = 0x5,
47 DBG_BLOCK_ID_GRBM = 0x6,
48 DBG_BLOCK_ID_RLC = 0x7,
49 DBG_BLOCK_ID_CSC = 0x8,
50 DBG_BLOCK_ID_SEM = 0x9,
51 DBG_BLOCK_ID_IH = 0xa,
52 DBG_BLOCK_ID_SC = 0xb,
53 DBG_BLOCK_ID_SQ = 0xc,
54 DBG_BLOCK_ID_UVDU = 0xd,
55 DBG_BLOCK_ID_SQA = 0xe,
56 DBG_BLOCK_ID_SDMA0 = 0xf,
57 DBG_BLOCK_ID_SDMA1 = 0x10,
58 DBG_BLOCK_ID_SPIM = 0x11,
59 DBG_BLOCK_ID_GDS = 0x12,
60 DBG_BLOCK_ID_VC0 = 0x13,
61 DBG_BLOCK_ID_VC1 = 0x14,
62 DBG_BLOCK_ID_PA0 = 0x15,
63 DBG_BLOCK_ID_PA1 = 0x16,
64 DBG_BLOCK_ID_CP0 = 0x17,
65 DBG_BLOCK_ID_CP1 = 0x18,
66 DBG_BLOCK_ID_CP2 = 0x19,
67 DBG_BLOCK_ID_XBR = 0x1a,
68 DBG_BLOCK_ID_UVDM = 0x1b,
69 DBG_BLOCK_ID_VGT0 = 0x1c,
70 DBG_BLOCK_ID_VGT1 = 0x1d,
71 DBG_BLOCK_ID_IA = 0x1e,
72 DBG_BLOCK_ID_SXM0 = 0x1f,
73 DBG_BLOCK_ID_SXM1 = 0x20,
74 DBG_BLOCK_ID_SCT0 = 0x21,
75 DBG_BLOCK_ID_SCT1 = 0x22,
76 DBG_BLOCK_ID_SPM0 = 0x23,
77 DBG_BLOCK_ID_SPM1 = 0x24,
78 DBG_BLOCK_ID_UNUSED0 = 0x25,
79 DBG_BLOCK_ID_UNUSED1 = 0x26,
80 DBG_BLOCK_ID_TCAA = 0x27,
81 DBG_BLOCK_ID_TCAB = 0x28,
82 DBG_BLOCK_ID_TCCA = 0x29,
83 DBG_BLOCK_ID_TCCB = 0x2a,
84 DBG_BLOCK_ID_MCC0 = 0x2b,
85 DBG_BLOCK_ID_MCC1 = 0x2c,
86 DBG_BLOCK_ID_MCC2 = 0x2d,
87 DBG_BLOCK_ID_MCC3 = 0x2e,
88 DBG_BLOCK_ID_SXS0 = 0x2f,
89 DBG_BLOCK_ID_SXS1 = 0x30,
90 DBG_BLOCK_ID_SXS2 = 0x31,
91 DBG_BLOCK_ID_SXS3 = 0x32,
92 DBG_BLOCK_ID_SXS4 = 0x33,
93 DBG_BLOCK_ID_SXS5 = 0x34,
94 DBG_BLOCK_ID_SXS6 = 0x35,
95 DBG_BLOCK_ID_SXS7 = 0x36,
96 DBG_BLOCK_ID_SXS8 = 0x37,
97 DBG_BLOCK_ID_SXS9 = 0x38,
98 DBG_BLOCK_ID_BCI0 = 0x39,
99 DBG_BLOCK_ID_BCI1 = 0x3a,
100 DBG_BLOCK_ID_BCI2 = 0x3b,
101 DBG_BLOCK_ID_BCI3 = 0x3c,
102 DBG_BLOCK_ID_MCB = 0x3d,
103 DBG_BLOCK_ID_UNUSED6 = 0x3e,
104 DBG_BLOCK_ID_SQA00 = 0x3f,
105 DBG_BLOCK_ID_SQA01 = 0x40,
106 DBG_BLOCK_ID_SQA02 = 0x41,
107 DBG_BLOCK_ID_SQA10 = 0x42,
108 DBG_BLOCK_ID_SQA11 = 0x43,
109 DBG_BLOCK_ID_SQA12 = 0x44,
110 DBG_BLOCK_ID_UNUSED7 = 0x45,
111 DBG_BLOCK_ID_UNUSED8 = 0x46,
112 DBG_BLOCK_ID_SQB00 = 0x47,
113 DBG_BLOCK_ID_SQB01 = 0x48,
114 DBG_BLOCK_ID_SQB10 = 0x49,
115 DBG_BLOCK_ID_SQB11 = 0x4a,
116 DBG_BLOCK_ID_SQ00 = 0x4b,
117 DBG_BLOCK_ID_SQ01 = 0x4c,
118 DBG_BLOCK_ID_SQ10 = 0x4d,
119 DBG_BLOCK_ID_SQ11 = 0x4e,
120 DBG_BLOCK_ID_CB00 = 0x4f,
121 DBG_BLOCK_ID_CB01 = 0x50,
122 DBG_BLOCK_ID_CB02 = 0x51,
123 DBG_BLOCK_ID_CB03 = 0x52,
124 DBG_BLOCK_ID_CB04 = 0x53,
125 DBG_BLOCK_ID_UNUSED9 = 0x54,
126 DBG_BLOCK_ID_UNUSED10 = 0x55,
127 DBG_BLOCK_ID_UNUSED11 = 0x56,
128 DBG_BLOCK_ID_CB10 = 0x57,
129 DBG_BLOCK_ID_CB11 = 0x58,
130 DBG_BLOCK_ID_CB12 = 0x59,
131 DBG_BLOCK_ID_CB13 = 0x5a,
132 DBG_BLOCK_ID_CB14 = 0x5b,
133 DBG_BLOCK_ID_UNUSED12 = 0x5c,
134 DBG_BLOCK_ID_UNUSED13 = 0x5d,
135 DBG_BLOCK_ID_UNUSED14 = 0x5e,
136 DBG_BLOCK_ID_TCP0 = 0x5f,
137 DBG_BLOCK_ID_TCP1 = 0x60,
138 DBG_BLOCK_ID_TCP2 = 0x61,
139 DBG_BLOCK_ID_TCP3 = 0x62,
140 DBG_BLOCK_ID_TCP4 = 0x63,
141 DBG_BLOCK_ID_TCP5 = 0x64,
142 DBG_BLOCK_ID_TCP6 = 0x65,
143 DBG_BLOCK_ID_TCP7 = 0x66,
144 DBG_BLOCK_ID_TCP8 = 0x67,
145 DBG_BLOCK_ID_TCP9 = 0x68,
146 DBG_BLOCK_ID_TCP10 = 0x69,
147 DBG_BLOCK_ID_TCP11 = 0x6a,
148 DBG_BLOCK_ID_TCP12 = 0x6b,
149 DBG_BLOCK_ID_TCP13 = 0x6c,
150 DBG_BLOCK_ID_TCP14 = 0x6d,
151 DBG_BLOCK_ID_TCP15 = 0x6e,
152 DBG_BLOCK_ID_TCP16 = 0x6f,
153 DBG_BLOCK_ID_TCP17 = 0x70,
154 DBG_BLOCK_ID_TCP18 = 0x71,
155 DBG_BLOCK_ID_TCP19 = 0x72,
156 DBG_BLOCK_ID_TCP20 = 0x73,
157 DBG_BLOCK_ID_TCP21 = 0x74,
158 DBG_BLOCK_ID_TCP22 = 0x75,
159 DBG_BLOCK_ID_TCP23 = 0x76,
160 DBG_BLOCK_ID_TCP_RESERVED0 = 0x77,
161 DBG_BLOCK_ID_TCP_RESERVED1 = 0x78,
162 DBG_BLOCK_ID_TCP_RESERVED2 = 0x79,
163 DBG_BLOCK_ID_TCP_RESERVED3 = 0x7a,
164 DBG_BLOCK_ID_TCP_RESERVED4 = 0x7b,
165 DBG_BLOCK_ID_TCP_RESERVED5 = 0x7c,
166 DBG_BLOCK_ID_TCP_RESERVED6 = 0x7d,
167 DBG_BLOCK_ID_TCP_RESERVED7 = 0x7e,
168 DBG_BLOCK_ID_DB00 = 0x7f,
169 DBG_BLOCK_ID_DB01 = 0x80,
170 DBG_BLOCK_ID_DB02 = 0x81,
171 DBG_BLOCK_ID_DB03 = 0x82,
172 DBG_BLOCK_ID_DB04 = 0x83,
173 DBG_BLOCK_ID_UNUSED15 = 0x84,
174 DBG_BLOCK_ID_UNUSED16 = 0x85,
175 DBG_BLOCK_ID_UNUSED17 = 0x86,
176 DBG_BLOCK_ID_DB10 = 0x87,
177 DBG_BLOCK_ID_DB11 = 0x88,
178 DBG_BLOCK_ID_DB12 = 0x89,
179 DBG_BLOCK_ID_DB13 = 0x8a,
180 DBG_BLOCK_ID_DB14 = 0x8b,
181 DBG_BLOCK_ID_UNUSED18 = 0x8c,
182 DBG_BLOCK_ID_UNUSED19 = 0x8d,
183 DBG_BLOCK_ID_UNUSED20 = 0x8e,
184 DBG_BLOCK_ID_TCC0 = 0x8f,
185 DBG_BLOCK_ID_TCC1 = 0x90,
186 DBG_BLOCK_ID_TCC2 = 0x91,
187 DBG_BLOCK_ID_TCC3 = 0x92,
188 DBG_BLOCK_ID_TCC4 = 0x93,
189 DBG_BLOCK_ID_TCC5 = 0x94,
190 DBG_BLOCK_ID_TCC6 = 0x95,
191 DBG_BLOCK_ID_TCC7 = 0x96,
192 DBG_BLOCK_ID_SPS00 = 0x97,
193 DBG_BLOCK_ID_SPS01 = 0x98,
194 DBG_BLOCK_ID_SPS02 = 0x99,
195 DBG_BLOCK_ID_SPS10 = 0x9a,
196 DBG_BLOCK_ID_SPS11 = 0x9b,
197 DBG_BLOCK_ID_SPS12 = 0x9c,
198 DBG_BLOCK_ID_UNUSED21 = 0x9d,
199 DBG_BLOCK_ID_UNUSED22 = 0x9e,
200 DBG_BLOCK_ID_TA00 = 0x9f,
201 DBG_BLOCK_ID_TA01 = 0xa0,
202 DBG_BLOCK_ID_TA02 = 0xa1,
203 DBG_BLOCK_ID_TA03 = 0xa2,
204 DBG_BLOCK_ID_TA04 = 0xa3,
205 DBG_BLOCK_ID_TA05 = 0xa4,
206 DBG_BLOCK_ID_TA06 = 0xa5,
207 DBG_BLOCK_ID_TA07 = 0xa6,
208 DBG_BLOCK_ID_TA08 = 0xa7,
209 DBG_BLOCK_ID_TA09 = 0xa8,
210 DBG_BLOCK_ID_TA0A = 0xa9,
211 DBG_BLOCK_ID_TA0B = 0xaa,
212 DBG_BLOCK_ID_UNUSED23 = 0xab,
213 DBG_BLOCK_ID_UNUSED24 = 0xac,
214 DBG_BLOCK_ID_UNUSED25 = 0xad,
215 DBG_BLOCK_ID_UNUSED26 = 0xae,
216 DBG_BLOCK_ID_TA10 = 0xaf,
217 DBG_BLOCK_ID_TA11 = 0xb0,
218 DBG_BLOCK_ID_TA12 = 0xb1,
219 DBG_BLOCK_ID_TA13 = 0xb2,
220 DBG_BLOCK_ID_TA14 = 0xb3,
221 DBG_BLOCK_ID_TA15 = 0xb4,
222 DBG_BLOCK_ID_TA16 = 0xb5,
223 DBG_BLOCK_ID_TA17 = 0xb6,
224 DBG_BLOCK_ID_TA18 = 0xb7,
225 DBG_BLOCK_ID_TA19 = 0xb8,
226 DBG_BLOCK_ID_TA1A = 0xb9,
227 DBG_BLOCK_ID_TA1B = 0xba,
228 DBG_BLOCK_ID_UNUSED27 = 0xbb,
229 DBG_BLOCK_ID_UNUSED28 = 0xbc,
230 DBG_BLOCK_ID_UNUSED29 = 0xbd,
231 DBG_BLOCK_ID_UNUSED30 = 0xbe,
232 DBG_BLOCK_ID_TD00 = 0xbf,
233 DBG_BLOCK_ID_TD01 = 0xc0,
234 DBG_BLOCK_ID_TD02 = 0xc1,
235 DBG_BLOCK_ID_TD03 = 0xc2,
236 DBG_BLOCK_ID_TD04 = 0xc3,
237 DBG_BLOCK_ID_TD05 = 0xc4,
238 DBG_BLOCK_ID_TD06 = 0xc5,
239 DBG_BLOCK_ID_TD07 = 0xc6,
240 DBG_BLOCK_ID_TD08 = 0xc7,
241 DBG_BLOCK_ID_TD09 = 0xc8,
242 DBG_BLOCK_ID_TD0A = 0xc9,
243 DBG_BLOCK_ID_TD0B = 0xca,
244 DBG_BLOCK_ID_UNUSED31 = 0xcb,
245 DBG_BLOCK_ID_UNUSED32 = 0xcc,
246 DBG_BLOCK_ID_UNUSED33 = 0xcd,
247 DBG_BLOCK_ID_UNUSED34 = 0xce,
248 DBG_BLOCK_ID_TD10 = 0xcf,
249 DBG_BLOCK_ID_TD11 = 0xd0,
250 DBG_BLOCK_ID_TD12 = 0xd1,
251 DBG_BLOCK_ID_TD13 = 0xd2,
252 DBG_BLOCK_ID_TD14 = 0xd3,
253 DBG_BLOCK_ID_TD15 = 0xd4,
254 DBG_BLOCK_ID_TD16 = 0xd5,
255 DBG_BLOCK_ID_TD17 = 0xd6,
256 DBG_BLOCK_ID_TD18 = 0xd7,
257 DBG_BLOCK_ID_TD19 = 0xd8,
258 DBG_BLOCK_ID_TD1A = 0xd9,
259 DBG_BLOCK_ID_TD1B = 0xda,
260 DBG_BLOCK_ID_UNUSED35 = 0xdb,
261 DBG_BLOCK_ID_UNUSED36 = 0xdc,
262 DBG_BLOCK_ID_UNUSED37 = 0xdd,
263 DBG_BLOCK_ID_UNUSED38 = 0xde,
264 DBG_BLOCK_ID_LDS00 = 0xdf,
265 DBG_BLOCK_ID_LDS01 = 0xe0,
266 DBG_BLOCK_ID_LDS02 = 0xe1,
267 DBG_BLOCK_ID_LDS03 = 0xe2,
268 DBG_BLOCK_ID_LDS04 = 0xe3,
269 DBG_BLOCK_ID_LDS05 = 0xe4,
270 DBG_BLOCK_ID_LDS06 = 0xe5,
271 DBG_BLOCK_ID_LDS07 = 0xe6,
272 DBG_BLOCK_ID_LDS08 = 0xe7,
273 DBG_BLOCK_ID_LDS09 = 0xe8,
274 DBG_BLOCK_ID_LDS0A = 0xe9,
275 DBG_BLOCK_ID_LDS0B = 0xea,
276 DBG_BLOCK_ID_UNUSED39 = 0xeb,
277 DBG_BLOCK_ID_UNUSED40 = 0xec,
278 DBG_BLOCK_ID_UNUSED41 = 0xed,
279 DBG_BLOCK_ID_UNUSED42 = 0xee,
280 DBG_BLOCK_ID_LDS10 = 0xef,
281 DBG_BLOCK_ID_LDS11 = 0xf0,
282 DBG_BLOCK_ID_LDS12 = 0xf1,
283 DBG_BLOCK_ID_LDS13 = 0xf2,
284 DBG_BLOCK_ID_LDS14 = 0xf3,
285 DBG_BLOCK_ID_LDS15 = 0xf4,
286 DBG_BLOCK_ID_LDS16 = 0xf5,
287 DBG_BLOCK_ID_LDS17 = 0xf6,
288 DBG_BLOCK_ID_LDS18 = 0xf7,
289 DBG_BLOCK_ID_LDS19 = 0xf8,
290 DBG_BLOCK_ID_LDS1A = 0xf9,
291 DBG_BLOCK_ID_LDS1B = 0xfa,
292 DBG_BLOCK_ID_UNUSED43 = 0xfb,
293 DBG_BLOCK_ID_UNUSED44 = 0xfc,
294 DBG_BLOCK_ID_UNUSED45 = 0xfd,
295 DBG_BLOCK_ID_UNUSED46 = 0xfe,
296} DebugBlockId;
297typedef enum DebugBlockId_BY2 {
298 DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
299 DBG_BLOCK_ID_VMC_BY2 = 0x1,
300 DBG_BLOCK_ID_UNUSED0_BY2 = 0x2,
301 DBG_BLOCK_ID_GRBM_BY2 = 0x3,
302 DBG_BLOCK_ID_CSC_BY2 = 0x4,
303 DBG_BLOCK_ID_IH_BY2 = 0x5,
304 DBG_BLOCK_ID_SQ_BY2 = 0x6,
305 DBG_BLOCK_ID_UVD_BY2 = 0x7,
306 DBG_BLOCK_ID_SDMA0_BY2 = 0x8,
307 DBG_BLOCK_ID_SPIM_BY2 = 0x9,
308 DBG_BLOCK_ID_VC0_BY2 = 0xa,
309 DBG_BLOCK_ID_PA_BY2 = 0xb,
310 DBG_BLOCK_ID_CP0_BY2 = 0xc,
311 DBG_BLOCK_ID_CP2_BY2 = 0xd,
312 DBG_BLOCK_ID_PC0_BY2 = 0xe,
313 DBG_BLOCK_ID_BCI0_BY2 = 0xf,
314 DBG_BLOCK_ID_SXM0_BY2 = 0x10,
315 DBG_BLOCK_ID_SCT0_BY2 = 0x11,
316 DBG_BLOCK_ID_SPM0_BY2 = 0x12,
317 DBG_BLOCK_ID_BCI2_BY2 = 0x13,
318 DBG_BLOCK_ID_TCA_BY2 = 0x14,
319 DBG_BLOCK_ID_TCCA_BY2 = 0x15,
320 DBG_BLOCK_ID_MCC_BY2 = 0x16,
321 DBG_BLOCK_ID_MCC2_BY2 = 0x17,
322 DBG_BLOCK_ID_MCD_BY2 = 0x18,
323 DBG_BLOCK_ID_MCD2_BY2 = 0x19,
324 DBG_BLOCK_ID_MCD4_BY2 = 0x1a,
325 DBG_BLOCK_ID_MCB_BY2 = 0x1b,
326 DBG_BLOCK_ID_SQA_BY2 = 0x1c,
327 DBG_BLOCK_ID_SQA02_BY2 = 0x1d,
328 DBG_BLOCK_ID_SQA11_BY2 = 0x1e,
329 DBG_BLOCK_ID_UNUSED8_BY2 = 0x1f,
330 DBG_BLOCK_ID_SQB_BY2 = 0x20,
331 DBG_BLOCK_ID_SQB10_BY2 = 0x21,
332 DBG_BLOCK_ID_UNUSED10_BY2 = 0x22,
333 DBG_BLOCK_ID_UNUSED12_BY2 = 0x23,
334 DBG_BLOCK_ID_CB_BY2 = 0x24,
335 DBG_BLOCK_ID_CB02_BY2 = 0x25,
336 DBG_BLOCK_ID_CB10_BY2 = 0x26,
337 DBG_BLOCK_ID_CB12_BY2 = 0x27,
338 DBG_BLOCK_ID_SXS_BY2 = 0x28,
339 DBG_BLOCK_ID_SXS2_BY2 = 0x29,
340 DBG_BLOCK_ID_SXS4_BY2 = 0x2a,
341 DBG_BLOCK_ID_SXS6_BY2 = 0x2b,
342 DBG_BLOCK_ID_DB_BY2 = 0x2c,
343 DBG_BLOCK_ID_DB02_BY2 = 0x2d,
344 DBG_BLOCK_ID_DB10_BY2 = 0x2e,
345 DBG_BLOCK_ID_DB12_BY2 = 0x2f,
346 DBG_BLOCK_ID_TCP_BY2 = 0x30,
347 DBG_BLOCK_ID_TCP2_BY2 = 0x31,
348 DBG_BLOCK_ID_TCP4_BY2 = 0x32,
349 DBG_BLOCK_ID_TCP6_BY2 = 0x33,
350 DBG_BLOCK_ID_TCP8_BY2 = 0x34,
351 DBG_BLOCK_ID_TCP10_BY2 = 0x35,
352 DBG_BLOCK_ID_TCP12_BY2 = 0x36,
353 DBG_BLOCK_ID_TCP14_BY2 = 0x37,
354 DBG_BLOCK_ID_TCP16_BY2 = 0x38,
355 DBG_BLOCK_ID_TCP18_BY2 = 0x39,
356 DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
357 DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
358 DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
359 DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
360 DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
361 DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
362 DBG_BLOCK_ID_TCC_BY2 = 0x40,
363 DBG_BLOCK_ID_TCC2_BY2 = 0x41,
364 DBG_BLOCK_ID_TCC4_BY2 = 0x42,
365 DBG_BLOCK_ID_TCC6_BY2 = 0x43,
366 DBG_BLOCK_ID_SPS_BY2 = 0x44,
367 DBG_BLOCK_ID_SPS02_BY2 = 0x45,
368 DBG_BLOCK_ID_SPS11_BY2 = 0x46,
369 DBG_BLOCK_ID_UNUSED14_BY2 = 0x47,
370 DBG_BLOCK_ID_TA_BY2 = 0x48,
371 DBG_BLOCK_ID_TA02_BY2 = 0x49,
372 DBG_BLOCK_ID_TA04_BY2 = 0x4a,
373 DBG_BLOCK_ID_TA06_BY2 = 0x4b,
374 DBG_BLOCK_ID_TA08_BY2 = 0x4c,
375 DBG_BLOCK_ID_TA0A_BY2 = 0x4d,
376 DBG_BLOCK_ID_UNUSED20_BY2 = 0x4e,
377 DBG_BLOCK_ID_UNUSED22_BY2 = 0x4f,
378 DBG_BLOCK_ID_TA10_BY2 = 0x50,
379 DBG_BLOCK_ID_TA12_BY2 = 0x51,
380 DBG_BLOCK_ID_TA14_BY2 = 0x52,
381 DBG_BLOCK_ID_TA16_BY2 = 0x53,
382 DBG_BLOCK_ID_TA18_BY2 = 0x54,
383 DBG_BLOCK_ID_TA1A_BY2 = 0x55,
384 DBG_BLOCK_ID_UNUSED24_BY2 = 0x56,
385 DBG_BLOCK_ID_UNUSED26_BY2 = 0x57,
386 DBG_BLOCK_ID_TD_BY2 = 0x58,
387 DBG_BLOCK_ID_TD02_BY2 = 0x59,
388 DBG_BLOCK_ID_TD04_BY2 = 0x5a,
389 DBG_BLOCK_ID_TD06_BY2 = 0x5b,
390 DBG_BLOCK_ID_TD08_BY2 = 0x5c,
391 DBG_BLOCK_ID_TD0A_BY2 = 0x5d,
392 DBG_BLOCK_ID_UNUSED28_BY2 = 0x5e,
393 DBG_BLOCK_ID_UNUSED30_BY2 = 0x5f,
394 DBG_BLOCK_ID_TD10_BY2 = 0x60,
395 DBG_BLOCK_ID_TD12_BY2 = 0x61,
396 DBG_BLOCK_ID_TD14_BY2 = 0x62,
397 DBG_BLOCK_ID_TD16_BY2 = 0x63,
398 DBG_BLOCK_ID_TD18_BY2 = 0x64,
399 DBG_BLOCK_ID_TD1A_BY2 = 0x65,
400 DBG_BLOCK_ID_UNUSED32_BY2 = 0x66,
401 DBG_BLOCK_ID_UNUSED34_BY2 = 0x67,
402 DBG_BLOCK_ID_LDS_BY2 = 0x68,
403 DBG_BLOCK_ID_LDS02_BY2 = 0x69,
404 DBG_BLOCK_ID_LDS04_BY2 = 0x6a,
405 DBG_BLOCK_ID_LDS06_BY2 = 0x6b,
406 DBG_BLOCK_ID_LDS08_BY2 = 0x6c,
407 DBG_BLOCK_ID_LDS0A_BY2 = 0x6d,
408 DBG_BLOCK_ID_UNUSED36_BY2 = 0x6e,
409 DBG_BLOCK_ID_UNUSED38_BY2 = 0x6f,
410 DBG_BLOCK_ID_LDS10_BY2 = 0x70,
411 DBG_BLOCK_ID_LDS12_BY2 = 0x71,
412 DBG_BLOCK_ID_LDS14_BY2 = 0x72,
413 DBG_BLOCK_ID_LDS16_BY2 = 0x73,
414 DBG_BLOCK_ID_LDS18_BY2 = 0x74,
415 DBG_BLOCK_ID_LDS1A_BY2 = 0x75,
416 DBG_BLOCK_ID_UNUSED40_BY2 = 0x76,
417 DBG_BLOCK_ID_UNUSED42_BY2 = 0x77,
418} DebugBlockId_BY2;
419typedef enum DebugBlockId_BY4 {
420 DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
421 DBG_BLOCK_ID_UNUSED0_BY4 = 0x1,
422 DBG_BLOCK_ID_CSC_BY4 = 0x2,
423 DBG_BLOCK_ID_SQ_BY4 = 0x3,
424 DBG_BLOCK_ID_SDMA0_BY4 = 0x4,
425 DBG_BLOCK_ID_VC0_BY4 = 0x5,
426 DBG_BLOCK_ID_CP0_BY4 = 0x6,
427 DBG_BLOCK_ID_UNUSED1_BY4 = 0x7,
428 DBG_BLOCK_ID_SXM0_BY4 = 0x8,
429 DBG_BLOCK_ID_SPM0_BY4 = 0x9,
430 DBG_BLOCK_ID_TCAA_BY4 = 0xa,
431 DBG_BLOCK_ID_MCC_BY4 = 0xb,
432 DBG_BLOCK_ID_MCD_BY4 = 0xc,
433 DBG_BLOCK_ID_MCD4_BY4 = 0xd,
434 DBG_BLOCK_ID_SQA_BY4 = 0xe,
435 DBG_BLOCK_ID_SQA11_BY4 = 0xf,
436 DBG_BLOCK_ID_SQB_BY4 = 0x10,
437 DBG_BLOCK_ID_UNUSED10_BY4 = 0x11,
438 DBG_BLOCK_ID_CB_BY4 = 0x12,
439 DBG_BLOCK_ID_CB10_BY4 = 0x13,
440 DBG_BLOCK_ID_SXS_BY4 = 0x14,
441 DBG_BLOCK_ID_SXS4_BY4 = 0x15,
442 DBG_BLOCK_ID_DB_BY4 = 0x16,
443 DBG_BLOCK_ID_DB10_BY4 = 0x17,
444 DBG_BLOCK_ID_TCP_BY4 = 0x18,
445 DBG_BLOCK_ID_TCP4_BY4 = 0x19,
446 DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
447 DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
448 DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
449 DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
450 DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
451 DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
452 DBG_BLOCK_ID_TCC_BY4 = 0x20,
453 DBG_BLOCK_ID_TCC4_BY4 = 0x21,
454 DBG_BLOCK_ID_SPS_BY4 = 0x22,
455 DBG_BLOCK_ID_SPS11_BY4 = 0x23,
456 DBG_BLOCK_ID_TA_BY4 = 0x24,
457 DBG_BLOCK_ID_TA04_BY4 = 0x25,
458 DBG_BLOCK_ID_TA08_BY4 = 0x26,
459 DBG_BLOCK_ID_UNUSED20_BY4 = 0x27,
460 DBG_BLOCK_ID_TA10_BY4 = 0x28,
461 DBG_BLOCK_ID_TA14_BY4 = 0x29,
462 DBG_BLOCK_ID_TA18_BY4 = 0x2a,
463 DBG_BLOCK_ID_UNUSED24_BY4 = 0x2b,
464 DBG_BLOCK_ID_TD_BY4 = 0x2c,
465 DBG_BLOCK_ID_TD04_BY4 = 0x2d,
466 DBG_BLOCK_ID_TD08_BY4 = 0x2e,
467 DBG_BLOCK_ID_UNUSED28_BY4 = 0x2f,
468 DBG_BLOCK_ID_TD10_BY4 = 0x30,
469 DBG_BLOCK_ID_TD14_BY4 = 0x31,
470 DBG_BLOCK_ID_TD18_BY4 = 0x32,
471 DBG_BLOCK_ID_UNUSED32_BY4 = 0x33,
472 DBG_BLOCK_ID_LDS_BY4 = 0x34,
473 DBG_BLOCK_ID_LDS04_BY4 = 0x35,
474 DBG_BLOCK_ID_LDS08_BY4 = 0x36,
475 DBG_BLOCK_ID_UNUSED36_BY4 = 0x37,
476 DBG_BLOCK_ID_LDS10_BY4 = 0x38,
477 DBG_BLOCK_ID_LDS14_BY4 = 0x39,
478 DBG_BLOCK_ID_LDS18_BY4 = 0x3a,
479 DBG_BLOCK_ID_UNUSED40_BY4 = 0x3b,
480} DebugBlockId_BY4;
481typedef enum DebugBlockId_BY8 {
482 DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
483 DBG_BLOCK_ID_CSC_BY8 = 0x1,
484 DBG_BLOCK_ID_SDMA0_BY8 = 0x2,
485 DBG_BLOCK_ID_CP0_BY8 = 0x3,
486 DBG_BLOCK_ID_SXM0_BY8 = 0x4,
487 DBG_BLOCK_ID_TCA_BY8 = 0x5,
488 DBG_BLOCK_ID_MCD_BY8 = 0x6,
489 DBG_BLOCK_ID_SQA_BY8 = 0x7,
490 DBG_BLOCK_ID_SQB_BY8 = 0x8,
491 DBG_BLOCK_ID_CB_BY8 = 0x9,
492 DBG_BLOCK_ID_SXS_BY8 = 0xa,
493 DBG_BLOCK_ID_DB_BY8 = 0xb,
494 DBG_BLOCK_ID_TCP_BY8 = 0xc,
495 DBG_BLOCK_ID_TCP8_BY8 = 0xd,
496 DBG_BLOCK_ID_TCP16_BY8 = 0xe,
497 DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
498 DBG_BLOCK_ID_TCC_BY8 = 0x10,
499 DBG_BLOCK_ID_SPS_BY8 = 0x11,
500 DBG_BLOCK_ID_TA_BY8 = 0x12,
501 DBG_BLOCK_ID_TA08_BY8 = 0x13,
502 DBG_BLOCK_ID_TA10_BY8 = 0x14,
503 DBG_BLOCK_ID_TA18_BY8 = 0x15,
504 DBG_BLOCK_ID_TD_BY8 = 0x16,
505 DBG_BLOCK_ID_TD08_BY8 = 0x17,
506 DBG_BLOCK_ID_TD10_BY8 = 0x18,
507 DBG_BLOCK_ID_TD18_BY8 = 0x19,
508 DBG_BLOCK_ID_LDS_BY8 = 0x1a,
509 DBG_BLOCK_ID_LDS08_BY8 = 0x1b,
510 DBG_BLOCK_ID_LDS10_BY8 = 0x1c,
511 DBG_BLOCK_ID_LDS18_BY8 = 0x1d,
512} DebugBlockId_BY8;
513typedef enum DebugBlockId_BY16 {
514 DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
515 DBG_BLOCK_ID_SDMA0_BY16 = 0x1,
516 DBG_BLOCK_ID_SXM_BY16 = 0x2,
517 DBG_BLOCK_ID_MCD_BY16 = 0x3,
518 DBG_BLOCK_ID_SQB_BY16 = 0x4,
519 DBG_BLOCK_ID_SXS_BY16 = 0x5,
520 DBG_BLOCK_ID_TCP_BY16 = 0x6,
521 DBG_BLOCK_ID_TCP16_BY16 = 0x7,
522 DBG_BLOCK_ID_TCC_BY16 = 0x8,
523 DBG_BLOCK_ID_TA_BY16 = 0x9,
524 DBG_BLOCK_ID_TA10_BY16 = 0xa,
525 DBG_BLOCK_ID_TD_BY16 = 0xb,
526 DBG_BLOCK_ID_TD10_BY16 = 0xc,
527 DBG_BLOCK_ID_LDS_BY16 = 0xd,
528 DBG_BLOCK_ID_LDS10_BY16 = 0xe,
529} DebugBlockId_BY16;
530typedef enum SurfaceEndian {
531 ENDIAN_NONE = 0x0,
532 ENDIAN_8IN16 = 0x1,
533 ENDIAN_8IN32 = 0x2,
534 ENDIAN_8IN64 = 0x3,
535} SurfaceEndian;
536typedef enum ArrayMode {
537 ARRAY_LINEAR_GENERAL = 0x0,
538 ARRAY_LINEAR_ALIGNED = 0x1,
539 ARRAY_1D_TILED_THIN1 = 0x2,
540 ARRAY_1D_TILED_THICK = 0x3,
541 ARRAY_2D_TILED_THIN1 = 0x4,
542 ARRAY_PRT_TILED_THIN1 = 0x5,
543 ARRAY_PRT_2D_TILED_THIN1 = 0x6,
544 ARRAY_2D_TILED_THICK = 0x7,
545 ARRAY_2D_TILED_XTHICK = 0x8,
546 ARRAY_PRT_TILED_THICK = 0x9,
547 ARRAY_PRT_2D_TILED_THICK = 0xa,
548 ARRAY_PRT_3D_TILED_THIN1 = 0xb,
549 ARRAY_3D_TILED_THIN1 = 0xc,
550 ARRAY_3D_TILED_THICK = 0xd,
551 ARRAY_3D_TILED_XTHICK = 0xe,
552 ARRAY_PRT_3D_TILED_THICK = 0xf,
553} ArrayMode;
554typedef enum PipeTiling {
555 CONFIG_1_PIPE = 0x0,
556 CONFIG_2_PIPE = 0x1,
557 CONFIG_4_PIPE = 0x2,
558 CONFIG_8_PIPE = 0x3,
559} PipeTiling;
560typedef enum BankTiling {
561 CONFIG_4_BANK = 0x0,
562 CONFIG_8_BANK = 0x1,
563} BankTiling;
564typedef enum GroupInterleave {
565 CONFIG_256B_GROUP = 0x0,
566 CONFIG_512B_GROUP = 0x1,
567} GroupInterleave;
568typedef enum RowTiling {
569 CONFIG_1KB_ROW = 0x0,
570 CONFIG_2KB_ROW = 0x1,
571 CONFIG_4KB_ROW = 0x2,
572 CONFIG_8KB_ROW = 0x3,
573 CONFIG_1KB_ROW_OPT = 0x4,
574 CONFIG_2KB_ROW_OPT = 0x5,
575 CONFIG_4KB_ROW_OPT = 0x6,
576 CONFIG_8KB_ROW_OPT = 0x7,
577} RowTiling;
578typedef enum BankSwapBytes {
579 CONFIG_128B_SWAPS = 0x0,
580 CONFIG_256B_SWAPS = 0x1,
581 CONFIG_512B_SWAPS = 0x2,
582 CONFIG_1KB_SWAPS = 0x3,
583} BankSwapBytes;
584typedef enum SampleSplitBytes {
585 CONFIG_1KB_SPLIT = 0x0,
586 CONFIG_2KB_SPLIT = 0x1,
587 CONFIG_4KB_SPLIT = 0x2,
588 CONFIG_8KB_SPLIT = 0x3,
589} SampleSplitBytes;
590typedef enum NumPipes {
591 ADDR_CONFIG_1_PIPE = 0x0,
592 ADDR_CONFIG_2_PIPE = 0x1,
593 ADDR_CONFIG_4_PIPE = 0x2,
594 ADDR_CONFIG_8_PIPE = 0x3,
595} NumPipes;
596typedef enum PipeInterleaveSize {
597 ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
598 ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
599} PipeInterleaveSize;
600typedef enum BankInterleaveSize {
601 ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
602 ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
603 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
604 ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
605} BankInterleaveSize;
606typedef enum NumShaderEngines {
607 ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
608 ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
609} NumShaderEngines;
610typedef enum ShaderEngineTileSize {
611 ADDR_CONFIG_SE_TILE_16 = 0x0,
612 ADDR_CONFIG_SE_TILE_32 = 0x1,
613} ShaderEngineTileSize;
614typedef enum NumGPUs {
615 ADDR_CONFIG_1_GPU = 0x0,
616 ADDR_CONFIG_2_GPU = 0x1,
617 ADDR_CONFIG_4_GPU = 0x2,
618} NumGPUs;
619typedef enum MultiGPUTileSize {
620 ADDR_CONFIG_GPU_TILE_16 = 0x0,
621 ADDR_CONFIG_GPU_TILE_32 = 0x1,
622 ADDR_CONFIG_GPU_TILE_64 = 0x2,
623 ADDR_CONFIG_GPU_TILE_128 = 0x3,
624} MultiGPUTileSize;
625typedef enum RowSize {
626 ADDR_CONFIG_1KB_ROW = 0x0,
627 ADDR_CONFIG_2KB_ROW = 0x1,
628 ADDR_CONFIG_4KB_ROW = 0x2,
629} RowSize;
630typedef enum NumLowerPipes {
631 ADDR_CONFIG_1_LOWER_PIPES = 0x0,
632 ADDR_CONFIG_2_LOWER_PIPES = 0x1,
633} NumLowerPipes;
634typedef enum ColorTransform {
635 DCC_CT_AUTO = 0x0,
636 DCC_CT_NONE = 0x1,
637 ABGR_TO_A_BG_G_RB = 0x2,
638 BGRA_TO_BG_G_RB_A = 0x3,
639} ColorTransform;
640typedef enum CompareRef {
641 REF_NEVER = 0x0,
642 REF_LESS = 0x1,
643 REF_EQUAL = 0x2,
644 REF_LEQUAL = 0x3,
645 REF_GREATER = 0x4,
646 REF_NOTEQUAL = 0x5,
647 REF_GEQUAL = 0x6,
648 REF_ALWAYS = 0x7,
649} CompareRef;
650typedef enum ReadSize {
651 READ_256_BITS = 0x0,
652 READ_512_BITS = 0x1,
653} ReadSize;
654typedef enum DepthFormat {
655 DEPTH_INVALID = 0x0,
656 DEPTH_16 = 0x1,
657 DEPTH_X8_24 = 0x2,
658 DEPTH_8_24 = 0x3,
659 DEPTH_X8_24_FLOAT = 0x4,
660 DEPTH_8_24_FLOAT = 0x5,
661 DEPTH_32_FLOAT = 0x6,
662 DEPTH_X24_8_32_FLOAT = 0x7,
663} DepthFormat;
664typedef enum ZFormat {
665 Z_INVALID = 0x0,
666 Z_16 = 0x1,
667 Z_24 = 0x2,
668 Z_32_FLOAT = 0x3,
669} ZFormat;
670typedef enum StencilFormat {
671 STENCIL_INVALID = 0x0,
672 STENCIL_8 = 0x1,
673} StencilFormat;
674typedef enum CmaskMode {
675 CMASK_CLEAR_NONE = 0x0,
676 CMASK_CLEAR_ONE = 0x1,
677 CMASK_CLEAR_ALL = 0x2,
678 CMASK_ANY_EXPANDED = 0x3,
679 CMASK_ALPHA0_FRAG1 = 0x4,
680 CMASK_ALPHA0_FRAG2 = 0x5,
681 CMASK_ALPHA0_FRAG4 = 0x6,
682 CMASK_ALPHA0_FRAGS = 0x7,
683 CMASK_ALPHA1_FRAG1 = 0x8,
684 CMASK_ALPHA1_FRAG2 = 0x9,
685 CMASK_ALPHA1_FRAG4 = 0xa,
686 CMASK_ALPHA1_FRAGS = 0xb,
687 CMASK_ALPHAX_FRAG1 = 0xc,
688 CMASK_ALPHAX_FRAG2 = 0xd,
689 CMASK_ALPHAX_FRAG4 = 0xe,
690 CMASK_ALPHAX_FRAGS = 0xf,
691} CmaskMode;
692typedef enum QuadExportFormat {
693 EXPORT_UNUSED = 0x0,
694 EXPORT_32_R = 0x1,
695 EXPORT_32_GR = 0x2,
696 EXPORT_32_AR = 0x3,
697 EXPORT_FP16_ABGR = 0x4,
698 EXPORT_UNSIGNED16_ABGR = 0x5,
699 EXPORT_SIGNED16_ABGR = 0x6,
700 EXPORT_32_ABGR = 0x7,
701} QuadExportFormat;
702typedef enum QuadExportFormatOld {
703 EXPORT_4P_32BPC_ABGR = 0x0,
704 EXPORT_4P_16BPC_ABGR = 0x1,
705 EXPORT_4P_32BPC_GR = 0x2,
706 EXPORT_4P_32BPC_AR = 0x3,
707 EXPORT_2P_32BPC_ABGR = 0x4,
708 EXPORT_8P_32BPC_R = 0x5,
709} QuadExportFormatOld;
710typedef enum ColorFormat {
711 COLOR_INVALID = 0x0,
712 COLOR_8 = 0x1,
713 COLOR_16 = 0x2,
714 COLOR_8_8 = 0x3,
715 COLOR_32 = 0x4,
716 COLOR_16_16 = 0x5,
717 COLOR_10_11_11 = 0x6,
718 COLOR_11_11_10 = 0x7,
719 COLOR_10_10_10_2 = 0x8,
720 COLOR_2_10_10_10 = 0x9,
721 COLOR_8_8_8_8 = 0xa,
722 COLOR_32_32 = 0xb,
723 COLOR_16_16_16_16 = 0xc,
724 COLOR_RESERVED_13 = 0xd,
725 COLOR_32_32_32_32 = 0xe,
726 COLOR_RESERVED_15 = 0xf,
727 COLOR_5_6_5 = 0x10,
728 COLOR_1_5_5_5 = 0x11,
729 COLOR_5_5_5_1 = 0x12,
730 COLOR_4_4_4_4 = 0x13,
731 COLOR_8_24 = 0x14,
732 COLOR_24_8 = 0x15,
733 COLOR_X24_8_32_FLOAT = 0x16,
734 COLOR_RESERVED_23 = 0x17,
735} ColorFormat;
736typedef enum SurfaceFormat {
737 FMT_INVALID = 0x0,
738 FMT_8 = 0x1,
739 FMT_16 = 0x2,
740 FMT_8_8 = 0x3,
741 FMT_32 = 0x4,
742 FMT_16_16 = 0x5,
743 FMT_10_11_11 = 0x6,
744 FMT_11_11_10 = 0x7,
745 FMT_10_10_10_2 = 0x8,
746 FMT_2_10_10_10 = 0x9,
747 FMT_8_8_8_8 = 0xa,
748 FMT_32_32 = 0xb,
749 FMT_16_16_16_16 = 0xc,
750 FMT_32_32_32 = 0xd,
751 FMT_32_32_32_32 = 0xe,
752 FMT_RESERVED_4 = 0xf,
753 FMT_5_6_5 = 0x10,
754 FMT_1_5_5_5 = 0x11,
755 FMT_5_5_5_1 = 0x12,
756 FMT_4_4_4_4 = 0x13,
757 FMT_8_24 = 0x14,
758 FMT_24_8 = 0x15,
759 FMT_X24_8_32_FLOAT = 0x16,
760 FMT_RESERVED_33 = 0x17,
761 FMT_11_11_10_FLOAT = 0x18,
762 FMT_16_FLOAT = 0x19,
763 FMT_32_FLOAT = 0x1a,
764 FMT_16_16_FLOAT = 0x1b,
765 FMT_8_24_FLOAT = 0x1c,
766 FMT_24_8_FLOAT = 0x1d,
767 FMT_32_32_FLOAT = 0x1e,
768 FMT_10_11_11_FLOAT = 0x1f,
769 FMT_16_16_16_16_FLOAT = 0x20,
770 FMT_3_3_2 = 0x21,
771 FMT_6_5_5 = 0x22,
772 FMT_32_32_32_32_FLOAT = 0x23,
773 FMT_RESERVED_36 = 0x24,
774 FMT_1 = 0x25,
775 FMT_1_REVERSED = 0x26,
776 FMT_GB_GR = 0x27,
777 FMT_BG_RG = 0x28,
778 FMT_32_AS_8 = 0x29,
779 FMT_32_AS_8_8 = 0x2a,
780 FMT_5_9_9_9_SHAREDEXP = 0x2b,
781 FMT_8_8_8 = 0x2c,
782 FMT_16_16_16 = 0x2d,
783 FMT_16_16_16_FLOAT = 0x2e,
784 FMT_4_4 = 0x2f,
785 FMT_32_32_32_FLOAT = 0x30,
786 FMT_BC1 = 0x31,
787 FMT_BC2 = 0x32,
788 FMT_BC3 = 0x33,
789 FMT_BC4 = 0x34,
790 FMT_BC5 = 0x35,
791 FMT_BC6 = 0x36,
792 FMT_BC7 = 0x37,
793 FMT_32_AS_32_32_32_32 = 0x38,
794 FMT_APC3 = 0x39,
795 FMT_APC4 = 0x3a,
796 FMT_APC5 = 0x3b,
797 FMT_APC6 = 0x3c,
798 FMT_APC7 = 0x3d,
799 FMT_CTX1 = 0x3e,
800 FMT_RESERVED_63 = 0x3f,
801} SurfaceFormat;
802typedef enum BUF_DATA_FORMAT {
803 BUF_DATA_FORMAT_INVALID = 0x0,
804 BUF_DATA_FORMAT_8 = 0x1,
805 BUF_DATA_FORMAT_16 = 0x2,
806 BUF_DATA_FORMAT_8_8 = 0x3,
807 BUF_DATA_FORMAT_32 = 0x4,
808 BUF_DATA_FORMAT_16_16 = 0x5,
809 BUF_DATA_FORMAT_10_11_11 = 0x6,
810 BUF_DATA_FORMAT_11_11_10 = 0x7,
811 BUF_DATA_FORMAT_10_10_10_2 = 0x8,
812 BUF_DATA_FORMAT_2_10_10_10 = 0x9,
813 BUF_DATA_FORMAT_8_8_8_8 = 0xa,
814 BUF_DATA_FORMAT_32_32 = 0xb,
815 BUF_DATA_FORMAT_16_16_16_16 = 0xc,
816 BUF_DATA_FORMAT_32_32_32 = 0xd,
817 BUF_DATA_FORMAT_32_32_32_32 = 0xe,
818 BUF_DATA_FORMAT_RESERVED_15 = 0xf,
819} BUF_DATA_FORMAT;
820typedef enum IMG_DATA_FORMAT {
821 IMG_DATA_FORMAT_INVALID = 0x0,
822 IMG_DATA_FORMAT_8 = 0x1,
823 IMG_DATA_FORMAT_16 = 0x2,
824 IMG_DATA_FORMAT_8_8 = 0x3,
825 IMG_DATA_FORMAT_32 = 0x4,
826 IMG_DATA_FORMAT_16_16 = 0x5,
827 IMG_DATA_FORMAT_10_11_11 = 0x6,
828 IMG_DATA_FORMAT_11_11_10 = 0x7,
829 IMG_DATA_FORMAT_10_10_10_2 = 0x8,
830 IMG_DATA_FORMAT_2_10_10_10 = 0x9,
831 IMG_DATA_FORMAT_8_8_8_8 = 0xa,
832 IMG_DATA_FORMAT_32_32 = 0xb,
833 IMG_DATA_FORMAT_16_16_16_16 = 0xc,
834 IMG_DATA_FORMAT_32_32_32 = 0xd,
835 IMG_DATA_FORMAT_32_32_32_32 = 0xe,
836 IMG_DATA_FORMAT_RESERVED_15 = 0xf,
837 IMG_DATA_FORMAT_5_6_5 = 0x10,
838 IMG_DATA_FORMAT_1_5_5_5 = 0x11,
839 IMG_DATA_FORMAT_5_5_5_1 = 0x12,
840 IMG_DATA_FORMAT_4_4_4_4 = 0x13,
841 IMG_DATA_FORMAT_8_24 = 0x14,
842 IMG_DATA_FORMAT_24_8 = 0x15,
843 IMG_DATA_FORMAT_X24_8_32 = 0x16,
844 IMG_DATA_FORMAT_RESERVED_23 = 0x17,
845 IMG_DATA_FORMAT_RESERVED_24 = 0x18,
846 IMG_DATA_FORMAT_RESERVED_25 = 0x19,
847 IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
848 IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
849 IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
850 IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
851 IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
852 IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
853 IMG_DATA_FORMAT_GB_GR = 0x20,
854 IMG_DATA_FORMAT_BG_RG = 0x21,
855 IMG_DATA_FORMAT_5_9_9_9 = 0x22,
856 IMG_DATA_FORMAT_BC1 = 0x23,
857 IMG_DATA_FORMAT_BC2 = 0x24,
858 IMG_DATA_FORMAT_BC3 = 0x25,
859 IMG_DATA_FORMAT_BC4 = 0x26,
860 IMG_DATA_FORMAT_BC5 = 0x27,
861 IMG_DATA_FORMAT_BC6 = 0x28,
862 IMG_DATA_FORMAT_BC7 = 0x29,
863 IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
864 IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
865 IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
866 IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
867 IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
868 IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
869 IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
870 IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
871 IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
872 IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
873 IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
874 IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
875 IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
876 IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
877 IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
878 IMG_DATA_FORMAT_4_4 = 0x39,
879 IMG_DATA_FORMAT_6_5_5 = 0x3a,
880 IMG_DATA_FORMAT_1 = 0x3b,
881 IMG_DATA_FORMAT_1_REVERSED = 0x3c,
882 IMG_DATA_FORMAT_32_AS_8 = 0x3d,
883 IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
884 IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
885} IMG_DATA_FORMAT;
886typedef enum BUF_NUM_FORMAT {
887 BUF_NUM_FORMAT_UNORM = 0x0,
888 BUF_NUM_FORMAT_SNORM = 0x1,
889 BUF_NUM_FORMAT_USCALED = 0x2,
890 BUF_NUM_FORMAT_SSCALED = 0x3,
891 BUF_NUM_FORMAT_UINT = 0x4,
892 BUF_NUM_FORMAT_SINT = 0x5,
893 BUF_NUM_FORMAT_RESERVED_6 = 0x6,
894 BUF_NUM_FORMAT_FLOAT = 0x7,
895} BUF_NUM_FORMAT;
896typedef enum IMG_NUM_FORMAT {
897 IMG_NUM_FORMAT_UNORM = 0x0,
898 IMG_NUM_FORMAT_SNORM = 0x1,
899 IMG_NUM_FORMAT_USCALED = 0x2,
900 IMG_NUM_FORMAT_SSCALED = 0x3,
901 IMG_NUM_FORMAT_UINT = 0x4,
902 IMG_NUM_FORMAT_SINT = 0x5,
903 IMG_NUM_FORMAT_RESERVED_6 = 0x6,
904 IMG_NUM_FORMAT_FLOAT = 0x7,
905 IMG_NUM_FORMAT_RESERVED_8 = 0x8,
906 IMG_NUM_FORMAT_SRGB = 0x9,
907 IMG_NUM_FORMAT_RESERVED_10 = 0xa,
908 IMG_NUM_FORMAT_RESERVED_11 = 0xb,
909 IMG_NUM_FORMAT_RESERVED_12 = 0xc,
910 IMG_NUM_FORMAT_RESERVED_13 = 0xd,
911 IMG_NUM_FORMAT_RESERVED_14 = 0xe,
912 IMG_NUM_FORMAT_RESERVED_15 = 0xf,
913} IMG_NUM_FORMAT;
914typedef enum TileType {
915 ARRAY_COLOR_TILE = 0x0,
916 ARRAY_DEPTH_TILE = 0x1,
917} TileType;
918typedef enum NonDispTilingOrder {
919 ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
920 ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
921} NonDispTilingOrder;
922typedef enum MicroTileMode {
923 ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
924 ADDR_SURF_THIN_MICRO_TILING = 0x1,
925 ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
926 ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
927 ADDR_SURF_THICK_MICRO_TILING = 0x4,
928} MicroTileMode;
929typedef enum TileSplit {
930 ADDR_SURF_TILE_SPLIT_64B = 0x0,
931 ADDR_SURF_TILE_SPLIT_128B = 0x1,
932 ADDR_SURF_TILE_SPLIT_256B = 0x2,
933 ADDR_SURF_TILE_SPLIT_512B = 0x3,
934 ADDR_SURF_TILE_SPLIT_1KB = 0x4,
935 ADDR_SURF_TILE_SPLIT_2KB = 0x5,
936 ADDR_SURF_TILE_SPLIT_4KB = 0x6,
937} TileSplit;
938typedef enum SampleSplit {
939 ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
940 ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
941 ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
942 ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
943} SampleSplit;
944typedef enum PipeConfig {
945 ADDR_SURF_P2 = 0x0,
946 ADDR_SURF_P2_RESERVED0 = 0x1,
947 ADDR_SURF_P2_RESERVED1 = 0x2,
948 ADDR_SURF_P2_RESERVED2 = 0x3,
949 ADDR_SURF_P4_8x16 = 0x4,
950 ADDR_SURF_P4_16x16 = 0x5,
951 ADDR_SURF_P4_16x32 = 0x6,
952 ADDR_SURF_P4_32x32 = 0x7,
953 ADDR_SURF_P8_16x16_8x16 = 0x8,
954 ADDR_SURF_P8_16x32_8x16 = 0x9,
955 ADDR_SURF_P8_32x32_8x16 = 0xa,
956 ADDR_SURF_P8_16x32_16x16 = 0xb,
957 ADDR_SURF_P8_32x32_16x16 = 0xc,
958 ADDR_SURF_P8_32x32_16x32 = 0xd,
959 ADDR_SURF_P8_32x64_32x32 = 0xe,
960 ADDR_SURF_P8_RESERVED0 = 0xf,
961 ADDR_SURF_P16_32x32_8x16 = 0x10,
962 ADDR_SURF_P16_32x32_16x16 = 0x11,
963} PipeConfig;
964typedef enum NumBanks {
965 ADDR_SURF_2_BANK = 0x0,
966 ADDR_SURF_4_BANK = 0x1,
967 ADDR_SURF_8_BANK = 0x2,
968 ADDR_SURF_16_BANK = 0x3,
969} NumBanks;
970typedef enum BankWidth {
971 ADDR_SURF_BANK_WIDTH_1 = 0x0,
972 ADDR_SURF_BANK_WIDTH_2 = 0x1,
973 ADDR_SURF_BANK_WIDTH_4 = 0x2,
974 ADDR_SURF_BANK_WIDTH_8 = 0x3,
975} BankWidth;
976typedef enum BankHeight {
977 ADDR_SURF_BANK_HEIGHT_1 = 0x0,
978 ADDR_SURF_BANK_HEIGHT_2 = 0x1,
979 ADDR_SURF_BANK_HEIGHT_4 = 0x2,
980 ADDR_SURF_BANK_HEIGHT_8 = 0x3,
981} BankHeight;
982typedef enum BankWidthHeight {
983 ADDR_SURF_BANK_WH_1 = 0x0,
984 ADDR_SURF_BANK_WH_2 = 0x1,
985 ADDR_SURF_BANK_WH_4 = 0x2,
986 ADDR_SURF_BANK_WH_8 = 0x3,
987} BankWidthHeight;
988typedef enum MacroTileAspect {
989 ADDR_SURF_MACRO_ASPECT_1 = 0x0,
990 ADDR_SURF_MACRO_ASPECT_2 = 0x1,
991 ADDR_SURF_MACRO_ASPECT_4 = 0x2,
992 ADDR_SURF_MACRO_ASPECT_8 = 0x3,
993} MacroTileAspect;
994typedef enum GATCL1RequestType {
995 GATCL1_TYPE_NORMAL = 0x0,
996 GATCL1_TYPE_SHOOTDOWN = 0x1,
997 GATCL1_TYPE_BYPASS = 0x2,
998} GATCL1RequestType;
999typedef enum TCC_CACHE_POLICIES {
1000 TCC_CACHE_POLICY_LRU = 0x0,
1001 TCC_CACHE_POLICY_STREAM = 0x1,
1002} TCC_CACHE_POLICIES;
1003typedef enum MTYPE {
1004 MTYPE_NC_NV = 0x0,
1005 MTYPE_NC = 0x1,
1006 MTYPE_CC = 0x2,
1007 MTYPE_UC = 0x3,
1008} MTYPE;
1009typedef enum PERFMON_COUNTER_MODE {
1010 PERFMON_COUNTER_MODE_ACCUM = 0x0,
1011 PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
1012 PERFMON_COUNTER_MODE_MAX = 0x2,
1013 PERFMON_COUNTER_MODE_DIRTY = 0x3,
1014 PERFMON_COUNTER_MODE_SAMPLE = 0x4,
1015 PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
1016 PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
1017 PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
1018 PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
1019 PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
1020 PERFMON_COUNTER_MODE_RESERVED = 0xf,
1021} PERFMON_COUNTER_MODE;
1022typedef enum PERFMON_SPM_MODE {
1023 PERFMON_SPM_MODE_OFF = 0x0,
1024 PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
1025 PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
1026 PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
1027 PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
1028 PERFMON_SPM_MODE_RESERVED_5 = 0x5,
1029 PERFMON_SPM_MODE_RESERVED_6 = 0x6,
1030 PERFMON_SPM_MODE_RESERVED_7 = 0x7,
1031 PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
1032 PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
1033 PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
1034} PERFMON_SPM_MODE;
1035typedef enum SurfaceTiling {
1036 ARRAY_LINEAR = 0x0,
1037 ARRAY_TILED = 0x1,
1038} SurfaceTiling;
1039typedef enum SurfaceArray {
1040 ARRAY_1D = 0x0,
1041 ARRAY_2D = 0x1,
1042 ARRAY_3D = 0x2,
1043 ARRAY_3D_SLICE = 0x3,
1044} SurfaceArray;
1045typedef enum ColorArray {
1046 ARRAY_2D_ALT_COLOR = 0x0,
1047 ARRAY_2D_COLOR = 0x1,
1048 ARRAY_3D_SLICE_COLOR = 0x3,
1049} ColorArray;
1050typedef enum DepthArray {
1051 ARRAY_2D_ALT_DEPTH = 0x0,
1052 ARRAY_2D_DEPTH = 0x1,
1053} DepthArray;
1054typedef enum ENUM_NUM_SIMD_PER_CU {
1055 NUM_SIMD_PER_CU = 0x4,
1056} ENUM_NUM_SIMD_PER_CU;
1057typedef enum MEM_PWR_FORCE_CTRL {
1058 NO_FORCE_REQUEST = 0x0,
1059 FORCE_LIGHT_SLEEP_REQUEST = 0x1,
1060 FORCE_DEEP_SLEEP_REQUEST = 0x2,
1061 FORCE_SHUT_DOWN_REQUEST = 0x3,
1062} MEM_PWR_FORCE_CTRL;
1063typedef enum MEM_PWR_FORCE_CTRL2 {
1064 NO_FORCE_REQ = 0x0,
1065 FORCE_LIGHT_SLEEP_REQ = 0x1,
1066} MEM_PWR_FORCE_CTRL2;
1067typedef enum MEM_PWR_DIS_CTRL {
1068 ENABLE_MEM_PWR_CTRL = 0x0,
1069 DISABLE_MEM_PWR_CTRL = 0x1,
1070} MEM_PWR_DIS_CTRL;
1071typedef enum MEM_PWR_SEL_CTRL {
1072 DYNAMIC_SHUT_DOWN_ENABLE = 0x0,
1073 DYNAMIC_DEEP_SLEEP_ENABLE = 0x1,
1074 DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
1075} MEM_PWR_SEL_CTRL;
1076typedef enum MEM_PWR_SEL_CTRL2 {
1077 DYNAMIC_DEEP_SLEEP_EN = 0x0,
1078 DYNAMIC_LIGHT_SLEEP_EN = 0x1,
1079} MEM_PWR_SEL_CTRL2;
1080
1081#endif /* UVD_6_0_ENUM_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h
new file mode 100644
index 000000000000..9917c543d895
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h
@@ -0,0 +1,1034 @@
1/*
2 * UVD_6_0 Register documentation
3 *
4 * Copyright (C) 2014 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#ifndef UVD_6_0_SH_MASK_H
25#define UVD_6_0_SH_MASK_H
26
27#define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28#define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29#define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30#define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31#define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32#define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33#define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34#define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35#define UVD_SEMA_CMD__MODE_MASK 0x40
36#define UVD_SEMA_CMD__MODE__SHIFT 0x6
37#define UVD_SEMA_CMD__VMID_EN_MASK 0x80
38#define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7
39#define UVD_SEMA_CMD__VMID_MASK 0xf00
40#define UVD_SEMA_CMD__VMID__SHIFT 0x8
41#define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x1
42#define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0
43#define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7ffffffe
44#define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1
45#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000
46#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f
47#define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xffffffff
48#define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0
49#define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xffffffff
50#define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0
51#define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x1
52#define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0
53#define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x2
54#define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1
55#define UVD_UDEC_ADDR_CONFIG__NUM_PIPES_MASK 0x7
56#define UVD_UDEC_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
57#define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
58#define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
59#define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
60#define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
61#define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
62#define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
63#define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
64#define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
65#define UVD_UDEC_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
66#define UVD_UDEC_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
67#define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
68#define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
69#define UVD_UDEC_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
70#define UVD_UDEC_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
71#define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
72#define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
73#define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES_MASK 0x7
74#define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
75#define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
76#define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
77#define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
78#define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
79#define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
80#define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
81#define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
82#define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
83#define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
84#define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
85#define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
86#define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
87#define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
88#define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
89#define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
90#define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
91#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK 0x7
92#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
93#define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
94#define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
95#define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
96#define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
97#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
98#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
99#define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
100#define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
101#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
102#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
103#define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
104#define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
105#define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
106#define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
107#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
108#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
109#define UVD_POWER_STATUS_U__UVD_POWER_STATUS_MASK 0x3
110#define UVD_POWER_STATUS_U__UVD_POWER_STATUS__SHIFT 0x0
111#define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xffffffff
112#define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
113#define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xffffffff
114#define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
115#define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xffffffff
116#define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
117#define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xffffffff
118#define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
119#define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xffffffff
120#define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
121#define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xffffffff
122#define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
123#define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x1
124#define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0
125#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x2
126#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1
127#define UVD_LMI_EXT40_ADDR__ADDR_MASK 0xff
128#define UVD_LMI_EXT40_ADDR__ADDR__SHIFT 0x0
129#define UVD_LMI_EXT40_ADDR__INDEX_MASK 0x1f0000
130#define UVD_LMI_EXT40_ADDR__INDEX__SHIFT 0x10
131#define UVD_LMI_EXT40_ADDR__WRITE_ADDR_MASK 0x80000000
132#define UVD_LMI_EXT40_ADDR__WRITE_ADDR__SHIFT 0x1f
133#define UVD_CTX_INDEX__INDEX_MASK 0x1ff
134#define UVD_CTX_INDEX__INDEX__SHIFT 0x0
135#define UVD_CTX_DATA__DATA_MASK 0xffffffff
136#define UVD_CTX_DATA__DATA__SHIFT 0x0
137#define UVD_CGC_GATE__SYS_MASK 0x1
138#define UVD_CGC_GATE__SYS__SHIFT 0x0
139#define UVD_CGC_GATE__UDEC_MASK 0x2
140#define UVD_CGC_GATE__UDEC__SHIFT 0x1
141#define UVD_CGC_GATE__MPEG2_MASK 0x4
142#define UVD_CGC_GATE__MPEG2__SHIFT 0x2
143#define UVD_CGC_GATE__REGS_MASK 0x8
144#define UVD_CGC_GATE__REGS__SHIFT 0x3
145#define UVD_CGC_GATE__RBC_MASK 0x10
146#define UVD_CGC_GATE__RBC__SHIFT 0x4
147#define UVD_CGC_GATE__LMI_MC_MASK 0x20
148#define UVD_CGC_GATE__LMI_MC__SHIFT 0x5
149#define UVD_CGC_GATE__LMI_UMC_MASK 0x40
150#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6
151#define UVD_CGC_GATE__IDCT_MASK 0x80
152#define UVD_CGC_GATE__IDCT__SHIFT 0x7
153#define UVD_CGC_GATE__MPRD_MASK 0x100
154#define UVD_CGC_GATE__MPRD__SHIFT 0x8
155#define UVD_CGC_GATE__MPC_MASK 0x200
156#define UVD_CGC_GATE__MPC__SHIFT 0x9
157#define UVD_CGC_GATE__LBSI_MASK 0x400
158#define UVD_CGC_GATE__LBSI__SHIFT 0xa
159#define UVD_CGC_GATE__LRBBM_MASK 0x800
160#define UVD_CGC_GATE__LRBBM__SHIFT 0xb
161#define UVD_CGC_GATE__UDEC_RE_MASK 0x1000
162#define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc
163#define UVD_CGC_GATE__UDEC_CM_MASK 0x2000
164#define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd
165#define UVD_CGC_GATE__UDEC_IT_MASK 0x4000
166#define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe
167#define UVD_CGC_GATE__UDEC_DB_MASK 0x8000
168#define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf
169#define UVD_CGC_GATE__UDEC_MP_MASK 0x10000
170#define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10
171#define UVD_CGC_GATE__WCB_MASK 0x20000
172#define UVD_CGC_GATE__WCB__SHIFT 0x11
173#define UVD_CGC_GATE__VCPU_MASK 0x40000
174#define UVD_CGC_GATE__VCPU__SHIFT 0x12
175#define UVD_CGC_GATE__SCPU_MASK 0x80000
176#define UVD_CGC_GATE__SCPU__SHIFT 0x13
177#define UVD_CGC_GATE__JPEG_MASK 0x100000
178#define UVD_CGC_GATE__JPEG__SHIFT 0x14
179#define UVD_CGC_GATE__JPEG2_MASK 0x200000
180#define UVD_CGC_GATE__JPEG2__SHIFT 0x15
181#define UVD_CGC_STATUS__SYS_SCLK_MASK 0x1
182#define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x0
183#define UVD_CGC_STATUS__SYS_DCLK_MASK 0x2
184#define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1
185#define UVD_CGC_STATUS__SYS_VCLK_MASK 0x4
186#define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2
187#define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x8
188#define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x3
189#define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x10
190#define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x4
191#define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x20
192#define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5
193#define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x40
194#define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6
195#define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x80
196#define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7
197#define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x100
198#define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8
199#define UVD_CGC_STATUS__REGS_SCLK_MASK 0x200
200#define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x9
201#define UVD_CGC_STATUS__REGS_VCLK_MASK 0x400
202#define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa
203#define UVD_CGC_STATUS__RBC_SCLK_MASK 0x800
204#define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0xb
205#define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x1000
206#define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc
207#define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x2000
208#define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd
209#define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x4000
210#define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe
211#define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x8000
212#define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf
213#define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x10000
214#define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10
215#define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x20000
216#define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11
217#define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x40000
218#define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12
219#define UVD_CGC_STATUS__MPC_SCLK_MASK 0x80000
220#define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13
221#define UVD_CGC_STATUS__MPC_DCLK_MASK 0x100000
222#define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14
223#define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x200000
224#define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x15
225#define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x400000
226#define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x16
227#define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x800000
228#define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17
229#define UVD_CGC_STATUS__WCB_SCLK_MASK 0x1000000
230#define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x18
231#define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x2000000
232#define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x19
233#define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x4000000
234#define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a
235#define UVD_CGC_STATUS__SCPU_SCLK_MASK 0x8000000
236#define UVD_CGC_STATUS__SCPU_SCLK__SHIFT 0x1b
237#define UVD_CGC_STATUS__SCPU_VCLK_MASK 0x10000000
238#define UVD_CGC_STATUS__SCPU_VCLK__SHIFT 0x1c
239#define UVD_CGC_STATUS__JPEG_ACTIVE_MASK 0x40000000
240#define UVD_CGC_STATUS__JPEG_ACTIVE__SHIFT 0x1e
241#define UVD_CGC_STATUS__ALL_DEC_ACTIVE_MASK 0x80000000
242#define UVD_CGC_STATUS__ALL_DEC_ACTIVE__SHIFT 0x1f
243#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x1
244#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0
245#define UVD_CGC_CTRL__JPEG2_MODE_MASK 0x2
246#define UVD_CGC_CTRL__JPEG2_MODE__SHIFT 0x1
247#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x3c
248#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2
249#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x7c0
250#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6
251#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x800
252#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb
253#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x1000
254#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc
255#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x2000
256#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd
257#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x4000
258#define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe
259#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x8000
260#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf
261#define UVD_CGC_CTRL__SYS_MODE_MASK 0x10000
262#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10
263#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x20000
264#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11
265#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x40000
266#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12
267#define UVD_CGC_CTRL__REGS_MODE_MASK 0x80000
268#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13
269#define UVD_CGC_CTRL__RBC_MODE_MASK 0x100000
270#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14
271#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x200000
272#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15
273#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x400000
274#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16
275#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x800000
276#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17
277#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x1000000
278#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18
279#define UVD_CGC_CTRL__MPC_MODE_MASK 0x2000000
280#define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19
281#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x4000000
282#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a
283#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x8000000
284#define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b
285#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000
286#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c
287#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000
288#define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d
289#define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000
290#define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x1e
291#define UVD_CGC_CTRL__JPEG_MODE_MASK 0x80000000
292#define UVD_CGC_CTRL__JPEG_MODE__SHIFT 0x1f
293#define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x1
294#define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x0
295#define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x2
296#define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x1
297#define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x4
298#define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x2
299#define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x8
300#define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x3
301#define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x10
302#define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4
303#define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x20
304#define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5
305#define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x40
306#define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x6
307#define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x80
308#define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x7
309#define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x100
310#define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x8
311#define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x200
312#define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x9
313#define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x400
314#define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa
315#define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x800
316#define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0xb
317#define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x1000
318#define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0xc
319#define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x2000
320#define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0xd
321#define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x4000
322#define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe
323#define UVD_CGC_UDEC_STATUS__JPEG_VCLK_MASK 0x8000
324#define UVD_CGC_UDEC_STATUS__JPEG_VCLK__SHIFT 0xf
325#define UVD_CGC_UDEC_STATUS__JPEG_SCLK_MASK 0x10000
326#define UVD_CGC_UDEC_STATUS__JPEG_SCLK__SHIFT 0x10
327#define UVD_CGC_UDEC_STATUS__JPEG2_VCLK_MASK 0x20000
328#define UVD_CGC_UDEC_STATUS__JPEG2_VCLK__SHIFT 0x11
329#define UVD_CGC_UDEC_STATUS__JPEG2_SCLK_MASK 0x40000
330#define UVD_CGC_UDEC_STATUS__JPEG2_SCLK__SHIFT 0x12
331#define UVD_LMI_CTRL2__SPH_DIS_MASK 0x1
332#define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0
333#define UVD_LMI_CTRL2__STALL_ARB_MASK 0x2
334#define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1
335#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x4
336#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2
337#define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x8
338#define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3
339#define UVD_LMI_CTRL2__MCIF_WR_WATERMARK_MASK 0x70
340#define UVD_LMI_CTRL2__MCIF_WR_WATERMARK__SHIFT 0x4
341#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x80
342#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7
343#define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100
344#define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8
345#define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x600
346#define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9
347#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x1800
348#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb
349#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x2000
350#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0xd
351#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x4000
352#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0xe
353#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x8000
354#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0xf
355#define UVD_LMI_CTRL2__RE_OFFLOAD_EN_MASK 0x10000
356#define UVD_LMI_CTRL2__RE_OFFLOAD_EN__SHIFT 0x10
357#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x1fe0000
358#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11
359#define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x1
360#define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0
361#define UVD_MASTINT_EN__VCPU_EN_MASK 0x2
362#define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1
363#define UVD_MASTINT_EN__SYS_EN_MASK 0x4
364#define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2
365#define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x7ffff0
366#define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4
367#define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT_MASK 0xf
368#define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT__SHIFT 0x0
369#define UVD_LMI_ADDR_EXT__CM_ADDR_EXT_MASK 0xf0
370#define UVD_LMI_ADDR_EXT__CM_ADDR_EXT__SHIFT 0x4
371#define UVD_LMI_ADDR_EXT__IT_ADDR_EXT_MASK 0xf00
372#define UVD_LMI_ADDR_EXT__IT_ADDR_EXT__SHIFT 0x8
373#define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT_MASK 0xf000
374#define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT__SHIFT 0xc
375#define UVD_LMI_ADDR_EXT__RE_ADDR_EXT_MASK 0xf0000
376#define UVD_LMI_ADDR_EXT__RE_ADDR_EXT__SHIFT 0x10
377#define UVD_LMI_ADDR_EXT__MP_ADDR_EXT_MASK 0xf00000
378#define UVD_LMI_ADDR_EXT__MP_ADDR_EXT__SHIFT 0x14
379#define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT_MASK 0xf000000
380#define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT__SHIFT 0x18
381#define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT_MASK 0xf0000000
382#define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT__SHIFT 0x1c
383#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0xff
384#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0
385#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x100
386#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8
387#define UVD_LMI_CTRL__REQ_MODE_MASK 0x200
388#define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9
389#define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x800
390#define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb
391#define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x1000
392#define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc
393#define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x2000
394#define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd
395#define UVD_LMI_CTRL__CRC_RESET_MASK 0x4000
396#define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe
397#define UVD_LMI_CTRL__CRC_SEL_MASK 0xf8000
398#define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf
399#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK 0x100000
400#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT 0x14
401#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x200000
402#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15
403#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x400000
404#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16
405#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x800000
406#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17
407#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x1000000
408#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18
409#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x2000000
410#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19
411#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x4000000
412#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x1a
413#define UVD_LMI_CTRL__RFU_MASK 0xf8000000
414#define UVD_LMI_CTRL__RFU__SHIFT 0x1b
415#define UVD_LMI_STATUS__READ_CLEAN_MASK 0x1
416#define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0
417#define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x2
418#define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1
419#define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x4
420#define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2
421#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x8
422#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3
423#define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x10
424#define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x4
425#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x20
426#define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5
427#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x40
428#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6
429#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x80
430#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x7
431#define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x100
432#define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x8
433#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x200
434#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9
435#define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x400
436#define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa
437#define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x800
438#define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0xb
439#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x1000
440#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0xc
441#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x2000
442#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0xd
443#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP_MASK 0x3
444#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0
445#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP_MASK 0xc
446#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2
447#define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x30
448#define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x4
449#define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0xc0
450#define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x6
451#define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x300
452#define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x8
453#define UVD_LMI_SWAP_CNTL__CM_MC_SWAP_MASK 0xc00
454#define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa
455#define UVD_LMI_SWAP_CNTL__IT_MC_SWAP_MASK 0x3000
456#define UVD_LMI_SWAP_CNTL__IT_MC_SWAP__SHIFT 0xc
457#define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP_MASK 0xc000
458#define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe
459#define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x30000
460#define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x10
461#define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP_MASK 0xc0000
462#define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x12
463#define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP_MASK 0xc00000
464#define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP__SHIFT 0x16
465#define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP_MASK 0x3000000
466#define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x18
467#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0xc000000
468#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x1a
469#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000
470#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x1c
471#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xc0000000
472#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x1e
473#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x3
474#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x0
475#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0xc
476#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2
477#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x30
478#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x4
479#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0xc0
480#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x6
481#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x300
482#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x8
483#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0xc00
484#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa
485#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x3000
486#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0xc
487#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0xc000
488#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0xe
489#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x30000
490#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x10
491#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0xc0000
492#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x12
493#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x300000
494#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14
495#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0xc00000
496#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x16
497#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x3000000
498#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x18
499#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0xc000000
500#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x1a
501#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000
502#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x1c
503#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xc0000000
504#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x1e
505#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x38
506#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3
507#define UVD_MPC_CNTL__PERF_RST_MASK 0x40
508#define UVD_MPC_CNTL__PERF_RST__SHIFT 0x6
509#define UVD_MPC_CNTL__DBG_MUX_MASK 0xf00
510#define UVD_MPC_CNTL__DBG_MUX__SHIFT 0x8
511#define UVD_MPC_CNTL__AVE_WEIGHT_MASK 0x30000
512#define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT 0x10
513#define UVD_MPC_CNTL__URGENT_EN_MASK 0x40000
514#define UVD_MPC_CNTL__URGENT_EN__SHIFT 0x12
515#define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x3f
516#define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0
517#define UVD_MPC_SET_MUXA0__VARA_1_MASK 0xfc0
518#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6
519#define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x3f000
520#define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc
521#define UVD_MPC_SET_MUXA0__VARA_3_MASK 0xfc0000
522#define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12
523#define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3f000000
524#define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18
525#define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x3f
526#define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0
527#define UVD_MPC_SET_MUXA1__VARA_6_MASK 0xfc0
528#define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6
529#define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x3f000
530#define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc
531#define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x3f
532#define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0
533#define UVD_MPC_SET_MUXB0__VARB_1_MASK 0xfc0
534#define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6
535#define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x3f000
536#define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc
537#define UVD_MPC_SET_MUXB0__VARB_3_MASK 0xfc0000
538#define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12
539#define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3f000000
540#define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18
541#define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x3f
542#define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0
543#define UVD_MPC_SET_MUXB1__VARB_6_MASK 0xfc0
544#define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6
545#define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x3f000
546#define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc
547#define UVD_MPC_SET_MUX__SET_0_MASK 0x7
548#define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0
549#define UVD_MPC_SET_MUX__SET_1_MASK 0x38
550#define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3
551#define UVD_MPC_SET_MUX__SET_2_MASK 0x1c0
552#define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6
553#define UVD_MPC_SET_ALU__FUNCT_MASK 0x7
554#define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0
555#define UVD_MPC_SET_ALU__OPERAND_MASK 0xff0
556#define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4
557#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x1ffffff
558#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0
559#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x1fffff
560#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0
561#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x1ffffff
562#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0
563#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x1fffff
564#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0
565#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x1ffffff
566#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0
567#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x1fffff
568#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0
569#define UVD_VCPU_CNTL__IRQ_ERR_MASK 0xf
570#define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x0
571#define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4_MASK 0x10
572#define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4__SHIFT 0x4
573#define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x20
574#define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x5
575#define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x40
576#define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x6
577#define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x80
578#define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7
579#define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x100
580#define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x8
581#define UVD_VCPU_CNTL__CLK_EN_MASK 0x200
582#define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9
583#define UVD_VCPU_CNTL__TRCE_EN_MASK 0x400
584#define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa
585#define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x1800
586#define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb
587#define UVD_VCPU_CNTL__DBG_MUX_MASK 0xe000
588#define UVD_VCPU_CNTL__DBG_MUX__SHIFT 0xd
589#define UVD_VCPU_CNTL__JTAG_EN_MASK 0x10000
590#define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x10
591#define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK 0x20000
592#define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP__SHIFT 0x11
593#define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x40000
594#define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x12
595#define UVD_VCPU_CNTL__SUVD_EN_MASK 0x80000
596#define UVD_VCPU_CNTL__SUVD_EN__SHIFT 0x13
597#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0xff00000
598#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14
599#define UVD_VCPU_CNTL__CABAC_MB_ACC_MASK 0x10000000
600#define UVD_VCPU_CNTL__CABAC_MB_ACC__SHIFT 0x1c
601#define UVD_VCPU_CNTL__WMV9_EN_MASK 0x40000000
602#define UVD_VCPU_CNTL__WMV9_EN__SHIFT 0x1e
603#define UVD_VCPU_CNTL__RE_OFFLOAD_EN_MASK 0x80000000
604#define UVD_VCPU_CNTL__RE_OFFLOAD_EN__SHIFT 0x1f
605#define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x1
606#define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0
607#define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x2
608#define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1
609#define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x4
610#define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2
611#define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x8
612#define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3
613#define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x10
614#define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4
615#define UVD_SOFT_RESET__CSM_SOFT_RESET_MASK 0x20
616#define UVD_SOFT_RESET__CSM_SOFT_RESET__SHIFT 0x5
617#define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x40
618#define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6
619#define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x80
620#define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7
621#define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x100
622#define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8
623#define UVD_SOFT_RESET__JPEG_SCLK_RESET_STATUS_MASK 0x200
624#define UVD_SOFT_RESET__JPEG_SCLK_RESET_STATUS__SHIFT 0x9
625#define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x400
626#define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa
627#define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x800
628#define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0xb
629#define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x1000
630#define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0xc
631#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x2000
632#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd
633#define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x4000
634#define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe
635#define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x8000
636#define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf
637#define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x10000
638#define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10
639#define UVD_SOFT_RESET__SUVD_SOFT_RESET_MASK 0x20000
640#define UVD_SOFT_RESET__SUVD_SOFT_RESET__SHIFT 0x11
641#define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS_MASK 0x40000
642#define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS__SHIFT 0x12
643#define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS_MASK 0x80000
644#define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS__SHIFT 0x13
645#define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS_MASK 0x100000
646#define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS__SHIFT 0x14
647#define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS_MASK 0x200000
648#define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS__SHIFT 0x15
649#define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS_MASK 0x400000
650#define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS__SHIFT 0x16
651#define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS_MASK 0x800000
652#define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS__SHIFT 0x17
653#define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS_MASK 0x1000000
654#define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS__SHIFT 0x18
655#define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS_MASK 0x2000000
656#define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS__SHIFT 0x19
657#define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS_MASK 0x4000000
658#define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS__SHIFT 0x1a
659#define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS_MASK 0x8000000
660#define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS__SHIFT 0x1b
661#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000
662#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS__SHIFT 0x1c
663#define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS_MASK 0x20000000
664#define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS__SHIFT 0x1d
665#define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS_MASK 0x40000000
666#define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS__SHIFT 0x1e
667#define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS_MASK 0x80000000
668#define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS__SHIFT 0x1f
669#define UVD_LMI_RBC_IB_VMID__IB_VMID_MASK 0xf
670#define UVD_LMI_RBC_IB_VMID__IB_VMID__SHIFT 0x0
671#define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x7ffff0
672#define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4
673#define UVD_LMI_RBC_RB_VMID__RB_VMID_MASK 0xf
674#define UVD_LMI_RBC_RB_VMID__RB_VMID__SHIFT 0x0
675#define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x7ffff0
676#define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4
677#define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x7ffff0
678#define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4
679#define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x1f
680#define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0
681#define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x1f00
682#define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8
683#define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x10000
684#define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10
685#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x100000
686#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14
687#define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x1000000
688#define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18
689#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000
690#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c
691#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xffffffff
692#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0
693#define UVD_STATUS__RBC_BUSY_MASK 0x1
694#define UVD_STATUS__RBC_BUSY__SHIFT 0x0
695#define UVD_STATUS__VCPU_REPORT_MASK 0xfe
696#define UVD_STATUS__VCPU_REPORT__SHIFT 0x1
697#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x1
698#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0
699#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x2
700#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1
701#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x4
702#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2
703#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x8
704#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3
705#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x1
706#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0
707#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x1ffffe
708#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1
709#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000
710#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18
711#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x1
712#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0
713#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x1ffffe
714#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1
715#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000
716#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18
717#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x1
718#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0
719#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x1ffffe
720#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1
721#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000
722#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18
723#define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xffffffff
724#define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0
725#define UVD_SUVD_CGC_GATE__SRE_MASK 0x1
726#define UVD_SUVD_CGC_GATE__SRE__SHIFT 0x0
727#define UVD_SUVD_CGC_GATE__SIT_MASK 0x2
728#define UVD_SUVD_CGC_GATE__SIT__SHIFT 0x1
729#define UVD_SUVD_CGC_GATE__SMP_MASK 0x4
730#define UVD_SUVD_CGC_GATE__SMP__SHIFT 0x2
731#define UVD_SUVD_CGC_GATE__SCM_MASK 0x8
732#define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3
733#define UVD_SUVD_CGC_GATE__SDB_MASK 0x10
734#define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4
735#define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x20
736#define UVD_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5
737#define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x40
738#define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6
739#define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x80
740#define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7
741#define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x100
742#define UVD_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8
743#define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x200
744#define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9
745#define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x400
746#define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
747#define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x800
748#define UVD_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb
749#define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x1000
750#define UVD_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc
751#define UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK 0x1
752#define UVD_SUVD_CGC_STATUS__SRE_VCLK__SHIFT 0x0
753#define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK 0x2
754#define UVD_SUVD_CGC_STATUS__SRE_DCLK__SHIFT 0x1
755#define UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK 0x4
756#define UVD_SUVD_CGC_STATUS__SIT_DCLK__SHIFT 0x2
757#define UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 0x8
758#define UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT 0x3
759#define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK 0x10
760#define UVD_SUVD_CGC_STATUS__SCM_DCLK__SHIFT 0x4
761#define UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 0x20
762#define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT 0x5
763#define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK 0x40
764#define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT 0x6
765#define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x80
766#define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK__SHIFT 0x7
767#define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK_MASK 0x100
768#define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK__SHIFT 0x8
769#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 0x200
770#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT 0x9
771#define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK_MASK 0x400
772#define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa
773#define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK 0x800
774#define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT 0xb
775#define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK_MASK 0x1000
776#define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK__SHIFT 0xc
777#define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK 0x2000
778#define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT 0xd
779#define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x1
780#define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0
781#define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x2
782#define UVD_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1
783#define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x4
784#define UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2
785#define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x8
786#define UVD_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3
787#define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x10
788#define UVD_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4
789#define UVD_LMI_VMID_INTERNAL__VCPU_NC0_VMID_MASK 0xf
790#define UVD_LMI_VMID_INTERNAL__VCPU_NC0_VMID__SHIFT 0x0
791#define UVD_LMI_VMID_INTERNAL__VCPU_NC1_VMID_MASK 0xf0
792#define UVD_LMI_VMID_INTERNAL__VCPU_NC1_VMID__SHIFT 0x4
793#define UVD_LMI_VMID_INTERNAL__DPB_VMID_MASK 0xf00
794#define UVD_LMI_VMID_INTERNAL__DPB_VMID__SHIFT 0x8
795#define UVD_LMI_VMID_INTERNAL__DBW_VMID_MASK 0xf000
796#define UVD_LMI_VMID_INTERNAL__DBW_VMID__SHIFT 0xc
797#define UVD_LMI_VMID_INTERNAL__LBSI_VMID_MASK 0xf0000
798#define UVD_LMI_VMID_INTERNAL__LBSI_VMID__SHIFT 0x10
799#define UVD_LMI_VMID_INTERNAL__IDCT_VMID_MASK 0xf00000
800#define UVD_LMI_VMID_INTERNAL__IDCT_VMID__SHIFT 0x14
801#define UVD_LMI_VMID_INTERNAL__JPEG_VMID_MASK 0xf000000
802#define UVD_LMI_VMID_INTERNAL__JPEG_VMID__SHIFT 0x18
803#define UVD_LMI_VMID_INTERNAL__JPEG2_VMID_MASK 0xf0000000
804#define UVD_LMI_VMID_INTERNAL__JPEG2_VMID__SHIFT 0x1c
805#define UVD_LMI_VMID_INTERNAL2__MIF_GPGPU_VMID_MASK 0xf
806#define UVD_LMI_VMID_INTERNAL2__MIF_GPGPU_VMID__SHIFT 0x0
807#define UVD_LMI_VMID_INTERNAL2__MIF_CURR_VMID_MASK 0xf0
808#define UVD_LMI_VMID_INTERNAL2__MIF_CURR_VMID__SHIFT 0x4
809#define UVD_LMI_VMID_INTERNAL2__MIF_REF_VMID_MASK 0xf00
810#define UVD_LMI_VMID_INTERNAL2__MIF_REF_VMID__SHIFT 0x8
811#define UVD_LMI_VMID_INTERNAL2__MIF_DBW_VMID_MASK 0xf000
812#define UVD_LMI_VMID_INTERNAL2__MIF_DBW_VMID__SHIFT 0xc
813#define UVD_LMI_VMID_INTERNAL2__MIF_CM_COLOC_VMID_MASK 0xf0000
814#define UVD_LMI_VMID_INTERNAL2__MIF_CM_COLOC_VMID__SHIFT 0x10
815#define UVD_LMI_VMID_INTERNAL2__MIF_BSD_VMID_MASK 0xf00000
816#define UVD_LMI_VMID_INTERNAL2__MIF_BSD_VMID__SHIFT 0x14
817#define UVD_LMI_VMID_INTERNAL2__MIF_BSP_VMID_MASK 0xf000000
818#define UVD_LMI_VMID_INTERNAL2__MIF_BSP_VMID__SHIFT 0x18
819#define UVD_LMI_VMID_INTERNAL2__VDMA_VMID_MASK 0xf0000000
820#define UVD_LMI_VMID_INTERNAL2__VDMA_VMID__SHIFT 0x1c
821#define UVD_LMI_CACHE_CTRL__IT_EN_MASK 0x1
822#define UVD_LMI_CACHE_CTRL__IT_EN__SHIFT 0x0
823#define UVD_LMI_CACHE_CTRL__IT_FLUSH_MASK 0x2
824#define UVD_LMI_CACHE_CTRL__IT_FLUSH__SHIFT 0x1
825#define UVD_LMI_CACHE_CTRL__CM_EN_MASK 0x4
826#define UVD_LMI_CACHE_CTRL__CM_EN__SHIFT 0x2
827#define UVD_LMI_CACHE_CTRL__CM_FLUSH_MASK 0x8
828#define UVD_LMI_CACHE_CTRL__CM_FLUSH__SHIFT 0x3
829#define UVD_LMI_CACHE_CTRL__VCPU_EN_MASK 0x10
830#define UVD_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x4
831#define UVD_LMI_CACHE_CTRL__VCPU_FLUSH_MASK 0x20
832#define UVD_LMI_CACHE_CTRL__VCPU_FLUSH__SHIFT 0x5
833#define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP_MASK 0x3
834#define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP__SHIFT 0x0
835#define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP_MASK 0xc
836#define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP__SHIFT 0x2
837#define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT_MASK 0xf
838#define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT__SHIFT 0x0
839#define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT_MASK 0xf0
840#define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT__SHIFT 0x4
841#define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT_MASK 0xf00
842#define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT__SHIFT 0x8
843#define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT_MASK 0xf000
844#define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT__SHIFT 0xc
845#define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN_MASK 0x1
846#define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN__SHIFT 0x0
847#define UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK 0x2
848#define UVD_CGC_MEM_CTRL__MPC_LS_EN__SHIFT 0x1
849#define UVD_CGC_MEM_CTRL__MPRD_LS_EN_MASK 0x4
850#define UVD_CGC_MEM_CTRL__MPRD_LS_EN__SHIFT 0x2
851#define UVD_CGC_MEM_CTRL__WCB_LS_EN_MASK 0x8
852#define UVD_CGC_MEM_CTRL__WCB_LS_EN__SHIFT 0x3
853#define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN_MASK 0x10
854#define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN__SHIFT 0x4
855#define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK 0x20
856#define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 0x5
857#define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN_MASK 0x40
858#define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN__SHIFT 0x6
859#define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK 0x80
860#define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN__SHIFT 0x7
861#define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN_MASK 0x100
862#define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN__SHIFT 0x8
863#define UVD_CGC_MEM_CTRL__SYS_LS_EN_MASK 0x200
864#define UVD_CGC_MEM_CTRL__SYS_LS_EN__SHIFT 0x9
865#define UVD_CGC_MEM_CTRL__VCPU_LS_EN_MASK 0x400
866#define UVD_CGC_MEM_CTRL__VCPU_LS_EN__SHIFT 0xa
867#define UVD_CGC_MEM_CTRL__SCPU_LS_EN_MASK 0x800
868#define UVD_CGC_MEM_CTRL__SCPU_LS_EN__SHIFT 0xb
869#define UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK 0x1000
870#define UVD_CGC_MEM_CTRL__MIF_LS_EN__SHIFT 0xc
871#define UVD_CGC_MEM_CTRL__LCM_LS_EN_MASK 0x2000
872#define UVD_CGC_MEM_CTRL__LCM_LS_EN__SHIFT 0xd
873#define UVD_CGC_MEM_CTRL__JPEG_LS_EN_MASK 0x4000
874#define UVD_CGC_MEM_CTRL__JPEG_LS_EN__SHIFT 0xe
875#define UVD_CGC_MEM_CTRL__JPEG2_LS_EN_MASK 0x8000
876#define UVD_CGC_MEM_CTRL__JPEG2_LS_EN__SHIFT 0xf
877#define UVD_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0xf0000
878#define UVD_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10
879#define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0xf00000
880#define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14
881#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x1
882#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x0
883#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x2
884#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x1
885#define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x1c
886#define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x2
887#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD0_VMID_MASK 0xf
888#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD0_VMID__SHIFT 0x0
889#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD1_VMID_MASK 0xf0
890#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD1_VMID__SHIFT 0x4
891#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR0_VMID_MASK 0xf00
892#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR0_VMID__SHIFT 0x8
893#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR1_VMID_MASK 0xf000
894#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR1_VMID__SHIFT 0xc
895#define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK 0xff
896#define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR__SHIFT 0x0
897#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK 0x100
898#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN__SHIFT 0x8
899#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK 0x200
900#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP__SHIFT 0x9
901#define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK 0x400
902#define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT__SHIFT 0xa
903#define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT_MASK 0x800
904#define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT__SHIFT 0xb
905#define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE_MASK 0x1000
906#define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE__SHIFT 0xc
907#define UVD_PGFSM_CONFIG__UVD_PGFSM_READ_MASK 0x2000
908#define UVD_PGFSM_CONFIG__UVD_PGFSM_READ__SHIFT 0xd
909#define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR_MASK 0xf0000000
910#define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR__SHIFT 0x1c
911#define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE_MASK 0xffffff
912#define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE__SHIFT 0x0
913#define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE_MASK 0xffffff
914#define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE__SHIFT 0x0
915#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x3
916#define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0
917#define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x4
918#define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2
919#define UVD_POWER_STATUS__UVD_STATUS_CHECK_TIMEOUT_MASK 0x8
920#define UVD_POWER_STATUS__UVD_STATUS_CHECK_TIMEOUT__SHIFT 0x3
921#define UVD_POWER_STATUS__PWR_ON_CHECK_TIMEOUT_MASK 0x10
922#define UVD_POWER_STATUS__PWR_ON_CHECK_TIMEOUT__SHIFT 0x4
923#define UVD_POWER_STATUS__PWR_OFF_CHECK_TIMEOUT_MASK 0x20
924#define UVD_POWER_STATUS__PWR_OFF_CHECK_TIMEOUT__SHIFT 0x5
925#define UVD_POWER_STATUS__UVD_PGFSM_TIMEOUT_MODE_MASK 0xc0
926#define UVD_POWER_STATUS__UVD_PGFSM_TIMEOUT_MODE__SHIFT 0x6
927#define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x100
928#define UVD_POWER_STATUS__UVD_PG_EN__SHIFT 0x8
929#define UVD_POWER_STATUS__PAUSE_DPG_REQ_MASK 0x200
930#define UVD_POWER_STATUS__PAUSE_DPG_REQ__SHIFT 0x9
931#define UVD_POWER_STATUS__PAUSE_DPG_ACK_MASK 0x400
932#define UVD_POWER_STATUS__PAUSE_DPG_ACK__SHIFT 0xa
933#define UVD_PGFSM_READ_TILE3__UVD_PGFSM_READ_TILE3_VALUE_MASK 0xffffff
934#define UVD_PGFSM_READ_TILE3__UVD_PGFSM_READ_TILE3_VALUE__SHIFT 0x0
935#define UVD_PGFSM_READ_TILE4__UVD_PGFSM_READ_TILE4_VALUE_MASK 0xffffff
936#define UVD_PGFSM_READ_TILE4__UVD_PGFSM_READ_TILE4_VALUE__SHIFT 0x0
937#define UVD_PGFSM_READ_TILE5__UVD_PGFSM_READ_TILE5_VALUE_MASK 0xffffff
938#define UVD_PGFSM_READ_TILE5__UVD_PGFSM_READ_TILE5_VALUE__SHIFT 0x0
939#define UVD_PGFSM_READ_TILE6__UVD_PGFSM_READ_TILE6_VALUE_MASK 0xffffff
940#define UVD_PGFSM_READ_TILE6__UVD_PGFSM_READ_TILE6_VALUE__SHIFT 0x0
941#define UVD_PGFSM_READ_TILE7__UVD_PGFSM_READ_TILE7_VALUE_MASK 0xffffff
942#define UVD_PGFSM_READ_TILE7__UVD_PGFSM_READ_TILE7_VALUE__SHIFT 0x0
943#define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES_MASK 0x7
944#define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
945#define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
946#define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
947#define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
948#define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
949#define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
950#define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
951#define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
952#define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
953#define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
954#define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
955#define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
956#define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
957#define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
958#define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
959#define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
960#define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
961#define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES_MASK 0x7
962#define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
963#define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
964#define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
965#define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
966#define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
967#define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
968#define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
969#define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
970#define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
971#define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
972#define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
973#define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
974#define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
975#define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
976#define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
977#define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
978#define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
979#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES_MASK 0x7
980#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
981#define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
982#define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
983#define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
984#define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
985#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
986#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
987#define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
988#define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
989#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
990#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
991#define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
992#define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
993#define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
994#define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
995#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
996#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
997#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_PIPES_MASK 0x7
998#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
999#define UVD_MIF_SCLR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
1000#define UVD_MIF_SCLR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
1001#define UVD_MIF_SCLR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
1002#define UVD_MIF_SCLR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
1003#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
1004#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
1005#define UVD_MIF_SCLR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
1006#define UVD_MIF_SCLR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
1007#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
1008#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
1009#define UVD_MIF_SCLR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
1010#define UVD_MIF_SCLR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
1011#define UVD_MIF_SCLR_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
1012#define UVD_MIF_SCLR_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
1013#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
1014#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
1015#define UVD_JPEG_ADDR_CONFIG__NUM_PIPES_MASK 0x7
1016#define UVD_JPEG_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
1017#define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
1018#define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
1019#define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
1020#define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
1021#define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
1022#define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
1023#define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
1024#define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
1025#define UVD_JPEG_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
1026#define UVD_JPEG_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
1027#define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
1028#define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
1029#define UVD_JPEG_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
1030#define UVD_JPEG_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
1031#define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
1032#define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
1033
1034#endif /* UVD_6_0_SH_MASK_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-30 15:54:08 -0400