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authorLinus Torvalds <torvalds@linux-foundation.org>2017-03-01 12:42:42 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2017-03-01 12:42:42 -0500
commit3437f9f0a69c7c9e926f702fb0d1abd1f750a40e (patch)
tree0685d6d4cf9b5e3a81552e823de7366c5d18d92f /drivers/gpu
parentf3ecc84b09df461639d59a313f50dc21d205e0b1 (diff)
parent9bb92f51558f2ef5f56c257bdcea0588f31d857e (diff)
Merge tag 'drm-ast-2500-for-v4.11' of git://people.freedesktop.org/~airlied/linux
Pull drm AST2500 support from Dave Airlie: "This is a set of changes to enable the AST2500 BMC hardware, and also fix some bugs interacting with the older AST hardware. Some of the bug fixes are cc'ed to stable" * tag 'drm-ast-2500-for-v4.11' of git://people.freedesktop.org/~airlied/linux: drm/ast: Call open_key before enable_mmio in POST code drm/ast: Fix test for VGA enabled drm/ast: POST code for the new AST2500 drm/ast: Rename ast_init_dram_2300 to ast_post_chip_2300 drm/ast: Factor mmc_test code in POST code drm/ast: Fixed vram size incorrect issue on POWER drm/ast: Base support for AST2500 drm/ast: Fix calculation of MCLK drm/ast: Remove spurious include drm/ast: const'ify mode setting tables drm/ast: Handle configuration without P2A bridge drm/ast: Fix AST2400 POST failure without BMC FW or VBIOS
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/ast/ast_dram_tables.h62
-rw-r--r--drivers/gpu/drm/ast/ast_drv.h12
-rw-r--r--drivers/gpu/drm/ast/ast_main.c304
-rw-r--r--drivers/gpu/drm/ast/ast_mode.c38
-rw-r--r--drivers/gpu/drm/ast/ast_post.c562
-rw-r--r--drivers/gpu/drm/ast/ast_tables.h164
6 files changed, 883 insertions, 259 deletions
diff --git a/drivers/gpu/drm/ast/ast_dram_tables.h b/drivers/gpu/drm/ast/ast_dram_tables.h
index cc04539c0ff3..1d9c4e75d303 100644
--- a/drivers/gpu/drm/ast/ast_dram_tables.h
+++ b/drivers/gpu/drm/ast/ast_dram_tables.h
@@ -141,4 +141,66 @@ static const struct ast_dramstruct ast2100_dram_table_data[] = {
141 { 0xffff, 0xffffffff }, 141 { 0xffff, 0xffffffff },
142}; 142};
143 143
144/*
145 * AST2500 DRAM settings modules
146 */
147#define REGTBL_NUM 17
148#define REGIDX_010 0
149#define REGIDX_014 1
150#define REGIDX_018 2
151#define REGIDX_020 3
152#define REGIDX_024 4
153#define REGIDX_02C 5
154#define REGIDX_030 6
155#define REGIDX_214 7
156#define REGIDX_2E0 8
157#define REGIDX_2E4 9
158#define REGIDX_2E8 10
159#define REGIDX_2EC 11
160#define REGIDX_2F0 12
161#define REGIDX_2F4 13
162#define REGIDX_2F8 14
163#define REGIDX_RFC 15
164#define REGIDX_PLL 16
165
166static const u32 ast2500_ddr3_1600_timing_table[REGTBL_NUM] = {
167 0x64604D38, /* 0x010 */
168 0x29690599, /* 0x014 */
169 0x00000300, /* 0x018 */
170 0x00000000, /* 0x020 */
171 0x00000000, /* 0x024 */
172 0x02181E70, /* 0x02C */
173 0x00000040, /* 0x030 */
174 0x00000024, /* 0x214 */
175 0x02001300, /* 0x2E0 */
176 0x0E0000A0, /* 0x2E4 */
177 0x000E001B, /* 0x2E8 */
178 0x35B8C105, /* 0x2EC */
179 0x08090408, /* 0x2F0 */
180 0x9B000800, /* 0x2F4 */
181 0x0E400A00, /* 0x2F8 */
182 0x9971452F, /* tRFC */
183 0x000071C1 /* PLL */
184};
185
186static const u32 ast2500_ddr4_1600_timing_table[REGTBL_NUM] = {
187 0x63604E37, /* 0x010 */
188 0xE97AFA99, /* 0x014 */
189 0x00019000, /* 0x018 */
190 0x08000000, /* 0x020 */
191 0x00000400, /* 0x024 */
192 0x00000410, /* 0x02C */
193 0x00000101, /* 0x030 */
194 0x00000024, /* 0x214 */
195 0x03002900, /* 0x2E0 */
196 0x0E0000A0, /* 0x2E4 */
197 0x000E001C, /* 0x2E8 */
198 0x35B8C106, /* 0x2EC */
199 0x08080607, /* 0x2F0 */
200 0x9B000900, /* 0x2F4 */
201 0x0E400A00, /* 0x2F8 */
202 0x99714545, /* tRFC */
203 0x000071C1 /* PLL */
204};
205
144#endif 206#endif
diff --git a/drivers/gpu/drm/ast/ast_drv.h b/drivers/gpu/drm/ast/ast_drv.h
index 5a8fa1c85229..8880f0b62e9c 100644
--- a/drivers/gpu/drm/ast/ast_drv.h
+++ b/drivers/gpu/drm/ast/ast_drv.h
@@ -65,6 +65,7 @@ enum ast_chip {
65 AST2150, 65 AST2150,
66 AST2300, 66 AST2300,
67 AST2400, 67 AST2400,
68 AST2500,
68 AST1180, 69 AST1180,
69}; 70};
70 71
@@ -81,6 +82,7 @@ enum ast_tx_chip {
81#define AST_DRAM_1Gx32 3 82#define AST_DRAM_1Gx32 3
82#define AST_DRAM_2Gx16 6 83#define AST_DRAM_2Gx16 6
83#define AST_DRAM_4Gx16 7 84#define AST_DRAM_4Gx16 7
85#define AST_DRAM_8Gx16 8
84 86
85struct ast_fbdev; 87struct ast_fbdev;
86 88
@@ -114,7 +116,11 @@ struct ast_private {
114 struct ttm_bo_kmap_obj cache_kmap; 116 struct ttm_bo_kmap_obj cache_kmap;
115 int next_cursor; 117 int next_cursor;
116 bool support_wide_screen; 118 bool support_wide_screen;
117 bool DisableP2A; 119 enum {
120 ast_use_p2a,
121 ast_use_dt,
122 ast_use_defaults
123 } config_mode;
118 124
119 enum ast_tx_chip tx_chip_type; 125 enum ast_tx_chip tx_chip_type;
120 u8 dp501_maxclk; 126 u8 dp501_maxclk;
@@ -301,8 +307,8 @@ struct ast_vbios_dclk_info {
301}; 307};
302 308
303struct ast_vbios_mode_info { 309struct ast_vbios_mode_info {
304 struct ast_vbios_stdtable *std_table; 310 const struct ast_vbios_stdtable *std_table;
305 struct ast_vbios_enhtable *enh_table; 311 const struct ast_vbios_enhtable *enh_table;
306}; 312};
307 313
308extern int ast_mode_init(struct drm_device *dev); 314extern int ast_mode_init(struct drm_device *dev);
diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c
index 993909430736..262c2c0e43b4 100644
--- a/drivers/gpu/drm/ast/ast_main.c
+++ b/drivers/gpu/drm/ast/ast_main.c
@@ -32,8 +32,6 @@
32#include <drm/drm_fb_helper.h> 32#include <drm/drm_fb_helper.h>
33#include <drm/drm_crtc_helper.h> 33#include <drm/drm_crtc_helper.h>
34 34
35#include "ast_dram_tables.h"
36
37void ast_set_index_reg_mask(struct ast_private *ast, 35void ast_set_index_reg_mask(struct ast_private *ast,
38 uint32_t base, uint8_t index, 36 uint32_t base, uint8_t index,
39 uint8_t mask, uint8_t val) 37 uint8_t mask, uint8_t val)
@@ -62,30 +60,99 @@ uint8_t ast_get_index_reg_mask(struct ast_private *ast,
62 return ret; 60 return ret;
63} 61}
64 62
63static void ast_detect_config_mode(struct drm_device *dev, u32 *scu_rev)
64{
65 struct device_node *np = dev->pdev->dev.of_node;
66 struct ast_private *ast = dev->dev_private;
67 uint32_t data, jregd0, jregd1;
68
69 /* Defaults */
70 ast->config_mode = ast_use_defaults;
71 *scu_rev = 0xffffffff;
72
73 /* Check if we have device-tree properties */
74 if (np && !of_property_read_u32(np, "aspeed,scu-revision-id",
75 scu_rev)) {
76 /* We do, disable P2A access */
77 ast->config_mode = ast_use_dt;
78 DRM_INFO("Using device-tree for configuration\n");
79 return;
80 }
81
82 /* Not all families have a P2A bridge */
83 if (dev->pdev->device != PCI_CHIP_AST2000)
84 return;
85
86 /*
87 * The BMC will set SCU 0x40 D[12] to 1 if the P2 bridge
88 * is disabled. We force using P2A if VGA only mode bit
89 * is set D[7]
90 */
91 jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
92 jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
93 if (!(jregd0 & 0x80) || !(jregd1 & 0x10)) {
94 /* Double check it's actually working */
95 data = ast_read32(ast, 0xf004);
96 if (data != 0xFFFFFFFF) {
97 /* P2A works, grab silicon revision */
98 ast->config_mode = ast_use_p2a;
99
100 DRM_INFO("Using P2A bridge for configuration\n");
101
102 /* Read SCU7c (silicon revision register) */
103 ast_write32(ast, 0xf004, 0x1e6e0000);
104 ast_write32(ast, 0xf000, 0x1);
105 *scu_rev = ast_read32(ast, 0x1207c);
106 return;
107 }
108 }
109
110 /* We have a P2A bridge but it's disabled */
111 DRM_INFO("P2A bridge disabled, using default configuration\n");
112}
65 113
66static int ast_detect_chip(struct drm_device *dev, bool *need_post) 114static int ast_detect_chip(struct drm_device *dev, bool *need_post)
67{ 115{
68 struct ast_private *ast = dev->dev_private; 116 struct ast_private *ast = dev->dev_private;
69 uint32_t data, jreg; 117 uint32_t jreg, scu_rev;
118
119 /*
120 * If VGA isn't enabled, we need to enable now or subsequent
121 * access to the scratch registers will fail. We also inform
122 * our caller that it needs to POST the chip
123 * (Assumption: VGA not enabled -> need to POST)
124 */
125 if (!ast_is_vga_enabled(dev)) {
126 ast_enable_vga(dev);
127 DRM_INFO("VGA not enabled on entry, requesting chip POST\n");
128 *need_post = true;
129 } else
130 *need_post = false;
131
132
133 /* Enable extended register access */
134 ast_enable_mmio(dev);
70 ast_open_key(ast); 135 ast_open_key(ast);
71 136
137 /* Find out whether P2A works or whether to use device-tree */
138 ast_detect_config_mode(dev, &scu_rev);
139
140 /* Identify chipset */
72 if (dev->pdev->device == PCI_CHIP_AST1180) { 141 if (dev->pdev->device == PCI_CHIP_AST1180) {
73 ast->chip = AST1100; 142 ast->chip = AST1100;
74 DRM_INFO("AST 1180 detected\n"); 143 DRM_INFO("AST 1180 detected\n");
75 } else { 144 } else {
76 if (dev->pdev->revision >= 0x30) { 145 if (dev->pdev->revision >= 0x40) {
146 ast->chip = AST2500;
147 DRM_INFO("AST 2500 detected\n");
148 } else if (dev->pdev->revision >= 0x30) {
77 ast->chip = AST2400; 149 ast->chip = AST2400;
78 DRM_INFO("AST 2400 detected\n"); 150 DRM_INFO("AST 2400 detected\n");
79 } else if (dev->pdev->revision >= 0x20) { 151 } else if (dev->pdev->revision >= 0x20) {
80 ast->chip = AST2300; 152 ast->chip = AST2300;
81 DRM_INFO("AST 2300 detected\n"); 153 DRM_INFO("AST 2300 detected\n");
82 } else if (dev->pdev->revision >= 0x10) { 154 } else if (dev->pdev->revision >= 0x10) {
83 uint32_t data; 155 switch (scu_rev & 0x0300) {
84 ast_write32(ast, 0xf004, 0x1e6e0000);
85 ast_write32(ast, 0xf000, 0x1);
86
87 data = ast_read32(ast, 0x1207c);
88 switch (data & 0x0300) {
89 case 0x0200: 156 case 0x0200:
90 ast->chip = AST1100; 157 ast->chip = AST1100;
91 DRM_INFO("AST 1100 detected\n"); 158 DRM_INFO("AST 1100 detected\n");
@@ -110,26 +177,6 @@ static int ast_detect_chip(struct drm_device *dev, bool *need_post)
110 } 177 }
111 } 178 }
112 179
113 /*
114 * If VGA isn't enabled, we need to enable now or subsequent
115 * access to the scratch registers will fail. We also inform
116 * our caller that it needs to POST the chip
117 * (Assumption: VGA not enabled -> need to POST)
118 */
119 if (!ast_is_vga_enabled(dev)) {
120 ast_enable_vga(dev);
121 ast_enable_mmio(dev);
122 DRM_INFO("VGA not enabled on entry, requesting chip POST\n");
123 *need_post = true;
124 } else
125 *need_post = false;
126
127 /* Check P2A Access */
128 ast->DisableP2A = true;
129 data = ast_read32(ast, 0xf004);
130 if (data != 0xFFFFFFFF)
131 ast->DisableP2A = false;
132
133 /* Check if we support wide screen */ 180 /* Check if we support wide screen */
134 switch (ast->chip) { 181 switch (ast->chip) {
135 case AST1180: 182 case AST1180:
@@ -146,17 +193,15 @@ static int ast_detect_chip(struct drm_device *dev, bool *need_post)
146 ast->support_wide_screen = true; 193 ast->support_wide_screen = true;
147 else { 194 else {
148 ast->support_wide_screen = false; 195 ast->support_wide_screen = false;
149 if (ast->DisableP2A == false) { 196 if (ast->chip == AST2300 &&
150 /* Read SCU7c (silicon revision register) */ 197 (scu_rev & 0x300) == 0x0) /* ast1300 */
151 ast_write32(ast, 0xf004, 0x1e6e0000); 198 ast->support_wide_screen = true;
152 ast_write32(ast, 0xf000, 0x1); 199 if (ast->chip == AST2400 &&
153 data = ast_read32(ast, 0x1207c); 200 (scu_rev & 0x300) == 0x100) /* ast1400 */
154 data &= 0x300; 201 ast->support_wide_screen = true;
155 if (ast->chip == AST2300 && data == 0x0) /* ast1300 */ 202 if (ast->chip == AST2500 &&
156 ast->support_wide_screen = true; 203 scu_rev == 0x100) /* ast2510 */
157 if (ast->chip == AST2400 && data == 0x100) /* ast1400 */ 204 ast->support_wide_screen = true;
158 ast->support_wide_screen = true;
159 }
160 } 205 }
161 break; 206 break;
162 } 207 }
@@ -220,85 +265,121 @@ static int ast_detect_chip(struct drm_device *dev, bool *need_post)
220 265
221static int ast_get_dram_info(struct drm_device *dev) 266static int ast_get_dram_info(struct drm_device *dev)
222{ 267{
268 struct device_node *np = dev->pdev->dev.of_node;
223 struct ast_private *ast = dev->dev_private; 269 struct ast_private *ast = dev->dev_private;
224 uint32_t data, data2; 270 uint32_t mcr_cfg, mcr_scu_mpll, mcr_scu_strap;
225 uint32_t denum, num, div, ref_pll; 271 uint32_t denum, num, div, ref_pll, dsel;
226 272
227 if (ast->DisableP2A) 273 switch (ast->config_mode) {
228 { 274 case ast_use_dt:
229 ast->dram_bus_width = 16; 275 /*
230 ast->dram_type = AST_DRAM_1Gx16; 276 * If some properties are missing, use reasonable
231 ast->mclk = 396; 277 * defaults for AST2400
232 } 278 */
233 else 279 if (of_property_read_u32(np, "aspeed,mcr-configuration",
234 { 280 &mcr_cfg))
281 mcr_cfg = 0x00000577;
282 if (of_property_read_u32(np, "aspeed,mcr-scu-mpll",
283 &mcr_scu_mpll))
284 mcr_scu_mpll = 0x000050C0;
285 if (of_property_read_u32(np, "aspeed,mcr-scu-strap",
286 &mcr_scu_strap))
287 mcr_scu_strap = 0;
288 break;
289 case ast_use_p2a:
235 ast_write32(ast, 0xf004, 0x1e6e0000); 290 ast_write32(ast, 0xf004, 0x1e6e0000);
236 ast_write32(ast, 0xf000, 0x1); 291 ast_write32(ast, 0xf000, 0x1);
237 data = ast_read32(ast, 0x10004); 292 mcr_cfg = ast_read32(ast, 0x10004);
238 293 mcr_scu_mpll = ast_read32(ast, 0x10120);
239 if (data & 0x40) 294 mcr_scu_strap = ast_read32(ast, 0x10170);
240 ast->dram_bus_width = 16; 295 break;
296 case ast_use_defaults:
297 default:
298 ast->dram_bus_width = 16;
299 ast->dram_type = AST_DRAM_1Gx16;
300 if (ast->chip == AST2500)
301 ast->mclk = 800;
241 else 302 else
242 ast->dram_bus_width = 32; 303 ast->mclk = 396;
243 304 return 0;
244 if (ast->chip == AST2300 || ast->chip == AST2400) { 305 }
245 switch (data & 0x03) {
246 case 0:
247 ast->dram_type = AST_DRAM_512Mx16;
248 break;
249 default:
250 case 1:
251 ast->dram_type = AST_DRAM_1Gx16;
252 break;
253 case 2:
254 ast->dram_type = AST_DRAM_2Gx16;
255 break;
256 case 3:
257 ast->dram_type = AST_DRAM_4Gx16;
258 break;
259 }
260 } else {
261 switch (data & 0x0c) {
262 case 0:
263 case 4:
264 ast->dram_type = AST_DRAM_512Mx16;
265 break;
266 case 8:
267 if (data & 0x40)
268 ast->dram_type = AST_DRAM_1Gx16;
269 else
270 ast->dram_type = AST_DRAM_512Mx32;
271 break;
272 case 0xc:
273 ast->dram_type = AST_DRAM_1Gx32;
274 break;
275 }
276 }
277 306
278 data = ast_read32(ast, 0x10120); 307 if (mcr_cfg & 0x40)
279 data2 = ast_read32(ast, 0x10170); 308 ast->dram_bus_width = 16;
280 if (data2 & 0x2000) 309 else
281 ref_pll = 14318; 310 ast->dram_bus_width = 32;
282 else
283 ref_pll = 12000;
284 311
285 denum = data & 0x1f; 312 if (ast->chip == AST2500) {
286 num = (data & 0x3fe0) >> 5; 313 switch (mcr_cfg & 0x03) {
287 data = (data & 0xc000) >> 14; 314 case 0:
288 switch (data) { 315 ast->dram_type = AST_DRAM_1Gx16;
289 case 3:
290 div = 0x4;
291 break; 316 break;
292 case 2: 317 default:
293 case 1: 318 case 1:
294 div = 0x2; 319 ast->dram_type = AST_DRAM_2Gx16;
320 break;
321 case 2:
322 ast->dram_type = AST_DRAM_4Gx16;
323 break;
324 case 3:
325 ast->dram_type = AST_DRAM_8Gx16;
326 break;
327 }
328 } else if (ast->chip == AST2300 || ast->chip == AST2400) {
329 switch (mcr_cfg & 0x03) {
330 case 0:
331 ast->dram_type = AST_DRAM_512Mx16;
295 break; 332 break;
296 default: 333 default:
297 div = 0x1; 334 case 1:
335 ast->dram_type = AST_DRAM_1Gx16;
336 break;
337 case 2:
338 ast->dram_type = AST_DRAM_2Gx16;
339 break;
340 case 3:
341 ast->dram_type = AST_DRAM_4Gx16;
342 break;
343 }
344 } else {
345 switch (mcr_cfg & 0x0c) {
346 case 0:
347 case 4:
348 ast->dram_type = AST_DRAM_512Mx16;
349 break;
350 case 8:
351 if (mcr_cfg & 0x40)
352 ast->dram_type = AST_DRAM_1Gx16;
353 else
354 ast->dram_type = AST_DRAM_512Mx32;
355 break;
356 case 0xc:
357 ast->dram_type = AST_DRAM_1Gx32;
298 break; 358 break;
299 } 359 }
300 ast->mclk = ref_pll * (num + 2) / (denum + 2) * (div * 1000);
301 } 360 }
361
362 if (mcr_scu_strap & 0x2000)
363 ref_pll = 14318;
364 else
365 ref_pll = 12000;
366
367 denum = mcr_scu_mpll & 0x1f;
368 num = (mcr_scu_mpll & 0x3fe0) >> 5;
369 dsel = (mcr_scu_mpll & 0xc000) >> 14;
370 switch (dsel) {
371 case 3:
372 div = 0x4;
373 break;
374 case 2:
375 case 1:
376 div = 0x2;
377 break;
378 default:
379 div = 0x1;
380 break;
381 }
382 ast->mclk = ref_pll * (num + 2) / ((denum + 2) * (div * 1000));
302 return 0; 383 return 0;
303} 384}
304 385
@@ -437,17 +518,19 @@ int ast_driver_load(struct drm_device *dev, unsigned long flags)
437 518
438 ast_detect_chip(dev, &need_post); 519 ast_detect_chip(dev, &need_post);
439 520
521 if (need_post)
522 ast_post_gpu(dev);
523
440 if (ast->chip != AST1180) { 524 if (ast->chip != AST1180) {
441 ret = ast_get_dram_info(dev); 525 ret = ast_get_dram_info(dev);
442 if (ret) 526 if (ret)
443 goto out_free; 527 goto out_free;
444 ast->vram_size = ast_get_vram_info(dev); 528 ast->vram_size = ast_get_vram_info(dev);
445 DRM_INFO("dram %d %d %d %08x\n", ast->mclk, ast->dram_type, ast->dram_bus_width, ast->vram_size); 529 DRM_INFO("dram MCLK=%u Mhz type=%d bus_width=%d size=%08x\n",
530 ast->mclk, ast->dram_type,
531 ast->dram_bus_width, ast->vram_size);
446 } 532 }
447 533
448 if (need_post)
449 ast_post_gpu(dev);
450
451 ret = ast_mm_init(ast); 534 ret = ast_mm_init(ast);
452 if (ret) 535 if (ret)
453 goto out_free; 536 goto out_free;
@@ -465,6 +548,7 @@ int ast_driver_load(struct drm_device *dev, unsigned long flags)
465 ast->chip == AST2200 || 548 ast->chip == AST2200 ||
466 ast->chip == AST2300 || 549 ast->chip == AST2300 ||
467 ast->chip == AST2400 || 550 ast->chip == AST2400 ||
551 ast->chip == AST2500 ||
468 ast->chip == AST1180) { 552 ast->chip == AST1180) {
469 dev->mode_config.max_width = 1920; 553 dev->mode_config.max_width = 1920;
470 dev->mode_config.max_height = 2048; 554 dev->mode_config.max_height = 2048;
diff --git a/drivers/gpu/drm/ast/ast_mode.c b/drivers/gpu/drm/ast/ast_mode.c
index 606cb40f6c7c..47b78e52691c 100644
--- a/drivers/gpu/drm/ast/ast_mode.c
+++ b/drivers/gpu/drm/ast/ast_mode.c
@@ -81,9 +81,9 @@ static bool ast_get_vbios_mode_info(struct drm_crtc *crtc, struct drm_display_mo
81 struct ast_private *ast = crtc->dev->dev_private; 81 struct ast_private *ast = crtc->dev->dev_private;
82 const struct drm_framebuffer *fb = crtc->primary->fb; 82 const struct drm_framebuffer *fb = crtc->primary->fb;
83 u32 refresh_rate_index = 0, mode_id, color_index, refresh_rate; 83 u32 refresh_rate_index = 0, mode_id, color_index, refresh_rate;
84 const struct ast_vbios_enhtable *best = NULL;
84 u32 hborder, vborder; 85 u32 hborder, vborder;
85 bool check_sync; 86 bool check_sync;
86 struct ast_vbios_enhtable *best = NULL;
87 87
88 switch (fb->format->cpp[0] * 8) { 88 switch (fb->format->cpp[0] * 8) {
89 case 8: 89 case 8:
@@ -147,7 +147,7 @@ static bool ast_get_vbios_mode_info(struct drm_crtc *crtc, struct drm_display_mo
147 refresh_rate = drm_mode_vrefresh(mode); 147 refresh_rate = drm_mode_vrefresh(mode);
148 check_sync = vbios_mode->enh_table->flags & WideScreenMode; 148 check_sync = vbios_mode->enh_table->flags & WideScreenMode;
149 do { 149 do {
150 struct ast_vbios_enhtable *loop = vbios_mode->enh_table; 150 const struct ast_vbios_enhtable *loop = vbios_mode->enh_table;
151 151
152 while (loop->refresh_rate != 0xff) { 152 while (loop->refresh_rate != 0xff) {
153 if ((check_sync) && 153 if ((check_sync) &&
@@ -227,7 +227,7 @@ static void ast_set_std_reg(struct drm_crtc *crtc, struct drm_display_mode *mode
227 struct ast_vbios_mode_info *vbios_mode) 227 struct ast_vbios_mode_info *vbios_mode)
228{ 228{
229 struct ast_private *ast = crtc->dev->dev_private; 229 struct ast_private *ast = crtc->dev->dev_private;
230 struct ast_vbios_stdtable *stdtable; 230 const struct ast_vbios_stdtable *stdtable;
231 u32 i; 231 u32 i;
232 u8 jreg; 232 u8 jreg;
233 233
@@ -273,7 +273,11 @@ static void ast_set_crtc_reg(struct drm_crtc *crtc, struct drm_display_mode *mod
273{ 273{
274 struct ast_private *ast = crtc->dev->dev_private; 274 struct ast_private *ast = crtc->dev->dev_private;
275 u8 jreg05 = 0, jreg07 = 0, jreg09 = 0, jregAC = 0, jregAD = 0, jregAE = 0; 275 u8 jreg05 = 0, jreg07 = 0, jreg09 = 0, jregAC = 0, jregAD = 0, jregAE = 0;
276 u16 temp; 276 u16 temp, precache = 0;
277
278 if ((ast->chip == AST2500) &&
279 (vbios_mode->enh_table->flags & AST2500PreCatchCRT))
280 precache = 40;
277 281
278 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00); 282 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00);
279 283
@@ -299,12 +303,12 @@ static void ast_set_crtc_reg(struct drm_crtc *crtc, struct drm_display_mode *mod
299 jregAD |= 0x01; /* HBE D[5] */ 303 jregAD |= 0x01; /* HBE D[5] */
300 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x03, 0xE0, (temp & 0x1f)); 304 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x03, 0xE0, (temp & 0x1f));
301 305
302 temp = (mode->crtc_hsync_start >> 3) - 1; 306 temp = ((mode->crtc_hsync_start-precache) >> 3) - 1;
303 if (temp & 0x100) 307 if (temp & 0x100)
304 jregAC |= 0x40; /* HRS D[5] */ 308 jregAC |= 0x40; /* HRS D[5] */
305 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x04, 0x00, temp); 309 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x04, 0x00, temp);
306 310
307 temp = ((mode->crtc_hsync_end >> 3) - 1) & 0x3f; 311 temp = (((mode->crtc_hsync_end-precache) >> 3) - 1) & 0x3f;
308 if (temp & 0x20) 312 if (temp & 0x20)
309 jregAD |= 0x04; /* HRE D[5] */ 313 jregAD |= 0x04; /* HRE D[5] */
310 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05)); 314 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05));
@@ -365,6 +369,11 @@ static void ast_set_crtc_reg(struct drm_crtc *crtc, struct drm_display_mode *mod
365 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x09, 0xdf, jreg09); 369 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x09, 0xdf, jreg09);
366 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAE, 0x00, (jregAE | 0x80)); 370 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAE, 0x00, (jregAE | 0x80));
367 371
372 if (precache)
373 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x80);
374 else
375 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x00);
376
368 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x80); 377 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x80);
369} 378}
370 379
@@ -384,14 +393,18 @@ static void ast_set_dclk_reg(struct drm_device *dev, struct drm_display_mode *mo
384 struct ast_vbios_mode_info *vbios_mode) 393 struct ast_vbios_mode_info *vbios_mode)
385{ 394{
386 struct ast_private *ast = dev->dev_private; 395 struct ast_private *ast = dev->dev_private;
387 struct ast_vbios_dclk_info *clk_info; 396 const struct ast_vbios_dclk_info *clk_info;
388 397
389 clk_info = &dclk_table[vbios_mode->enh_table->dclk_index]; 398 if (ast->chip == AST2500)
399 clk_info = &dclk_table_ast2500[vbios_mode->enh_table->dclk_index];
400 else
401 clk_info = &dclk_table[vbios_mode->enh_table->dclk_index];
390 402
391 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc0, 0x00, clk_info->param1); 403 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc0, 0x00, clk_info->param1);
392 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc1, 0x00, clk_info->param2); 404 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc1, 0x00, clk_info->param2);
393 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xbb, 0x0f, 405 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xbb, 0x0f,
394 (clk_info->param3 & 0x80) | ((clk_info->param3 & 0x3) << 4)); 406 (clk_info->param3 & 0xc0) |
407 ((clk_info->param3 & 0x3) << 4));
395} 408}
396 409
397static void ast_set_ext_reg(struct drm_crtc *crtc, struct drm_display_mode *mode, 410static void ast_set_ext_reg(struct drm_crtc *crtc, struct drm_display_mode *mode,
@@ -425,7 +438,8 @@ static void ast_set_ext_reg(struct drm_crtc *crtc, struct drm_display_mode *mode
425 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa8, 0xfd, jregA8); 438 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa8, 0xfd, jregA8);
426 439
427 /* Set Threshold */ 440 /* Set Threshold */
428 if (ast->chip == AST2300 || ast->chip == AST2400) { 441 if (ast->chip == AST2300 || ast->chip == AST2400 ||
442 ast->chip == AST2500) {
429 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x78); 443 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x78);
430 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x60); 444 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x60);
431 } else if (ast->chip == AST2100 || 445 } else if (ast->chip == AST2100 ||
@@ -800,7 +814,9 @@ static int ast_mode_valid(struct drm_connector *connector,
800 if ((mode->hdisplay == 1600) && (mode->vdisplay == 900)) 814 if ((mode->hdisplay == 1600) && (mode->vdisplay == 900))
801 return MODE_OK; 815 return MODE_OK;
802 816
803 if ((ast->chip == AST2100) || (ast->chip == AST2200) || (ast->chip == AST2300) || (ast->chip == AST2400) || (ast->chip == AST1180)) { 817 if ((ast->chip == AST2100) || (ast->chip == AST2200) ||
818 (ast->chip == AST2300) || (ast->chip == AST2400) ||
819 (ast->chip == AST2500) || (ast->chip == AST1180)) {
804 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1080)) 820 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1080))
805 return MODE_OK; 821 return MODE_OK;
806 822
diff --git a/drivers/gpu/drm/ast/ast_post.c b/drivers/gpu/drm/ast/ast_post.c
index 5331ee1df086..f7d421359d56 100644
--- a/drivers/gpu/drm/ast/ast_post.c
+++ b/drivers/gpu/drm/ast/ast_post.c
@@ -31,7 +31,8 @@
31 31
32#include "ast_dram_tables.h" 32#include "ast_dram_tables.h"
33 33
34static void ast_init_dram_2300(struct drm_device *dev); 34static void ast_post_chip_2300(struct drm_device *dev);
35static void ast_post_chip_2500(struct drm_device *dev);
35 36
36void ast_enable_vga(struct drm_device *dev) 37void ast_enable_vga(struct drm_device *dev)
37{ 38{
@@ -58,13 +59,9 @@ bool ast_is_vga_enabled(struct drm_device *dev)
58 /* TODO 1180 */ 59 /* TODO 1180 */
59 } else { 60 } else {
60 ch = ast_io_read8(ast, AST_IO_VGA_ENABLE_PORT); 61 ch = ast_io_read8(ast, AST_IO_VGA_ENABLE_PORT);
61 if (ch) { 62 return !!(ch & 0x01);
62 ast_open_key(ast);
63 ch = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff);
64 return ch & 0x04;
65 }
66 } 63 }
67 return 0; 64 return false;
68} 65}
69 66
70static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff }; 67static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff };
@@ -79,10 +76,11 @@ ast_set_def_ext_reg(struct drm_device *dev)
79 const u8 *ext_reg_info; 76 const u8 *ext_reg_info;
80 77
81 /* reset scratch */ 78 /* reset scratch */
82 for (i = 0x81; i <= 0x8f; i++) 79 for (i = 0x81; i <= 0x9f; i++)
83 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, 0x00); 80 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, 0x00);
84 81
85 if (ast->chip == AST2300 || ast->chip == AST2400) { 82 if (ast->chip == AST2300 || ast->chip == AST2400 ||
83 ast->chip == AST2500) {
86 if (dev->pdev->revision >= 0x20) 84 if (dev->pdev->revision >= 0x20)
87 ext_reg_info = extreginfo_ast2300; 85 ext_reg_info = extreginfo_ast2300;
88 else 86 else
@@ -106,7 +104,8 @@ ast_set_def_ext_reg(struct drm_device *dev)
106 104
107 /* Enable RAMDAC for A1 */ 105 /* Enable RAMDAC for A1 */
108 reg = 0x04; 106 reg = 0x04;
109 if (ast->chip == AST2300 || ast->chip == AST2400) 107 if (ast->chip == AST2300 || ast->chip == AST2400 ||
108 ast->chip == AST2500)
110 reg |= 0x20; 109 reg |= 0x20;
111 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff, reg); 110 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff, reg);
112} 111}
@@ -375,21 +374,20 @@ void ast_post_gpu(struct drm_device *dev)
375 pci_write_config_dword(ast->dev->pdev, 0x04, reg); 374 pci_write_config_dword(ast->dev->pdev, 0x04, reg);
376 375
377 ast_enable_vga(dev); 376 ast_enable_vga(dev);
378 ast_enable_mmio(dev);
379 ast_open_key(ast); 377 ast_open_key(ast);
378 ast_enable_mmio(dev);
380 ast_set_def_ext_reg(dev); 379 ast_set_def_ext_reg(dev);
381 380
382 if (ast->DisableP2A == false) 381 if (ast->config_mode == ast_use_p2a) {
383 { 382 if (ast->chip == AST2500)
384 if (ast->chip == AST2300 || ast->chip == AST2400) 383 ast_post_chip_2500(dev);
385 ast_init_dram_2300(dev); 384 else if (ast->chip == AST2300 || ast->chip == AST2400)
385 ast_post_chip_2300(dev);
386 else 386 else
387 ast_init_dram_reg(dev); 387 ast_init_dram_reg(dev);
388 388
389 ast_init_3rdtx(dev); 389 ast_init_3rdtx(dev);
390 } 390 } else {
391 else
392 {
393 if (ast->tx_chip_type != AST_TX_NONE) 391 if (ast->tx_chip_type != AST_TX_NONE)
394 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80); /* Enable DVO */ 392 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80); /* Enable DVO */
395 } 393 }
@@ -448,85 +446,70 @@ static const u32 pattern[8] = {
448 0x7C61D253 446 0x7C61D253
449}; 447};
450 448
451static int mmc_test_burst(struct ast_private *ast, u32 datagen) 449static bool mmc_test(struct ast_private *ast, u32 datagen, u8 test_ctl)
452{ 450{
453 u32 data, timeout; 451 u32 data, timeout;
454 452
455 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); 453 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
456 ast_moutdwm(ast, 0x1e6e0070, 0x000000c1 | (datagen << 3)); 454 ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl);
457 timeout = 0; 455 timeout = 0;
458 do { 456 do {
459 data = ast_mindwm(ast, 0x1e6e0070) & 0x3000; 457 data = ast_mindwm(ast, 0x1e6e0070) & 0x3000;
460 if (data & 0x2000) { 458 if (data & 0x2000)
461 return 0; 459 return false;
462 }
463 if (++timeout > TIMEOUT) { 460 if (++timeout > TIMEOUT) {
464 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); 461 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
465 return 0; 462 return false;
466 } 463 }
467 } while (!data); 464 } while (!data);
468 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); 465 ast_moutdwm(ast, 0x1e6e0070, 0x0);
469 return 1; 466 return true;
470} 467}
471 468
472static int mmc_test_burst2(struct ast_private *ast, u32 datagen) 469static u32 mmc_test2(struct ast_private *ast, u32 datagen, u8 test_ctl)
473{ 470{
474 u32 data, timeout; 471 u32 data, timeout;
475 472
476 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); 473 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
477 ast_moutdwm(ast, 0x1e6e0070, 0x00000041 | (datagen << 3)); 474 ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl);
478 timeout = 0; 475 timeout = 0;
479 do { 476 do {
480 data = ast_mindwm(ast, 0x1e6e0070) & 0x1000; 477 data = ast_mindwm(ast, 0x1e6e0070) & 0x1000;
481 if (++timeout > TIMEOUT) { 478 if (++timeout > TIMEOUT) {
482 ast_moutdwm(ast, 0x1e6e0070, 0x0); 479 ast_moutdwm(ast, 0x1e6e0070, 0x0);
483 return -1; 480 return 0xffffffff;
484 } 481 }
485 } while (!data); 482 } while (!data);
486 data = ast_mindwm(ast, 0x1e6e0078); 483 data = ast_mindwm(ast, 0x1e6e0078);
487 data = (data | (data >> 16)) & 0xffff; 484 data = (data | (data >> 16)) & 0xffff;
488 ast_moutdwm(ast, 0x1e6e0070, 0x0); 485 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
489 return data; 486 return data;
490} 487}
491 488
492static int mmc_test_single(struct ast_private *ast, u32 datagen) 489
490static bool mmc_test_burst(struct ast_private *ast, u32 datagen)
493{ 491{
494 u32 data, timeout; 492 return mmc_test(ast, datagen, 0xc1);
493}
495 494
496 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); 495static u32 mmc_test_burst2(struct ast_private *ast, u32 datagen)
497 ast_moutdwm(ast, 0x1e6e0070, 0x000000c5 | (datagen << 3)); 496{
498 timeout = 0; 497 return mmc_test2(ast, datagen, 0x41);
499 do {
500 data = ast_mindwm(ast, 0x1e6e0070) & 0x3000;
501 if (data & 0x2000)
502 return 0;
503 if (++timeout > TIMEOUT) {
504 ast_moutdwm(ast, 0x1e6e0070, 0x0);
505 return 0;
506 }
507 } while (!data);
508 ast_moutdwm(ast, 0x1e6e0070, 0x0);
509 return 1;
510} 498}
511 499
512static int mmc_test_single2(struct ast_private *ast, u32 datagen) 500static bool mmc_test_single(struct ast_private *ast, u32 datagen)
513{ 501{
514 u32 data, timeout; 502 return mmc_test(ast, datagen, 0xc5);
503}
515 504
516 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); 505static u32 mmc_test_single2(struct ast_private *ast, u32 datagen)
517 ast_moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3)); 506{
518 timeout = 0; 507 return mmc_test2(ast, datagen, 0x05);
519 do { 508}
520 data = ast_mindwm(ast, 0x1e6e0070) & 0x1000; 509
521 if (++timeout > TIMEOUT) { 510static bool mmc_test_single_2500(struct ast_private *ast, u32 datagen)
522 ast_moutdwm(ast, 0x1e6e0070, 0x0); 511{
523 return -1; 512 return mmc_test(ast, datagen, 0x85);
524 }
525 } while (!data);
526 data = ast_mindwm(ast, 0x1e6e0078);
527 data = (data | (data >> 16)) & 0xffff;
528 ast_moutdwm(ast, 0x1e6e0070, 0x0);
529 return data;
530} 513}
531 514
532static int cbr_test(struct ast_private *ast) 515static int cbr_test(struct ast_private *ast)
@@ -604,16 +587,16 @@ static u32 cbr_scan2(struct ast_private *ast)
604 return data2; 587 return data2;
605} 588}
606 589
607static u32 cbr_test3(struct ast_private *ast) 590static bool cbr_test3(struct ast_private *ast)
608{ 591{
609 if (!mmc_test_burst(ast, 0)) 592 if (!mmc_test_burst(ast, 0))
610 return 0; 593 return false;
611 if (!mmc_test_single(ast, 0)) 594 if (!mmc_test_single(ast, 0))
612 return 0; 595 return false;
613 return 1; 596 return true;
614} 597}
615 598
616static u32 cbr_scan3(struct ast_private *ast) 599static bool cbr_scan3(struct ast_private *ast)
617{ 600{
618 u32 patcnt, loop; 601 u32 patcnt, loop;
619 602
@@ -624,9 +607,9 @@ static u32 cbr_scan3(struct ast_private *ast)
624 break; 607 break;
625 } 608 }
626 if (loop == 2) 609 if (loop == 2)
627 return 0; 610 return false;
628 } 611 }
629 return 1; 612 return true;
630} 613}
631 614
632static bool finetuneDQI_L(struct ast_private *ast, struct ast2300_dram_param *param) 615static bool finetuneDQI_L(struct ast_private *ast, struct ast2300_dram_param *param)
@@ -1612,7 +1595,7 @@ ddr2_init_start:
1612 1595
1613} 1596}
1614 1597
1615static void ast_init_dram_2300(struct drm_device *dev) 1598static void ast_post_chip_2300(struct drm_device *dev)
1616{ 1599{
1617 struct ast_private *ast = dev->dev_private; 1600 struct ast_private *ast = dev->dev_private;
1618 struct ast2300_dram_param param; 1601 struct ast2300_dram_param param;
@@ -1638,12 +1621,44 @@ static void ast_init_dram_2300(struct drm_device *dev)
1638 temp |= 0x73; 1621 temp |= 0x73;
1639 ast_write32(ast, 0x12008, temp); 1622 ast_write32(ast, 0x12008, temp);
1640 1623
1624 param.dram_freq = 396;
1641 param.dram_type = AST_DDR3; 1625 param.dram_type = AST_DDR3;
1626 temp = ast_mindwm(ast, 0x1e6e2070);
1642 if (temp & 0x01000000) 1627 if (temp & 0x01000000)
1643 param.dram_type = AST_DDR2; 1628 param.dram_type = AST_DDR2;
1644 param.dram_chipid = ast->dram_type; 1629 switch (temp & 0x18000000) {
1645 param.dram_freq = ast->mclk; 1630 case 0:
1646 param.vram_size = ast->vram_size; 1631 param.dram_chipid = AST_DRAM_512Mx16;
1632 break;
1633 default:
1634 case 0x08000000:
1635 param.dram_chipid = AST_DRAM_1Gx16;
1636 break;
1637 case 0x10000000:
1638 param.dram_chipid = AST_DRAM_2Gx16;
1639 break;
1640 case 0x18000000:
1641 param.dram_chipid = AST_DRAM_4Gx16;
1642 break;
1643 }
1644 switch (temp & 0x0c) {
1645 default:
1646 case 0x00:
1647 param.vram_size = AST_VIDMEM_SIZE_8M;
1648 break;
1649
1650 case 0x04:
1651 param.vram_size = AST_VIDMEM_SIZE_16M;
1652 break;
1653
1654 case 0x08:
1655 param.vram_size = AST_VIDMEM_SIZE_32M;
1656 break;
1657
1658 case 0x0c:
1659 param.vram_size = AST_VIDMEM_SIZE_64M;
1660 break;
1661 }
1647 1662
1648 if (param.dram_type == AST_DDR3) { 1663 if (param.dram_type == AST_DDR3) {
1649 get_ddr3_info(ast, &param); 1664 get_ddr3_info(ast, &param);
@@ -1663,3 +1678,404 @@ static void ast_init_dram_2300(struct drm_device *dev)
1663 } while ((reg & 0x40) == 0); 1678 } while ((reg & 0x40) == 0);
1664} 1679}
1665 1680
1681static bool cbr_test_2500(struct ast_private *ast)
1682{
1683 ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
1684 ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
1685 if (!mmc_test_burst(ast, 0))
1686 return false;
1687 if (!mmc_test_single_2500(ast, 0))
1688 return false;
1689 return true;
1690}
1691
1692static bool ddr_test_2500(struct ast_private *ast)
1693{
1694 ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
1695 ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
1696 if (!mmc_test_burst(ast, 0))
1697 return false;
1698 if (!mmc_test_burst(ast, 1))
1699 return false;
1700 if (!mmc_test_burst(ast, 2))
1701 return false;
1702 if (!mmc_test_burst(ast, 3))
1703 return false;
1704 if (!mmc_test_single_2500(ast, 0))
1705 return false;
1706 return true;
1707}
1708
1709static void ddr_init_common_2500(struct ast_private *ast)
1710{
1711 ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
1712 ast_moutdwm(ast, 0x1E6E0008, 0x2003000F);
1713 ast_moutdwm(ast, 0x1E6E0038, 0x00000FFF);
1714 ast_moutdwm(ast, 0x1E6E0040, 0x88448844);
1715 ast_moutdwm(ast, 0x1E6E0044, 0x24422288);
1716 ast_moutdwm(ast, 0x1E6E0048, 0x22222222);
1717 ast_moutdwm(ast, 0x1E6E004C, 0x22222222);
1718 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1719 ast_moutdwm(ast, 0x1E6E0208, 0x00000000);
1720 ast_moutdwm(ast, 0x1E6E0218, 0x00000000);
1721 ast_moutdwm(ast, 0x1E6E0220, 0x00000000);
1722 ast_moutdwm(ast, 0x1E6E0228, 0x00000000);
1723 ast_moutdwm(ast, 0x1E6E0230, 0x00000000);
1724 ast_moutdwm(ast, 0x1E6E02A8, 0x00000000);
1725 ast_moutdwm(ast, 0x1E6E02B0, 0x00000000);
1726 ast_moutdwm(ast, 0x1E6E0240, 0x86000000);
1727 ast_moutdwm(ast, 0x1E6E0244, 0x00008600);
1728 ast_moutdwm(ast, 0x1E6E0248, 0x80000000);
1729 ast_moutdwm(ast, 0x1E6E024C, 0x80808080);
1730}
1731
1732static void ddr_phy_init_2500(struct ast_private *ast)
1733{
1734 u32 data, pass, timecnt;
1735
1736 pass = 0;
1737 ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
1738 while (!pass) {
1739 for (timecnt = 0; timecnt < TIMEOUT; timecnt++) {
1740 data = ast_mindwm(ast, 0x1E6E0060) & 0x1;
1741 if (!data)
1742 break;
1743 }
1744 if (timecnt != TIMEOUT) {
1745 data = ast_mindwm(ast, 0x1E6E0300) & 0x000A0000;
1746 if (!data)
1747 pass = 1;
1748 }
1749 if (!pass) {
1750 ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1751 udelay(10); /* delay 10 us */
1752 ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
1753 }
1754 }
1755
1756 ast_moutdwm(ast, 0x1E6E0060, 0x00000006);
1757}
1758
1759/*
1760 * Check DRAM Size
1761 * 1Gb : 0x80000000 ~ 0x87FFFFFF
1762 * 2Gb : 0x80000000 ~ 0x8FFFFFFF
1763 * 4Gb : 0x80000000 ~ 0x9FFFFFFF
1764 * 8Gb : 0x80000000 ~ 0xBFFFFFFF
1765 */
1766static void check_dram_size_2500(struct ast_private *ast, u32 tRFC)
1767{
1768 u32 reg_04, reg_14;
1769
1770 reg_04 = ast_mindwm(ast, 0x1E6E0004) & 0xfffffffc;
1771 reg_14 = ast_mindwm(ast, 0x1E6E0014) & 0xffffff00;
1772
1773 ast_moutdwm(ast, 0xA0100000, 0x41424344);
1774 ast_moutdwm(ast, 0x90100000, 0x35363738);
1775 ast_moutdwm(ast, 0x88100000, 0x292A2B2C);
1776 ast_moutdwm(ast, 0x80100000, 0x1D1E1F10);
1777
1778 /* Check 8Gbit */
1779 if (ast_mindwm(ast, 0xA0100000) == 0x41424344) {
1780 reg_04 |= 0x03;
1781 reg_14 |= (tRFC >> 24) & 0xFF;
1782 /* Check 4Gbit */
1783 } else if (ast_mindwm(ast, 0x90100000) == 0x35363738) {
1784 reg_04 |= 0x02;
1785 reg_14 |= (tRFC >> 16) & 0xFF;
1786 /* Check 2Gbit */
1787 } else if (ast_mindwm(ast, 0x88100000) == 0x292A2B2C) {
1788 reg_04 |= 0x01;
1789 reg_14 |= (tRFC >> 8) & 0xFF;
1790 } else {
1791 reg_14 |= tRFC & 0xFF;
1792 }
1793 ast_moutdwm(ast, 0x1E6E0004, reg_04);
1794 ast_moutdwm(ast, 0x1E6E0014, reg_14);
1795}
1796
1797static void enable_cache_2500(struct ast_private *ast)
1798{
1799 u32 reg_04, data;
1800
1801 reg_04 = ast_mindwm(ast, 0x1E6E0004);
1802 ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x1000);
1803
1804 do
1805 data = ast_mindwm(ast, 0x1E6E0004);
1806 while (!(data & 0x80000));
1807 ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x400);
1808}
1809
1810static void set_mpll_2500(struct ast_private *ast)
1811{
1812 u32 addr, data, param;
1813
1814 /* Reset MMC */
1815 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1816 ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
1817 for (addr = 0x1e6e0004; addr < 0x1e6e0090;) {
1818 ast_moutdwm(ast, addr, 0x0);
1819 addr += 4;
1820 }
1821 ast_moutdwm(ast, 0x1E6E0034, 0x00020000);
1822
1823 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
1824 data = ast_mindwm(ast, 0x1E6E2070) & 0x00800000;
1825 if (data) {
1826 /* CLKIN = 25MHz */
1827 param = 0x930023E0;
1828 ast_moutdwm(ast, 0x1E6E2160, 0x00011320);
1829 } else {
1830 /* CLKIN = 24MHz */
1831 param = 0x93002400;
1832 }
1833 ast_moutdwm(ast, 0x1E6E2020, param);
1834 udelay(100);
1835}
1836
1837static void reset_mmc_2500(struct ast_private *ast)
1838{
1839 ast_moutdwm(ast, 0x1E78505C, 0x00000004);
1840 ast_moutdwm(ast, 0x1E785044, 0x00000001);
1841 ast_moutdwm(ast, 0x1E785048, 0x00004755);
1842 ast_moutdwm(ast, 0x1E78504C, 0x00000013);
1843 mdelay(100);
1844 ast_moutdwm(ast, 0x1E785054, 0x00000077);
1845 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1846}
1847
1848static void ddr3_init_2500(struct ast_private *ast, const u32 *ddr_table)
1849{
1850
1851 ast_moutdwm(ast, 0x1E6E0004, 0x00000303);
1852 ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
1853 ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
1854 ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
1855 ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */
1856 ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */
1857 ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
1858 ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */
1859
1860 /* DDR PHY Setting */
1861 ast_moutdwm(ast, 0x1E6E0200, 0x02492AAE);
1862 ast_moutdwm(ast, 0x1E6E0204, 0x00001001);
1863 ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
1864 ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
1865 ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
1866 ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
1867 ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
1868 ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
1869 ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
1870 ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
1871 ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
1872 ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
1873 ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
1874 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006);
1875
1876 /* Controller Setting */
1877 ast_moutdwm(ast, 0x1E6E0034, 0x00020091);
1878
1879 /* Wait DDR PHY init done */
1880 ddr_phy_init_2500(ast);
1881
1882 ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
1883 ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
1884 ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
1885
1886 check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
1887 enable_cache_2500(ast);
1888 ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
1889 ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
1890}
1891
1892static void ddr4_init_2500(struct ast_private *ast, const u32 *ddr_table)
1893{
1894 u32 data, data2, pass, retrycnt;
1895 u32 ddr_vref, phy_vref;
1896 u32 min_ddr_vref = 0, min_phy_vref = 0;
1897 u32 max_ddr_vref = 0, max_phy_vref = 0;
1898
1899 ast_moutdwm(ast, 0x1E6E0004, 0x00000313);
1900 ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
1901 ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
1902 ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
1903 ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */
1904 ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */
1905 ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
1906 ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */
1907
1908 /* DDR PHY Setting */
1909 ast_moutdwm(ast, 0x1E6E0200, 0x42492AAE);
1910 ast_moutdwm(ast, 0x1E6E0204, 0x09002000);
1911 ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
1912 ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
1913 ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
1914 ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
1915 ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
1916 ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
1917 ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
1918 ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
1919 ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
1920 ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
1921 ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
1922 ast_moutdwm(ast, 0x1E6E02C4, 0x3C183C3C);
1923 ast_moutdwm(ast, 0x1E6E02C8, 0x00631E0E);
1924
1925 /* Controller Setting */
1926 ast_moutdwm(ast, 0x1E6E0034, 0x0001A991);
1927
1928 /* Train PHY Vref first */
1929 pass = 0;
1930
1931 for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) {
1932 max_phy_vref = 0x0;
1933 pass = 0;
1934 ast_moutdwm(ast, 0x1E6E02C0, 0x00001C06);
1935 for (phy_vref = 0x40; phy_vref < 0x80; phy_vref++) {
1936 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1937 ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1938 ast_moutdwm(ast, 0x1E6E02CC, phy_vref | (phy_vref << 8));
1939 /* Fire DFI Init */
1940 ddr_phy_init_2500(ast);
1941 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1942 if (cbr_test_2500(ast)) {
1943 pass++;
1944 data = ast_mindwm(ast, 0x1E6E03D0);
1945 data2 = data >> 8;
1946 data = data & 0xff;
1947 if (data > data2)
1948 data = data2;
1949 if (max_phy_vref < data) {
1950 max_phy_vref = data;
1951 min_phy_vref = phy_vref;
1952 }
1953 } else if (pass > 0)
1954 break;
1955 }
1956 }
1957 ast_moutdwm(ast, 0x1E6E02CC, min_phy_vref | (min_phy_vref << 8));
1958
1959 /* Train DDR Vref next */
1960 pass = 0;
1961
1962 for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) {
1963 min_ddr_vref = 0xFF;
1964 max_ddr_vref = 0x0;
1965 pass = 0;
1966 for (ddr_vref = 0x00; ddr_vref < 0x40; ddr_vref++) {
1967 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1968 ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1969 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
1970 /* Fire DFI Init */
1971 ddr_phy_init_2500(ast);
1972 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1973 if (cbr_test_2500(ast)) {
1974 pass++;
1975 if (min_ddr_vref > ddr_vref)
1976 min_ddr_vref = ddr_vref;
1977 if (max_ddr_vref < ddr_vref)
1978 max_ddr_vref = ddr_vref;
1979 } else if (pass != 0)
1980 break;
1981 }
1982 }
1983
1984 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1985 ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1986 ddr_vref = (min_ddr_vref + max_ddr_vref + 1) >> 1;
1987 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
1988
1989 /* Wait DDR PHY init done */
1990 ddr_phy_init_2500(ast);
1991
1992 ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
1993 ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
1994 ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
1995
1996 check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
1997 enable_cache_2500(ast);
1998 ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
1999 ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
2000}
2001
2002static bool ast_dram_init_2500(struct ast_private *ast)
2003{
2004 u32 data;
2005 u32 max_tries = 5;
2006
2007 do {
2008 if (max_tries-- == 0)
2009 return false;
2010 set_mpll_2500(ast);
2011 reset_mmc_2500(ast);
2012 ddr_init_common_2500(ast);
2013
2014 data = ast_mindwm(ast, 0x1E6E2070);
2015 if (data & 0x01000000)
2016 ddr4_init_2500(ast, ast2500_ddr4_1600_timing_table);
2017 else
2018 ddr3_init_2500(ast, ast2500_ddr3_1600_timing_table);
2019 } while (!ddr_test_2500(ast));
2020
2021 ast_moutdwm(ast, 0x1E6E2040, ast_mindwm(ast, 0x1E6E2040) | 0x41);
2022
2023 /* Patch code */
2024 data = ast_mindwm(ast, 0x1E6E200C) & 0xF9FFFFFF;
2025 ast_moutdwm(ast, 0x1E6E200C, data | 0x10000000);
2026
2027 return true;
2028}
2029
2030void ast_post_chip_2500(struct drm_device *dev)
2031{
2032 struct ast_private *ast = dev->dev_private;
2033 u32 temp;
2034 u8 reg;
2035
2036 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
2037 if ((reg & 0x80) == 0) {/* vga only */
2038 /* Clear bus lock condition */
2039 ast_moutdwm(ast, 0x1e600000, 0xAEED1A03);
2040 ast_moutdwm(ast, 0x1e600084, 0x00010000);
2041 ast_moutdwm(ast, 0x1e600088, 0x00000000);
2042 ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8);
2043 ast_write32(ast, 0xf004, 0x1e6e0000);
2044 ast_write32(ast, 0xf000, 0x1);
2045 ast_write32(ast, 0x12000, 0x1688a8a8);
2046 while (ast_read32(ast, 0x12000) != 0x1)
2047 ;
2048
2049 ast_write32(ast, 0x10000, 0xfc600309);
2050 while (ast_read32(ast, 0x10000) != 0x1)
2051 ;
2052
2053 /* Slow down CPU/AHB CLK in VGA only mode */
2054 temp = ast_read32(ast, 0x12008);
2055 temp |= 0x73;
2056 ast_write32(ast, 0x12008, temp);
2057
2058 /* Reset USB port to patch USB unknown device issue */
2059 ast_moutdwm(ast, 0x1e6e2090, 0x20000000);
2060 temp = ast_mindwm(ast, 0x1e6e2094);
2061 temp |= 0x00004000;
2062 ast_moutdwm(ast, 0x1e6e2094, temp);
2063 temp = ast_mindwm(ast, 0x1e6e2070);
2064 if (temp & 0x00800000) {
2065 ast_moutdwm(ast, 0x1e6e207c, 0x00800000);
2066 mdelay(100);
2067 ast_moutdwm(ast, 0x1e6e2070, 0x00800000);
2068 }
2069
2070 if (!ast_dram_init_2500(ast))
2071 DRM_ERROR("DRAM init failed !\n");
2072
2073 temp = ast_mindwm(ast, 0x1e6e2040);
2074 ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);
2075 }
2076
2077 /* wait ready */
2078 do {
2079 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
2080 } while ((reg & 0x40) == 0);
2081}
diff --git a/drivers/gpu/drm/ast/ast_tables.h b/drivers/gpu/drm/ast/ast_tables.h
index 3608d5aa7451..5f4c2e833a65 100644
--- a/drivers/gpu/drm/ast/ast_tables.h
+++ b/drivers/gpu/drm/ast/ast_tables.h
@@ -47,6 +47,7 @@
47#define SyncPN (PVSync | NHSync) 47#define SyncPN (PVSync | NHSync)
48#define SyncNP (NVSync | PHSync) 48#define SyncNP (NVSync | PHSync)
49#define SyncNN (NVSync | NHSync) 49#define SyncNN (NVSync | NHSync)
50#define AST2500PreCatchCRT 0x00004000
50 51
51/* DCLK Index */ 52/* DCLK Index */
52#define VCLK25_175 0x00 53#define VCLK25_175 0x00
@@ -78,37 +79,67 @@
78#define VCLK97_75 0x19 79#define VCLK97_75 0x19
79#define VCLK118_25 0x1A 80#define VCLK118_25 0x1A
80 81
81static struct ast_vbios_dclk_info dclk_table[] = { 82static const struct ast_vbios_dclk_info dclk_table[] = {
82 {0x2C, 0xE7, 0x03}, /* 00: VCLK25_175 */ 83 {0x2C, 0xE7, 0x03}, /* 00: VCLK25_175 */
83 {0x95, 0x62, 0x03}, /* 01: VCLK28_322 */ 84 {0x95, 0x62, 0x03}, /* 01: VCLK28_322 */
84 {0x67, 0x63, 0x01}, /* 02: VCLK31_5 */ 85 {0x67, 0x63, 0x01}, /* 02: VCLK31_5 */
85 {0x76, 0x63, 0x01}, /* 03: VCLK36 */ 86 {0x76, 0x63, 0x01}, /* 03: VCLK36 */
86 {0xEE, 0x67, 0x01}, /* 04: VCLK40 */ 87 {0xEE, 0x67, 0x01}, /* 04: VCLK40 */
87 {0x82, 0x62, 0x01}, /* 05: VCLK49_5 */ 88 {0x82, 0x62, 0x01}, /* 05: VCLK49_5 */
88 {0xC6, 0x64, 0x01}, /* 06: VCLK50 */ 89 {0xC6, 0x64, 0x01}, /* 06: VCLK50 */
89 {0x94, 0x62, 0x01}, /* 07: VCLK56_25 */ 90 {0x94, 0x62, 0x01}, /* 07: VCLK56_25 */
90 {0x80, 0x64, 0x00}, /* 08: VCLK65 */ 91 {0x80, 0x64, 0x00}, /* 08: VCLK65 */
91 {0x7B, 0x63, 0x00}, /* 09: VCLK75 */ 92 {0x7B, 0x63, 0x00}, /* 09: VCLK75 */
92 {0x67, 0x62, 0x00}, /* 0A: VCLK78_75 */ 93 {0x67, 0x62, 0x00}, /* 0A: VCLK78_75 */
93 {0x7C, 0x62, 0x00}, /* 0B: VCLK94_5 */ 94 {0x7C, 0x62, 0x00}, /* 0B: VCLK94_5 */
94 {0x8E, 0x62, 0x00}, /* 0C: VCLK108 */ 95 {0x8E, 0x62, 0x00}, /* 0C: VCLK108 */
95 {0x85, 0x24, 0x00}, /* 0D: VCLK135 */ 96 {0x85, 0x24, 0x00}, /* 0D: VCLK135 */
96 {0x67, 0x22, 0x00}, /* 0E: VCLK157_5 */ 97 {0x67, 0x22, 0x00}, /* 0E: VCLK157_5 */
97 {0x6A, 0x22, 0x00}, /* 0F: VCLK162 */ 98 {0x6A, 0x22, 0x00}, /* 0F: VCLK162 */
98 {0x4d, 0x4c, 0x80}, /* 10: VCLK154 */ 99 {0x4d, 0x4c, 0x80}, /* 10: VCLK154 */
99 {0xa7, 0x78, 0x80}, /* 11: VCLK83.5 */ 100 {0xa7, 0x78, 0x80}, /* 11: VCLK83.5 */
100 {0x28, 0x49, 0x80}, /* 12: VCLK106.5 */ 101 {0x28, 0x49, 0x80}, /* 12: VCLK106.5 */
101 {0x37, 0x49, 0x80}, /* 13: VCLK146.25 */ 102 {0x37, 0x49, 0x80}, /* 13: VCLK146.25 */
102 {0x1f, 0x45, 0x80}, /* 14: VCLK148.5 */ 103 {0x1f, 0x45, 0x80}, /* 14: VCLK148.5 */
103 {0x47, 0x6c, 0x80}, /* 15: VCLK71 */ 104 {0x47, 0x6c, 0x80}, /* 15: VCLK71 */
104 {0x25, 0x65, 0x80}, /* 16: VCLK88.75 */ 105 {0x25, 0x65, 0x80}, /* 16: VCLK88.75 */
105 {0x77, 0x58, 0x80}, /* 17: VCLK119 */ 106 {0x77, 0x58, 0x80}, /* 17: VCLK119 */
106 {0x32, 0x67, 0x80}, /* 18: VCLK85_5 */ 107 {0x32, 0x67, 0x80}, /* 18: VCLK85_5 */
107 {0x6a, 0x6d, 0x80}, /* 19: VCLK97_75 */ 108 {0x6a, 0x6d, 0x80}, /* 19: VCLK97_75 */
108 {0x3b, 0x2c, 0x81}, /* 1A: VCLK118_25 */ 109 {0x3b, 0x2c, 0x81}, /* 1A: VCLK118_25 */
109}; 110};
110 111
111static struct ast_vbios_stdtable vbios_stdtable[] = { 112static const struct ast_vbios_dclk_info dclk_table_ast2500[] = {
113 {0x2C, 0xE7, 0x03}, /* 00: VCLK25_175 */
114 {0x95, 0x62, 0x03}, /* 01: VCLK28_322 */
115 {0x67, 0x63, 0x01}, /* 02: VCLK31_5 */
116 {0x76, 0x63, 0x01}, /* 03: VCLK36 */
117 {0xEE, 0x67, 0x01}, /* 04: VCLK40 */
118 {0x82, 0x62, 0x01}, /* 05: VCLK49_5 */
119 {0xC6, 0x64, 0x01}, /* 06: VCLK50 */
120 {0x94, 0x62, 0x01}, /* 07: VCLK56_25 */
121 {0x80, 0x64, 0x00}, /* 08: VCLK65 */
122 {0x7B, 0x63, 0x00}, /* 09: VCLK75 */
123 {0x67, 0x62, 0x00}, /* 0A: VCLK78_75 */
124 {0x7C, 0x62, 0x00}, /* 0B: VCLK94_5 */
125 {0x8E, 0x62, 0x00}, /* 0C: VCLK108 */
126 {0x85, 0x24, 0x00}, /* 0D: VCLK135 */
127 {0x67, 0x22, 0x00}, /* 0E: VCLK157_5 */
128 {0x6A, 0x22, 0x00}, /* 0F: VCLK162 */
129 {0x4d, 0x4c, 0x80}, /* 10: VCLK154 */
130 {0xa7, 0x78, 0x80}, /* 11: VCLK83.5 */
131 {0x28, 0x49, 0x80}, /* 12: VCLK106.5 */
132 {0x37, 0x49, 0x80}, /* 13: VCLK146.25 */
133 {0x1f, 0x45, 0x80}, /* 14: VCLK148.5 */
134 {0x47, 0x6c, 0x80}, /* 15: VCLK71 */
135 {0x25, 0x65, 0x80}, /* 16: VCLK88.75 */
136 {0x58, 0x01, 0x42}, /* 17: VCLK119 */
137 {0x32, 0x67, 0x80}, /* 18: VCLK85_5 */
138 {0x6a, 0x6d, 0x80}, /* 19: VCLK97_75 */
139 {0x44, 0x20, 0x43}, /* 1A: VCLK118_25 */
140};
141
142static const struct ast_vbios_stdtable vbios_stdtable[] = {
112 /* MD_2_3_400 */ 143 /* MD_2_3_400 */
113 { 144 {
114 0x67, 145 0x67,
@@ -181,21 +212,21 @@ static struct ast_vbios_stdtable vbios_stdtable[] = {
181 }, 212 },
182}; 213};
183 214
184static struct ast_vbios_enhtable res_640x480[] = { 215static const struct ast_vbios_enhtable res_640x480[] = {
185 { 800, 640, 8, 96, 525, 480, 2, 2, VCLK25_175, /* 60Hz */ 216 { 800, 640, 8, 96, 525, 480, 2, 2, VCLK25_175, /* 60Hz */
186 (SyncNN | HBorder | VBorder | Charx8Dot), 60, 1, 0x2E }, 217 (SyncNN | HBorder | VBorder | Charx8Dot), 60, 1, 0x2E },
187 { 832, 640, 16, 40, 520, 480, 1, 3, VCLK31_5, /* 72Hz */ 218 { 832, 640, 16, 40, 520, 480, 1, 3, VCLK31_5, /* 72Hz */
188 (SyncNN | HBorder | VBorder | Charx8Dot), 72, 2, 0x2E }, 219 (SyncNN | HBorder | VBorder | Charx8Dot), 72, 2, 0x2E },
189 { 840, 640, 16, 64, 500, 480, 1, 3, VCLK31_5, /* 75Hz */ 220 { 840, 640, 16, 64, 500, 480, 1, 3, VCLK31_5, /* 75Hz */
190 (SyncNN | Charx8Dot) , 75, 3, 0x2E }, 221 (SyncNN | Charx8Dot) , 75, 3, 0x2E },
191 { 832, 640, 56, 56, 509, 480, 1, 3, VCLK36, /* 85Hz */ 222 { 832, 640, 56, 56, 509, 480, 1, 3, VCLK36, /* 85Hz */
192 (SyncNN | Charx8Dot) , 85, 4, 0x2E }, 223 (SyncNN | Charx8Dot) , 85, 4, 0x2E },
193 { 832, 640, 56, 56, 509, 480, 1, 3, VCLK36, /* end */ 224 { 832, 640, 56, 56, 509, 480, 1, 3, VCLK36, /* end */
194 (SyncNN | Charx8Dot) , 0xFF, 4, 0x2E }, 225 (SyncNN | Charx8Dot) , 0xFF, 4, 0x2E },
195}; 226};
196 227
197static struct ast_vbios_enhtable res_800x600[] = { 228static const struct ast_vbios_enhtable res_800x600[] = {
198 {1024, 800, 24, 72, 625, 600, 1, 2, VCLK36, /* 56Hz */ 229 {1024, 800, 24, 72, 625, 600, 1, 2, VCLK36, /* 56Hz */
199 (SyncPP | Charx8Dot), 56, 1, 0x30 }, 230 (SyncPP | Charx8Dot), 56, 1, 0x30 },
200 {1056, 800, 40, 128, 628, 600, 1, 4, VCLK40, /* 60Hz */ 231 {1056, 800, 40, 128, 628, 600, 1, 4, VCLK40, /* 60Hz */
201 (SyncPP | Charx8Dot), 60, 2, 0x30 }, 232 (SyncPP | Charx8Dot), 60, 2, 0x30 },
@@ -210,7 +241,7 @@ static struct ast_vbios_enhtable res_800x600[] = {
210}; 241};
211 242
212 243
213static struct ast_vbios_enhtable res_1024x768[] = { 244static const struct ast_vbios_enhtable res_1024x768[] = {
214 {1344, 1024, 24, 136, 806, 768, 3, 6, VCLK65, /* 60Hz */ 245 {1344, 1024, 24, 136, 806, 768, 3, 6, VCLK65, /* 60Hz */
215 (SyncNN | Charx8Dot), 60, 1, 0x31 }, 246 (SyncNN | Charx8Dot), 60, 1, 0x31 },
216 {1328, 1024, 24, 136, 806, 768, 3, 6, VCLK75, /* 70Hz */ 247 {1328, 1024, 24, 136, 806, 768, 3, 6, VCLK75, /* 70Hz */
@@ -223,7 +254,7 @@ static struct ast_vbios_enhtable res_1024x768[] = {
223 (SyncPP | Charx8Dot), 0xFF, 4, 0x31 }, 254 (SyncPP | Charx8Dot), 0xFF, 4, 0x31 },
224}; 255};
225 256
226static struct ast_vbios_enhtable res_1280x1024[] = { 257static const struct ast_vbios_enhtable res_1280x1024[] = {
227 {1688, 1280, 48, 112, 1066, 1024, 1, 3, VCLK108, /* 60Hz */ 258 {1688, 1280, 48, 112, 1066, 1024, 1, 3, VCLK108, /* 60Hz */
228 (SyncPP | Charx8Dot), 60, 1, 0x32 }, 259 (SyncPP | Charx8Dot), 60, 1, 0x32 },
229 {1688, 1280, 16, 144, 1066, 1024, 1, 3, VCLK135, /* 75Hz */ 260 {1688, 1280, 16, 144, 1066, 1024, 1, 3, VCLK135, /* 75Hz */
@@ -234,7 +265,7 @@ static struct ast_vbios_enhtable res_1280x1024[] = {
234 (SyncPP | Charx8Dot), 0xFF, 3, 0x32 }, 265 (SyncPP | Charx8Dot), 0xFF, 3, 0x32 },
235}; 266};
236 267
237static struct ast_vbios_enhtable res_1600x1200[] = { 268static const struct ast_vbios_enhtable res_1600x1200[] = {
238 {2160, 1600, 64, 192, 1250, 1200, 1, 3, VCLK162, /* 60Hz */ 269 {2160, 1600, 64, 192, 1250, 1200, 1, 3, VCLK162, /* 60Hz */
239 (SyncPP | Charx8Dot), 60, 1, 0x33 }, 270 (SyncPP | Charx8Dot), 60, 1, 0x33 },
240 {2160, 1600, 64, 192, 1250, 1200, 1, 3, VCLK162, /* end */ 271 {2160, 1600, 64, 192, 1250, 1200, 1, 3, VCLK162, /* end */
@@ -242,34 +273,39 @@ static struct ast_vbios_enhtable res_1600x1200[] = {
242}; 273};
243 274
244/* 16:9 */ 275/* 16:9 */
245static struct ast_vbios_enhtable res_1360x768[] = { 276static const struct ast_vbios_enhtable res_1360x768[] = {
246 {1792, 1360, 64,112, 795, 768, 3, 6, VCLK85_5, /* 60Hz */ 277 {1792, 1360, 64, 112, 795, 768, 3, 6, VCLK85_5, /* 60Hz */
247 (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x39 }, 278 (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x39 },
248 {1792, 1360, 64,112, 795, 768, 3, 6, VCLK85_5, /* end */ 279 {1792, 1360, 64, 112, 795, 768, 3, 6, VCLK85_5, /* end */
249 (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x39 }, 280 (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo |
281 AST2500PreCatchCRT), 0xFF, 1, 0x39 },
250}; 282};
251 283
252static struct ast_vbios_enhtable res_1600x900[] = { 284static const struct ast_vbios_enhtable res_1600x900[] = {
253 {1760, 1600, 48, 32, 926, 900, 3, 5, VCLK97_75, /* 60Hz CVT RB */ 285 {1760, 1600, 48, 32, 926, 900, 3, 5, VCLK97_75, /* 60Hz CVT RB */
254 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x3A }, 286 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo |
255 {2112, 1600, 88,168, 934, 900, 3, 5, VCLK118_25, /* 60Hz CVT */ 287 AST2500PreCatchCRT), 60, 1, 0x3A },
288 {2112, 1600, 88, 168, 934, 900, 3, 5, VCLK118_25, /* 60Hz CVT */
256 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x3A }, 289 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x3A },
257 {2112, 1600, 88,168, 934, 900, 3, 5, VCLK118_25, /* 60Hz CVT */ 290 {2112, 1600, 88, 168, 934, 900, 3, 5, VCLK118_25, /* 60Hz CVT */
258 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x3A }, 291 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x3A },
259}; 292};
260 293
261static struct ast_vbios_enhtable res_1920x1080[] = { 294static const struct ast_vbios_enhtable res_1920x1080[] = {
262 {2200, 1920, 88, 44, 1125, 1080, 4, 5, VCLK148_5, /* 60Hz */ 295 {2200, 1920, 88, 44, 1125, 1080, 4, 5, VCLK148_5, /* 60Hz */
263 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x38 }, 296 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo |
297 AST2500PreCatchCRT), 60, 1, 0x38 },
264 {2200, 1920, 88, 44, 1125, 1080, 4, 5, VCLK148_5, /* 60Hz */ 298 {2200, 1920, 88, 44, 1125, 1080, 4, 5, VCLK148_5, /* 60Hz */
265 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x38 }, 299 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo |
300 AST2500PreCatchCRT), 0xFF, 1, 0x38 },
266}; 301};
267 302
268 303
269/* 16:10 */ 304/* 16:10 */
270static struct ast_vbios_enhtable res_1280x800[] = { 305static const struct ast_vbios_enhtable res_1280x800[] = {
271 {1440, 1280, 48, 32, 823, 800, 3, 6, VCLK71, /* 60Hz RB */ 306 {1440, 1280, 48, 32, 823, 800, 3, 6, VCLK71, /* 60Hz RB */
272 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x35 }, 307 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo |
308 AST2500PreCatchCRT), 60, 1, 0x35 },
273 {1680, 1280, 72,128, 831, 800, 3, 6, VCLK83_5, /* 60Hz */ 309 {1680, 1280, 72,128, 831, 800, 3, 6, VCLK83_5, /* 60Hz */
274 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x35 }, 310 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x35 },
275 {1680, 1280, 72,128, 831, 800, 3, 6, VCLK83_5, /* 60Hz */ 311 {1680, 1280, 72,128, 831, 800, 3, 6, VCLK83_5, /* 60Hz */
@@ -277,29 +313,33 @@ static struct ast_vbios_enhtable res_1280x800[] = {
277 313
278}; 314};
279 315
280static struct ast_vbios_enhtable res_1440x900[] = { 316static const struct ast_vbios_enhtable res_1440x900[] = {
281 {1600, 1440, 48, 32, 926, 900, 3, 6, VCLK88_75, /* 60Hz RB */ 317 {1600, 1440, 48, 32, 926, 900, 3, 6, VCLK88_75, /* 60Hz RB */
282 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x36 }, 318 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo |
319 AST2500PreCatchCRT), 60, 1, 0x36 },
283 {1904, 1440, 80,152, 934, 900, 3, 6, VCLK106_5, /* 60Hz */ 320 {1904, 1440, 80,152, 934, 900, 3, 6, VCLK106_5, /* 60Hz */
284 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x36 }, 321 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x36 },
285 {1904, 1440, 80,152, 934, 900, 3, 6, VCLK106_5, /* 60Hz */ 322 {1904, 1440, 80,152, 934, 900, 3, 6, VCLK106_5, /* 60Hz */
286 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x36 }, 323 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x36 },
287}; 324};
288 325
289static struct ast_vbios_enhtable res_1680x1050[] = { 326static const struct ast_vbios_enhtable res_1680x1050[] = {
290 {1840, 1680, 48, 32, 1080, 1050, 3, 6, VCLK119, /* 60Hz RB */ 327 {1840, 1680, 48, 32, 1080, 1050, 3, 6, VCLK119, /* 60Hz RB */
291 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x37 }, 328 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo |
329 AST2500PreCatchCRT), 60, 1, 0x37 },
292 {2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz */ 330 {2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz */
293 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x37 }, 331 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x37 },
294 {2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz */ 332 {2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz */
295 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x37 }, 333 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x37 },
296}; 334};
297 335
298static struct ast_vbios_enhtable res_1920x1200[] = { 336static const struct ast_vbios_enhtable res_1920x1200[] = {
299 {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* 60Hz RB*/ 337 {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* 60Hz RB*/
300 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x34 }, 338 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo |
301 {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* 60Hz RB */ 339 AST2500PreCatchCRT), 60, 1, 0x34 },
302 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x34 }, 340 {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* 60Hz RB */
341 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo |
342 AST2500PreCatchCRT), 0xFF, 1, 0x34 },
303}; 343};
304 344
305#endif 345#endif
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-06 04:44:55 -0500