Merge branch 'x86/pti-urgent' into x86/pti

Integrate the PTI Global bit fixes which conflict with the 32bit PTI
support.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

51 files changed, 445 insertions, 149 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index f4c474a95875..71efcf38f11b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -57,6 +57,10 @@
 #define ACP_I2S_COMP2_CAP_REG_OFFSET            0xa8
 #define ACP_I2S_COMP1_PLAY_REG_OFFSET           0x6c
 #define ACP_I2S_COMP2_PLAY_REG_OFFSET           0x68
+#define ACP_BT_PLAY_REGS_START                  0x14970
+#define ACP_BT_PLAY_REGS_END                    0x14a24
+#define ACP_BT_COMP1_REG_OFFSET                 0xac
+#define ACP_BT_COMP2_REG_OFFSET                 0xa8
 
 #define mmACP_PGFSM_RETAIN_REG                  0x51c9
 #define mmACP_PGFSM_CONFIG_REG                  0x51ca
@@ -77,7 +81,7 @@
 #define ACP_SOFT_RESET_DONE_TIME_OUT_VALUE      0x000000FF
 
 #define ACP_TIMEOUT_LOOP                        0x000000FF
-#define ACP_DEVS                                3
+#define ACP_DEVS                                4
 #define ACP_SRC_ID                              162
 
 enum {
@@ -316,14 +320,13 @@ static int acp_hw_init(void *handle)
         if (adev->acp.acp_cell == NULL)
                 return -ENOMEM;
 
-        adev->acp.acp_res = kcalloc(4, sizeof(struct resource), GFP_KERNEL);
-
+        adev->acp.acp_res = kcalloc(5, sizeof(struct resource), GFP_KERNEL);
         if (adev->acp.acp_res == NULL) {
                 kfree(adev->acp.acp_cell);
                 return -ENOMEM;
         }
 
-        i2s_pdata = kcalloc(2, sizeof(struct i2s_platform_data), GFP_KERNEL);
+        i2s_pdata = kcalloc(3, sizeof(struct i2s_platform_data), GFP_KERNEL);
         if (i2s_pdata == NULL) {
                 kfree(adev->acp.acp_res);
                 kfree(adev->acp.acp_cell);
@@ -358,6 +361,20 @@ static int acp_hw_init(void *handle)
         i2s_pdata[1].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET;
         i2s_pdata[1].i2s_reg_comp2 = ACP_I2S_COMP2_CAP_REG_OFFSET;
 
+        i2s_pdata[2].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
+        switch (adev->asic_type) {
+        case CHIP_STONEY:
+                i2s_pdata[2].quirks |= DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
+                break;
+        default:
+                break;
+        }
+
+        i2s_pdata[2].cap = DWC_I2S_PLAY | DWC_I2S_RECORD;
+        i2s_pdata[2].snd_rates = SNDRV_PCM_RATE_8000_96000;
+        i2s_pdata[2].i2s_reg_comp1 = ACP_BT_COMP1_REG_OFFSET;
+        i2s_pdata[2].i2s_reg_comp2 = ACP_BT_COMP2_REG_OFFSET;
+
         adev->acp.acp_res[0].name = "acp2x_dma";
         adev->acp.acp_res[0].flags = IORESOURCE_MEM;
         adev->acp.acp_res[0].start = acp_base;
@@ -373,13 +390,18 @@ static int acp_hw_init(void *handle)
         adev->acp.acp_res[2].start = acp_base + ACP_I2S_CAP_REGS_START;
         adev->acp.acp_res[2].end = acp_base + ACP_I2S_CAP_REGS_END;
 
-        adev->acp.acp_res[3].name = "acp2x_dma_irq";
-        adev->acp.acp_res[3].flags = IORESOURCE_IRQ;
-        adev->acp.acp_res[3].start = amdgpu_irq_create_mapping(adev, 162);
-        adev->acp.acp_res[3].end = adev->acp.acp_res[3].start;
+        adev->acp.acp_res[3].name = "acp2x_dw_bt_i2s_play_cap";
+        adev->acp.acp_res[3].flags = IORESOURCE_MEM;
+        adev->acp.acp_res[3].start = acp_base + ACP_BT_PLAY_REGS_START;
+        adev->acp.acp_res[3].end = acp_base + ACP_BT_PLAY_REGS_END;
+
+        adev->acp.acp_res[4].name = "acp2x_dma_irq";
+        adev->acp.acp_res[4].flags = IORESOURCE_IRQ;
+        adev->acp.acp_res[4].start = amdgpu_irq_create_mapping(adev, 162);
+        adev->acp.acp_res[4].end = adev->acp.acp_res[4].start;
 
         adev->acp.acp_cell[0].name = "acp_audio_dma";
-        adev->acp.acp_cell[0].num_resources = 4;
+        adev->acp.acp_cell[0].num_resources = 5;
         adev->acp.acp_cell[0].resources = &adev->acp.acp_res[0];
         adev->acp.acp_cell[0].platform_data = &adev->asic_type;
         adev->acp.acp_cell[0].pdata_size = sizeof(adev->asic_type);
@@ -396,6 +418,12 @@ static int acp_hw_init(void *handle)
         adev->acp.acp_cell[2].platform_data = &i2s_pdata[1];
         adev->acp.acp_cell[2].pdata_size = sizeof(struct i2s_platform_data);
 
+        adev->acp.acp_cell[3].name = "designware-i2s";
+        adev->acp.acp_cell[3].num_resources = 1;
+        adev->acp.acp_cell[3].resources = &adev->acp.acp_res[3];
+        adev->acp.acp_cell[3].platform_data = &i2s_pdata[2];
+        adev->acp.acp_cell[3].pdata_size = sizeof(struct i2s_platform_data);
+
         r = mfd_add_hotplug_devices(adev->acp.parent, adev->acp.acp_cell,
                                                                 ACP_DEVS);
         if (r)
@@ -451,7 +479,6 @@ static int acp_hw_init(void *handle)
         val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
         val &= ~ACP_SOFT_RESET__SoftResetAud_MASK;
         cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);
-
         return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
index 9ab89371d9e8..ca8bf1c9a98e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
@@ -575,6 +575,7 @@ static const struct amdgpu_px_quirk amdgpu_px_quirk_list[] = {
         { 0x1002, 0x6900, 0x1002, 0x0124, AMDGPU_PX_QUIRK_FORCE_ATPX },
         { 0x1002, 0x6900, 0x1028, 0x0812, AMDGPU_PX_QUIRK_FORCE_ATPX },
         { 0x1002, 0x6900, 0x1028, 0x0813, AMDGPU_PX_QUIRK_FORCE_ATPX },
+        { 0x1002, 0x6900, 0x1025, 0x125A, AMDGPU_PX_QUIRK_FORCE_ATPX },
         { 0, 0, 0, 0, 0 },
 };
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 82312a7bc6ad..9c85a90be293 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -927,6 +927,10 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
                 r = amdgpu_bo_vm_update_pte(p);
                 if (r)
                         return r;
+
+                r = reservation_object_reserve_shared(vm->root.base.bo->tbo.resv);
+                if (r)
+                        return r;
         }
 
         return amdgpu_cs_sync_rings(p);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 6e5284e6c028..2c5f093e79e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2747,6 +2747,9 @@ int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
         if (r)
                 return r;
 
+        /* Make sure IB tests flushed */
+        flush_delayed_work(&adev->late_init_work);
+
         /* blat the mode back in */
         if (fbcon) {
                 if (!amdgpu_device_has_dc_support(adev)) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index edf16b2b957a..fdcb498f6d19 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -107,6 +107,9 @@ static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
                 return;
         list_add_tail(&base->bo_list, &bo->va);
 
+        if (bo->tbo.type == ttm_bo_type_kernel)
+                list_move(&base->vm_status, &vm->relocated);
+
         if (bo->tbo.resv != vm->root.base.bo->tbo.resv)
                 return;
 
@@ -468,7 +471,6 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev,
                         pt->parent = amdgpu_bo_ref(parent->base.bo);
 
                         amdgpu_vm_bo_base_init(&entry->base, vm, pt);
-                        list_move(&entry->base.vm_status, &vm->relocated);
                 }
 
                 if (level < AMDGPU_VM_PTB) {
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 4304d9e408b8..ace9ad578ca0 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -83,22 +83,21 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
         enum i2c_mot_mode mot = (msg->request & DP_AUX_I2C_MOT) ?
                 I2C_MOT_TRUE : I2C_MOT_FALSE;
         enum ddc_result res;
-        uint32_t read_bytes = msg->size;
+        ssize_t read_bytes;
 
         if (WARN_ON(msg->size > 16))
                 return -E2BIG;
 
         switch (msg->request & ~DP_AUX_I2C_MOT) {
         case DP_AUX_NATIVE_READ:
-                res = dal_ddc_service_read_dpcd_data(
+                read_bytes = dal_ddc_service_read_dpcd_data(
                                 TO_DM_AUX(aux)->ddc_service,
                                 false,
                                 I2C_MOT_UNDEF,
                                 msg->address,
                                 msg->buffer,
-                                msg->size,
-                                &read_bytes);
-                break;
+                                msg->size);
+                return read_bytes;
         case DP_AUX_NATIVE_WRITE:
                 res = dal_ddc_service_write_dpcd_data(
                                 TO_DM_AUX(aux)->ddc_service,
@@ -109,15 +108,14 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
                                 msg->size);
                 break;
         case DP_AUX_I2C_READ:
-                res = dal_ddc_service_read_dpcd_data(
+                read_bytes = dal_ddc_service_read_dpcd_data(
                                 TO_DM_AUX(aux)->ddc_service,
                                 true,
                                 mot,
                                 msg->address,
                                 msg->buffer,
-                                msg->size,
-                                &read_bytes);
-                break;
+                                msg->size);
+                return read_bytes;
         case DP_AUX_I2C_WRITE:
                 res = dal_ddc_service_write_dpcd_data(
                                 TO_DM_AUX(aux)->ddc_service,
@@ -139,9 +137,7 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
                  r == DDC_RESULT_SUCESSFULL);
 #endif
 
-        if (res != DDC_RESULT_SUCESSFULL)
-                return -EIO;
-        return read_bytes;
+        return msg->size;
 }
 
 static enum drm_connector_status
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
index 5a3346124a01..5a2e952c5bea 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
@@ -255,8 +255,9 @@ static void pp_to_dc_clock_levels_with_latency(
                         DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
 
         for (i = 0; i < clk_level_info->num_levels; i++) {
-                DRM_DEBUG("DM_PPLIB:\t %d\n", pp_clks->data[i].clocks_in_khz);
-                clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz;
+                DRM_DEBUG("DM_PPLIB:\t %d in 10kHz\n", pp_clks->data[i].clocks_in_khz);
+                /* translate 10kHz to kHz */
+                clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz * 10;
                 clk_level_info->data[i].latency_in_us = pp_clks->data[i].latency_in_us;
         }
 }
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
index ae48d603ebd6..49c2face1e7a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
@@ -629,14 +629,13 @@ bool dal_ddc_service_query_ddc_data(
         return ret;
 }
 
-enum ddc_result dal_ddc_service_read_dpcd_data(
+ssize_t dal_ddc_service_read_dpcd_data(
         struct ddc_service *ddc,
         bool i2c,
         enum i2c_mot_mode mot,
         uint32_t address,
         uint8_t *data,
-        uint32_t len,
-        uint32_t *read)
+        uint32_t len)
 {
         struct aux_payload read_payload = {
                 .i2c_over_aux = i2c,
@@ -653,8 +652,6 @@ enum ddc_result dal_ddc_service_read_dpcd_data(
                 .mot = mot
         };
 
-        *read = 0;
-
         if (len > DEFAULT_AUX_MAX_DATA_SIZE) {
                 BREAK_TO_DEBUGGER();
                 return DDC_RESULT_FAILED_INVALID_OPERATION;
@@ -664,8 +661,7 @@ enum ddc_result dal_ddc_service_read_dpcd_data(
                 ddc->ctx->i2caux,
                 ddc->ddc_pin,
                 &command)) {
-                *read = command.payloads->length;
-                return DDC_RESULT_SUCESSFULL;
+                return (ssize_t)command.payloads->length;
         }
 
         return DDC_RESULT_FAILED_OPERATION;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 7857cb42b3e6..bdd121485cbc 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1767,12 +1767,10 @@ static void dp_test_send_link_training(struct dc_link *link)
         dp_retrain_link_dp_test(link, &link_settings, false);
 }
 
-/* TODO hbr2 compliance eye output is unstable
+/* TODO Raven hbr2 compliance eye output is unstable
  * (toggling on and off) with debugger break
  * This caueses intermittent PHY automation failure
  * Need to look into the root cause */
-static uint8_t force_tps4_for_cp2520 = 1;
-
 static void dp_test_send_phy_test_pattern(struct dc_link *link)
 {
         union phy_test_pattern dpcd_test_pattern;
@@ -1832,13 +1830,13 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link)
                 break;
         case PHY_TEST_PATTERN_CP2520_1:
                 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
-                test_pattern = (force_tps4_for_cp2520 == 1) ?
+                test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
                                 DP_TEST_PATTERN_TRAINING_PATTERN4 :
                                 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
                 break;
         case PHY_TEST_PATTERN_CP2520_2:
                 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
-                test_pattern = (force_tps4_for_cp2520 == 1) ?
+                test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
                                 DP_TEST_PATTERN_TRAINING_PATTERN4 :
                                 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
                 break;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 9cfde0ccf4e9..53c71296f3dd 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -76,6 +76,7 @@ struct dc_caps {
         bool is_apu;
         bool dual_link_dvi;
         bool post_blend_color_processing;
+        bool force_dp_tps4_for_cp2520;
 };
 
 struct dc_dcc_surface_param {
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
index b235a75355b8..bae752332a9f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
@@ -741,6 +741,29 @@ static struct mem_input_funcs dce_mi_funcs = {
         .mem_input_is_flip_pending = dce_mi_is_flip_pending
 };
 
+static struct mem_input_funcs dce112_mi_funcs = {
+        .mem_input_program_display_marks = dce112_mi_program_display_marks,
+        .allocate_mem_input = dce_mi_allocate_dmif,
+        .free_mem_input = dce_mi_free_dmif,
+        .mem_input_program_surface_flip_and_addr =
+                        dce_mi_program_surface_flip_and_addr,
+        .mem_input_program_pte_vm = dce_mi_program_pte_vm,
+        .mem_input_program_surface_config =
+                        dce_mi_program_surface_config,
+        .mem_input_is_flip_pending = dce_mi_is_flip_pending
+};
+
+static struct mem_input_funcs dce120_mi_funcs = {
+        .mem_input_program_display_marks = dce120_mi_program_display_marks,
+        .allocate_mem_input = dce_mi_allocate_dmif,
+        .free_mem_input = dce_mi_free_dmif,
+        .mem_input_program_surface_flip_and_addr =
+                        dce_mi_program_surface_flip_and_addr,
+        .mem_input_program_pte_vm = dce_mi_program_pte_vm,
+        .mem_input_program_surface_config =
+                        dce_mi_program_surface_config,
+        .mem_input_is_flip_pending = dce_mi_is_flip_pending
+};
 
 void dce_mem_input_construct(
         struct dce_mem_input *dce_mi,
@@ -769,7 +792,7 @@ void dce112_mem_input_construct(
         const struct dce_mem_input_mask *mi_mask)
 {
         dce_mem_input_construct(dce_mi, ctx, inst, regs, mi_shift, mi_mask);
-        dce_mi->base.funcs->mem_input_program_display_marks = dce112_mi_program_display_marks;
+        dce_mi->base.funcs = &dce112_mi_funcs;
 }
 
 void dce120_mem_input_construct(
@@ -781,5 +804,5 @@ void dce120_mem_input_construct(
         const struct dce_mem_input_mask *mi_mask)
 {
         dce_mem_input_construct(dce_mi, ctx, inst, regs, mi_shift, mi_mask);
-        dce_mi->base.funcs->mem_input_program_display_marks = dce120_mi_program_display_marks;
+        dce_mi->base.funcs = &dce120_mi_funcs;
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index 38ec0d609297..344dd2e69e7c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -678,9 +678,22 @@ bool dce100_validate_bandwidth(
         struct dc  *dc,
         struct dc_state *context)
 {
-        /* TODO implement when needed but for now hardcode max value*/
-        context->bw.dce.dispclk_khz = 681000;
-        context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER;
+        int i;
+        bool at_least_one_pipe = false;
+
+        for (i = 0; i < dc->res_pool->pipe_count; i++) {
+                if (context->res_ctx.pipe_ctx[i].stream)
+                        at_least_one_pipe = true;
+        }
+
+        if (at_least_one_pipe) {
+                /* TODO implement when needed but for now hardcode max value*/
+                context->bw.dce.dispclk_khz = 681000;
+                context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER;
+        } else {
+                context->bw.dce.dispclk_khz = 0;
+                context->bw.dce.yclk_khz = 0;
+        }
 
         return true;
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index df5cb2d1d164..34dac84066a0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -1027,6 +1027,8 @@ static bool construct(
         dc->caps.max_slave_planes = 1;
         dc->caps.is_apu = true;
         dc->caps.post_blend_color_processing = false;
+        /* Raven DP PHY HBR2 eye diagram pattern is not stable. Use TP4 */
+        dc->caps.force_dp_tps4_for_cp2520 = true;
 
         if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
                 dc->debug = debug_defaults_drv;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
index 30b3a08b91be..090b7a8dd67b 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
@@ -102,14 +102,13 @@ bool dal_ddc_service_query_ddc_data(
                 uint8_t *read_buf,
                 uint32_t read_size);
 
-enum ddc_result dal_ddc_service_read_dpcd_data(
+ssize_t dal_ddc_service_read_dpcd_data(
                 struct ddc_service *ddc,
                 bool i2c,
                 enum i2c_mot_mode mot,
                 uint32_t address,
                 uint8_t *data,
-                uint32_t len,
-                uint32_t *read);
+                uint32_t len);
 
 enum ddc_result dal_ddc_service_write_dpcd_data(
                 struct ddc_service *ddc,
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
index d644a9bb9078..9f407c48d4f0 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
@@ -381,6 +381,7 @@ int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr)
         uint32_t fw_to_load;
         int result = 0;
         struct SMU_DRAMData_TOC *toc;
+        uint32_t num_entries = 0;
 
         if (!hwmgr->reload_fw) {
                 pr_info("skip reloading...\n");
@@ -422,41 +423,41 @@ int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr)
         }
 
         toc = (struct SMU_DRAMData_TOC *)smu_data->header;
-        toc->num_entries = 0;
         toc->structure_version = 1;
 
         PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-                                UCODE_ID_RLC_G, &toc->entry[toc->num_entries++]),
+                                UCODE_ID_RLC_G, &toc->entry[num_entries++]),
                                 "Failed to Get Firmware Entry.", return -EINVAL);
         PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-                                UCODE_ID_CP_CE, &toc->entry[toc->num_entries++]),
+                                UCODE_ID_CP_CE, &toc->entry[num_entries++]),
                                 "Failed to Get Firmware Entry.", return -EINVAL);
         PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-                                UCODE_ID_CP_PFP, &toc->entry[toc->num_entries++]),
+                                UCODE_ID_CP_PFP, &toc->entry[num_entries++]),
                                 "Failed to Get Firmware Entry.", return -EINVAL);
         PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-                                UCODE_ID_CP_ME, &toc->entry[toc->num_entries++]),
+                                UCODE_ID_CP_ME, &toc->entry[num_entries++]),
                                 "Failed to Get Firmware Entry.", return -EINVAL);
         PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-                                UCODE_ID_CP_MEC, &toc->entry[toc->num_entries++]),
+                                UCODE_ID_CP_MEC, &toc->entry[num_entries++]),
                                 "Failed to Get Firmware Entry.", return -EINVAL);
         PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-                                UCODE_ID_CP_MEC_JT1, &toc->entry[toc->num_entries++]),
+                                UCODE_ID_CP_MEC_JT1, &toc->entry[num_entries++]),
                                 "Failed to Get Firmware Entry.", return -EINVAL);
         PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-                                UCODE_ID_CP_MEC_JT2, &toc->entry[toc->num_entries++]),
+                                UCODE_ID_CP_MEC_JT2, &toc->entry[num_entries++]),
                                 "Failed to Get Firmware Entry.", return -EINVAL);
         PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-                                UCODE_ID_SDMA0, &toc->entry[toc->num_entries++]),
+                                UCODE_ID_SDMA0, &toc->entry[num_entries++]),
                                 "Failed to Get Firmware Entry.", return -EINVAL);
         PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-                                UCODE_ID_SDMA1, &toc->entry[toc->num_entries++]),
+                                UCODE_ID_SDMA1, &toc->entry[num_entries++]),
                                 "Failed to Get Firmware Entry.", return -EINVAL);
         if (!hwmgr->not_vf)
                 PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
-                                UCODE_ID_MEC_STORAGE, &toc->entry[toc->num_entries++]),
+                                UCODE_ID_MEC_STORAGE, &toc->entry[num_entries++]),
                                 "Failed to Get Firmware Entry.", return -EINVAL);
 
+        toc->num_entries = num_entries;
         smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, upper_32_bits(smu_data->header_buffer.mc_addr));
         smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, lower_32_bits(smu_data->header_buffer.mc_addr));
 
diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c
index 03eeee11dd5b..42a40daff132 100644
--- a/drivers/gpu/drm/armada/armada_crtc.c
+++ b/drivers/gpu/drm/armada/armada_crtc.c
@@ -519,8 +519,9 @@ static irqreturn_t armada_drm_irq(int irq, void *arg)
         u32 v, stat = readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR);
 
         /*
-         * This is rediculous - rather than writing bits to clear, we
-         * have to set the actual status register value.  This is racy.
+         * Reading the ISR appears to clear bits provided CLEAN_SPU_IRQ_ISR
+         * is set.  Writing has some other effect to acknowledge the IRQ -
+         * without this, we only get a single IRQ.
          */
         writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
 
@@ -1116,16 +1117,22 @@ armada_drm_crtc_set_property(struct drm_crtc *crtc,
 static int armada_drm_crtc_enable_vblank(struct drm_crtc *crtc)
 {
         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
+        unsigned long flags;
 
+        spin_lock_irqsave(&dcrtc->irq_lock, flags);
         armada_drm_crtc_enable_irq(dcrtc, VSYNC_IRQ_ENA);
+        spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
         return 0;
 }
 
 static void armada_drm_crtc_disable_vblank(struct drm_crtc *crtc)
 {
         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
+        unsigned long flags;
 
+        spin_lock_irqsave(&dcrtc->irq_lock, flags);
         armada_drm_crtc_disable_irq(dcrtc, VSYNC_IRQ_ENA);
+        spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
 }
 
 static const struct drm_crtc_funcs armada_crtc_funcs = {
@@ -1415,6 +1422,7 @@ static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev,
                        CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1);
         writel_relaxed(0x2032ff81, dcrtc->base + LCD_SPU_DMA_CTRL1);
         writel_relaxed(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
+        readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR);
         writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
 
         ret = devm_request_irq(dev, irq, armada_drm_irq, 0, "armada_drm_crtc",
diff --git a/drivers/gpu/drm/armada/armada_hw.h b/drivers/gpu/drm/armada/armada_hw.h
index 27319a8335e2..345dc4d0851e 100644
--- a/drivers/gpu/drm/armada/armada_hw.h
+++ b/drivers/gpu/drm/armada/armada_hw.h
@@ -160,6 +160,7 @@ enum {
         CFG_ALPHAM_GRA          = 0x1 << 16,
         CFG_ALPHAM_CFG          = 0x2 << 16,
         CFG_ALPHA_MASK          = 0xff << 8,
+#define CFG_ALPHA(x)            ((x) << 8)
         CFG_PIXCMD_MASK         = 0xff,
 };
 
diff --git a/drivers/gpu/drm/armada/armada_overlay.c b/drivers/gpu/drm/armada/armada_overlay.c
index c391955009d6..afa7ded3ae31 100644
--- a/drivers/gpu/drm/armada/armada_overlay.c
+++ b/drivers/gpu/drm/armada/armada_overlay.c
@@ -28,6 +28,7 @@ struct armada_ovl_plane_properties {
         uint16_t contrast;
         uint16_t saturation;
         uint32_t colorkey_mode;
+        uint32_t colorkey_enable;
 };
 
 struct armada_ovl_plane {
@@ -54,11 +55,13 @@ armada_ovl_update_attr(struct armada_ovl_plane_properties *prop,
         writel_relaxed(0x00002000, dcrtc->base + LCD_SPU_CBSH_HUE);
 
         spin_lock_irq(&dcrtc->irq_lock);
-        armada_updatel(prop->colorkey_mode | CFG_ALPHAM_GRA,
-                     CFG_CKMODE_MASK | CFG_ALPHAM_MASK | CFG_ALPHA_MASK,
-                     dcrtc->base + LCD_SPU_DMA_CTRL1);
-
-        armada_updatel(ADV_GRACOLORKEY, 0, dcrtc->base + LCD_SPU_ADV_REG);
+        armada_updatel(prop->colorkey_mode,
+                       CFG_CKMODE_MASK | CFG_ALPHAM_MASK | CFG_ALPHA_MASK,
+                       dcrtc->base + LCD_SPU_DMA_CTRL1);
+        if (dcrtc->variant->has_spu_adv_reg)
+                armada_updatel(prop->colorkey_enable,
+                               ADV_GRACOLORKEY | ADV_VIDCOLORKEY,
+                               dcrtc->base + LCD_SPU_ADV_REG);
         spin_unlock_irq(&dcrtc->irq_lock);
 }
 
@@ -321,8 +324,17 @@ static int armada_ovl_plane_set_property(struct drm_plane *plane,
                 dplane->prop.colorkey_vb |= K2B(val);
                 update_attr = true;
         } else if (property == priv->colorkey_mode_prop) {
-                dplane->prop.colorkey_mode &= ~CFG_CKMODE_MASK;
-                dplane->prop.colorkey_mode |= CFG_CKMODE(val);
+                if (val == CKMODE_DISABLE) {
+                        dplane->prop.colorkey_mode =
+                                CFG_CKMODE(CKMODE_DISABLE) |
+                                CFG_ALPHAM_CFG | CFG_ALPHA(255);
+                        dplane->prop.colorkey_enable = 0;
+                } else {
+                        dplane->prop.colorkey_mode =
+                                CFG_CKMODE(val) |
+                                CFG_ALPHAM_GRA | CFG_ALPHA(0);
+                        dplane->prop.colorkey_enable = ADV_GRACOLORKEY;
+                }
                 update_attr = true;
         } else if (property == priv->brightness_prop) {
                 dplane->prop.brightness = val - 256;
@@ -453,7 +465,9 @@ int armada_overlay_plane_create(struct drm_device *dev, unsigned long crtcs)
         dplane->prop.colorkey_yr = 0xfefefe00;
         dplane->prop.colorkey_ug = 0x01010100;
         dplane->prop.colorkey_vb = 0x01010100;
-        dplane->prop.colorkey_mode = CFG_CKMODE(CKMODE_RGB);
+        dplane->prop.colorkey_mode = CFG_CKMODE(CKMODE_RGB) |
+                                     CFG_ALPHAM_GRA | CFG_ALPHA(0);
+        dplane->prop.colorkey_enable = ADV_GRACOLORKEY;
         dplane->prop.brightness = 0;
         dplane->prop.contrast = 0x4000;
         dplane->prop.saturation = 0x4000;
diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
index 73021b388e12..dd3ff2f2cdce 100644
--- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
+++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
@@ -429,6 +429,18 @@ static void adv7511_hpd_work(struct work_struct *work)
         else
                 status = connector_status_disconnected;
 
+        /*
+         * The bridge resets its registers on unplug. So when we get a plug
+         * event and we're already supposed to be powered, cycle the bridge to
+         * restore its state.
+         */
+        if (status == connector_status_connected &&
+            adv7511->connector.status == connector_status_disconnected &&
+            adv7511->powered) {
+                regcache_mark_dirty(adv7511->regmap);
+                adv7511_power_on(adv7511);
+        }
+
         if (adv7511->connector.status != status) {
                 adv7511->connector.status = status;
                 if (status == connector_status_disconnected)
diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c
index 130da5195f3b..81e32199d3ef 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -1510,8 +1510,9 @@ int drm_atomic_helper_async_check(struct drm_device *dev,
 {
         struct drm_crtc *crtc;
         struct drm_crtc_state *crtc_state;
-        struct drm_plane *plane;
-        struct drm_plane_state *old_plane_state, *new_plane_state;
+        struct drm_plane *plane = NULL;
+        struct drm_plane_state *old_plane_state = NULL;
+        struct drm_plane_state *new_plane_state = NULL;
         const struct drm_plane_helper_funcs *funcs;
         int i, n_planes = 0;
 
@@ -1527,7 +1528,8 @@ int drm_atomic_helper_async_check(struct drm_device *dev,
         if (n_planes != 1)
                 return -EINVAL;
 
-        if (!new_plane_state->crtc)
+        if (!new_plane_state->crtc ||
+            old_plane_state->crtc != new_plane_state->crtc)
                 return -EINVAL;
 
         funcs = plane->helper_private;
diff --git a/drivers/gpu/drm/drm_context.c b/drivers/gpu/drm/drm_context.c
index 3c4000facb36..f973d287696a 100644
--- a/drivers/gpu/drm/drm_context.c
+++ b/drivers/gpu/drm/drm_context.c
@@ -372,7 +372,7 @@ int drm_legacy_addctx(struct drm_device *dev, void *data,
                 ctx->handle = drm_legacy_ctxbitmap_next(dev);
         }
         DRM_DEBUG("%d\n", ctx->handle);
-        if (ctx->handle == -1) {
+        if (ctx->handle < 0) {
                 DRM_DEBUG("Not enough free contexts.\n");
                 /* Should this return -EBUSY instead? */
                 return -ENOMEM;
diff --git a/drivers/gpu/drm/drm_lease.c b/drivers/gpu/drm/drm_lease.c
index 50c73c0a20b9..d638c0fb3418 100644
--- a/drivers/gpu/drm/drm_lease.c
+++ b/drivers/gpu/drm/drm_lease.c
@@ -553,24 +553,13 @@ int drm_mode_create_lease_ioctl(struct drm_device *dev,
 
         /* Clone the lessor file to create a new file for us */
         DRM_DEBUG_LEASE("Allocating lease file\n");
-        path_get(&lessor_file->f_path);
-        lessee_file = alloc_file(&lessor_file->f_path,
-                                 lessor_file->f_mode,
-                                 fops_get(lessor_file->f_inode->i_fop));
-
+        lessee_file = filp_clone_open(lessor_file);
         if (IS_ERR(lessee_file)) {
                 ret = PTR_ERR(lessee_file);
                 goto out_lessee;
         }
 
-        /* Initialize the new file for DRM */
-        DRM_DEBUG_LEASE("Initializing the file with %p\n", lessee_file->f_op->open);
-        ret = lessee_file->f_op->open(lessee_file->f_inode, lessee_file);
-        if (ret)
-                goto out_lessee_file;
-
         lessee_priv = lessee_file->private_data;
-
         /* Change the file to a master one */
         drm_master_put(&lessee_priv->master);
         lessee_priv->master = lessee;
@@ -588,9 +577,6 @@ int drm_mode_create_lease_ioctl(struct drm_device *dev,
         DRM_DEBUG_LEASE("drm_mode_create_lease_ioctl succeeded\n");
         return 0;
 
-out_lessee_file:
-        fput(lessee_file);
-
 out_lessee:
         drm_master_put(&lessee);
 
diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index b51c05d03f14..7f562410f9cf 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -862,6 +862,7 @@ static int cmd_reg_handler(struct parser_exec_state *s,
 {
         struct intel_vgpu *vgpu = s->vgpu;
         struct intel_gvt *gvt = vgpu->gvt;
+        u32 ctx_sr_ctl;
 
         if (offset + 4 > gvt->device_info.mmio_size) {
                 gvt_vgpu_err("%s access to (%x) outside of MMIO range\n",
@@ -894,6 +895,28 @@ static int cmd_reg_handler(struct parser_exec_state *s,
                 patch_value(s, cmd_ptr(s, index), VGT_PVINFO_PAGE);
         }
 
+        /* TODO
+         * Right now only scan LRI command on KBL and in inhibit context.
+         * It's good enough to support initializing mmio by lri command in
+         * vgpu inhibit context on KBL.
+         */
+        if (IS_KABYLAKE(s->vgpu->gvt->dev_priv) &&
+                        intel_gvt_mmio_is_in_ctx(gvt, offset) &&
+                        !strncmp(cmd, "lri", 3)) {
+                intel_gvt_hypervisor_read_gpa(s->vgpu,
+                        s->workload->ring_context_gpa + 12, &ctx_sr_ctl, 4);
+                /* check inhibit context */
+                if (ctx_sr_ctl & 1) {
+                        u32 data = cmd_val(s, index + 1);
+
+                        if (intel_gvt_mmio_has_mode_mask(s->vgpu->gvt, offset))
+                                intel_vgpu_mask_mmio_write(vgpu,
+                                                        offset, &data, 4);
+                        else
+                                vgpu_vreg(vgpu, offset) = data;
+                }
+        }
+
         /* TODO: Update the global mask if this MMIO is a masked-MMIO */
         intel_gvt_mmio_set_cmd_accessed(gvt, offset);
         return 0;
diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index 05d15a095310..858967daf04b 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -268,6 +268,8 @@ struct intel_gvt_mmio {
 #define F_CMD_ACCESSED  (1 << 5)
 /* This reg could be accessed by unaligned address */
 #define F_UNALIGN       (1 << 6)
+/* This reg is saved/restored in context */
+#define F_IN_CTX        (1 << 7)
 
         struct gvt_mmio_block *mmio_block;
         unsigned int num_mmio_block;
@@ -639,6 +641,33 @@ static inline bool intel_gvt_mmio_has_mode_mask(
         return gvt->mmio.mmio_attribute[offset >> 2] & F_MODE_MASK;
 }
 
+/**
+ * intel_gvt_mmio_is_in_ctx - check if a MMIO has in-ctx mask
+ * @gvt: a GVT device
+ * @offset: register offset
+ *
+ * Returns:
+ * True if a MMIO has a in-context mask, false if it isn't.
+ *
+ */
+static inline bool intel_gvt_mmio_is_in_ctx(
+                        struct intel_gvt *gvt, unsigned int offset)
+{
+        return gvt->mmio.mmio_attribute[offset >> 2] & F_IN_CTX;
+}
+
+/**
+ * intel_gvt_mmio_set_in_ctx - mask a MMIO in logical context
+ * @gvt: a GVT device
+ * @offset: register offset
+ *
+ */
+static inline void intel_gvt_mmio_set_in_ctx(
+                        struct intel_gvt *gvt, unsigned int offset)
+{
+        gvt->mmio.mmio_attribute[offset >> 2] |= F_IN_CTX;
+}
+
 int intel_gvt_debugfs_add_vgpu(struct intel_vgpu *vgpu);
 void intel_gvt_debugfs_remove_vgpu(struct intel_vgpu *vgpu);
 int intel_gvt_debugfs_init(struct intel_gvt *gvt);
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index bcbc47a88a70..8f1caacdc78a 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -3046,6 +3046,30 @@ int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 }
 
 /**
+ * intel_vgpu_mask_mmio_write - write mask register
+ * @vgpu: a vGPU
+ * @offset: access offset
+ * @p_data: write data buffer
+ * @bytes: access data length
+ *
+ * Returns:
+ * Zero on success, negative error code if failed.
+ */
+int intel_vgpu_mask_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
+                void *p_data, unsigned int bytes)
+{
+        u32 mask, old_vreg;
+
+        old_vreg = vgpu_vreg(vgpu, offset);
+        write_vreg(vgpu, offset, p_data, bytes);
+        mask = vgpu_vreg(vgpu, offset) >> 16;
+        vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) |
+                                (vgpu_vreg(vgpu, offset) & mask);
+
+        return 0;
+}
+
+/**
  * intel_gvt_in_force_nonpriv_whitelist - if a mmio is in whitelist to be
  * force-nopriv register
  *
diff --git a/drivers/gpu/drm/i915/gvt/mmio.h b/drivers/gpu/drm/i915/gvt/mmio.h
index 71b620875943..dac8c6401e26 100644
--- a/drivers/gpu/drm/i915/gvt/mmio.h
+++ b/drivers/gpu/drm/i915/gvt/mmio.h
@@ -98,4 +98,6 @@ bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt,
 int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset,
                            void *pdata, unsigned int bytes, bool is_read);
 
+int intel_vgpu_mask_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
+                                  void *p_data, unsigned int bytes);
 #endif
diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
index 0f949554d118..5ca9caf7552a 100644
--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
@@ -581,7 +581,9 @@ void intel_gvt_init_engine_mmio_context(struct intel_gvt *gvt)
 
         for (mmio = gvt->engine_mmio_list.mmio;
              i915_mmio_reg_valid(mmio->reg); mmio++) {
-                if (mmio->in_context)
+                if (mmio->in_context) {
                         gvt->engine_mmio_list.ctx_mmio_count[mmio->ring_id]++;
+                        intel_gvt_mmio_set_in_ctx(gvt, mmio->reg.reg);
+                }
         }
 }
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 52f3b91d14fd..71e1aa54f774 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -652,6 +652,7 @@ enum intel_sbi_destination {
 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
 #define QUIRK_INCREASE_T12_DELAY (1<<6)
+#define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
 
 struct intel_fbdev;
 struct intel_fbc_work;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 4a02747ac658..c16cb025755e 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1998,10 +1998,38 @@ static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
 
 static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
 {
-        u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
+        u32 hotplug_status = 0, hotplug_status_mask;
+        int i;
+
+        if (IS_G4X(dev_priv) ||
+            IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+                hotplug_status_mask = HOTPLUG_INT_STATUS_G4X |
+                        DP_AUX_CHANNEL_MASK_INT_STATUS_G4X;
+        else
+                hotplug_status_mask = HOTPLUG_INT_STATUS_I915;
 
-        if (hotplug_status)
+        /*
+         * We absolutely have to clear all the pending interrupt
+         * bits in PORT_HOTPLUG_STAT. Otherwise the ISR port
+         * interrupt bit won't have an edge, and the i965/g4x
+         * edge triggered IIR will not notice that an interrupt
+         * is still pending. We can't use PORT_HOTPLUG_EN to
+         * guarantee the edge as the act of toggling the enable
+         * bits can itself generate a new hotplug interrupt :(
+         */
+        for (i = 0; i < 10; i++) {
+                u32 tmp = I915_READ(PORT_HOTPLUG_STAT) & hotplug_status_mask;
+
+                if (tmp == 0)
+                        return hotplug_status;
+
+                hotplug_status |= tmp;
                 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
+        }
+
+        WARN_ONCE(1,
+                  "PORT_HOTPLUG_STAT did not clear (0x%08x)\n",
+                  I915_READ(PORT_HOTPLUG_STAT));
 
         return hotplug_status;
 }
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index f4a8598a2d39..fed26d6e4e27 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1782,15 +1782,24 @@ void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
 }
 
-void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
-                                       enum transcoder cpu_transcoder)
+void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
 {
+        struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+        enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
         i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
         uint32_t val = I915_READ(reg);
 
         val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
         val |= TRANS_DDI_PORT_NONE;
         I915_WRITE(reg, val);
+
+        if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
+            intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
+                DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
+                /* Quirk time at 100ms for reliable operation */
+                msleep(100);
+        }
 }
 
 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2cc6faa1daa8..dec0d60921bf 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5809,7 +5809,7 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
                 intel_ddi_set_vc_payload_alloc(intel_crtc->config, false);
 
         if (!transcoder_is_dsi(cpu_transcoder))
-                intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
+                intel_ddi_disable_transcoder_func(old_crtc_state);
 
         if (INTEL_GEN(dev_priv) >= 9)
                 skylake_scaler_disable(intel_crtc);
@@ -14646,6 +14646,18 @@ static void quirk_increase_t12_delay(struct drm_device *dev)
         DRM_INFO("Applying T12 delay quirk\n");
 }
 
+/*
+ * GeminiLake NUC HDMI outputs require additional off time
+ * this allows the onboard retimer to correctly sync to signal
+ */
+static void quirk_increase_ddi_disabled_time(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = to_i915(dev);
+
+        dev_priv->quirks |= QUIRK_INCREASE_DDI_DISABLED_TIME;
+        DRM_INFO("Applying Increase DDI Disabled quirk\n");
+}
+
 struct intel_quirk {
         int device;
         int subsystem_vendor;
@@ -14732,6 +14744,13 @@ static struct intel_quirk intel_quirks[] = {
 
         /* Toshiba Satellite P50-C-18C */
         { 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay },
+
+        /* GeminiLake NUC */
+        { 0x3185, 0x8086, 0x2072, quirk_increase_ddi_disabled_time },
+        { 0x3184, 0x8086, 0x2072, quirk_increase_ddi_disabled_time },
+        /* ASRock ITX*/
+        { 0x3185, 0x1849, 0x2212, quirk_increase_ddi_disabled_time },
+        { 0x3184, 0x1849, 0x2212, quirk_increase_ddi_disabled_time },
 };
 
 static void intel_init_quirks(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0361130500a6..b8eefbffc77d 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1388,8 +1388,7 @@ void hsw_fdi_link_train(struct intel_crtc *crtc,
 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
-void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
-                                       enum transcoder cpu_transcoder);
+void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state);
 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
 void intel_ddi_disable_pipe_clock(const  struct intel_crtc_state *crtc_state);
 struct intel_encoder *
diff --git a/drivers/gpu/drm/imx/imx-ldb.c b/drivers/gpu/drm/imx/imx-ldb.c
index 56dd7a9a8e25..dd5312b02a8d 100644
--- a/drivers/gpu/drm/imx/imx-ldb.c
+++ b/drivers/gpu/drm/imx/imx-ldb.c
@@ -612,6 +612,9 @@ static int imx_ldb_bind(struct device *dev, struct device *master, void *data)
                 return PTR_ERR(imx_ldb->regmap);
         }
 
+        /* disable LDB by resetting the control register to POR default */
+        regmap_write(imx_ldb->regmap, IOMUXC_GPR2, 0);
+
         imx_ldb->dev = dev;
 
         if (of_id)
@@ -652,14 +655,14 @@ static int imx_ldb_bind(struct device *dev, struct device *master, void *data)
                 if (ret || i < 0 || i > 1)
                         return -EINVAL;
 
+                if (!of_device_is_available(child))
+                        continue;
+
                 if (dual && i > 0) {
                         dev_warn(dev, "dual-channel mode, ignoring second output\n");
                         continue;
                 }
 
-                if (!of_device_is_available(child))
-                        continue;
-
                 channel = &imx_ldb->channel[i];
                 channel->ldb = imx_ldb;
                 channel->chno = i;
diff --git a/drivers/gpu/drm/nouveau/dispnv04/disp.c b/drivers/gpu/drm/nouveau/dispnv04/disp.c
index 501d2d290e9c..70dce544984e 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/disp.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/disp.c
@@ -55,6 +55,9 @@ nv04_display_create(struct drm_device *dev)
         nouveau_display(dev)->init = nv04_display_init;
         nouveau_display(dev)->fini = nv04_display_fini;
 
+        /* Pre-nv50 doesn't support atomic, so don't expose the ioctls */
+        dev->driver->driver_features &= ~DRIVER_ATOMIC;
+
         nouveau_hw_save_vga_fonts(dev, 1);
 
         nv04_crtc_create(dev, 0);
diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c
index b83465ae7c1b..9bae4db84cfb 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
@@ -1585,8 +1585,9 @@ nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
  *****************************************************************************/
 
 static void
-nv50_disp_atomic_commit_core(struct nouveau_drm *drm, u32 *interlock)
+nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock)
 {
+        struct nouveau_drm *drm = nouveau_drm(state->dev);
         struct nv50_disp *disp = nv50_disp(drm->dev);
         struct nv50_core *core = disp->core;
         struct nv50_mstm *mstm;
@@ -1618,6 +1619,22 @@ nv50_disp_atomic_commit_core(struct nouveau_drm *drm, u32 *interlock)
 }
 
 static void
+nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock)
+{
+        struct drm_plane_state *new_plane_state;
+        struct drm_plane *plane;
+        int i;
+
+        for_each_new_plane_in_state(state, plane, new_plane_state, i) {
+                struct nv50_wndw *wndw = nv50_wndw(plane);
+                if (interlock[wndw->interlock.type] & wndw->interlock.data) {
+                        if (wndw->func->update)
+                                wndw->func->update(wndw, interlock);
+                }
+        }
+}
+
+static void
 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
 {
         struct drm_device *dev = state->dev;
@@ -1684,7 +1701,8 @@ nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
                         help->disable(encoder);
                         interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
                         if (outp->flush_disable) {
-                                nv50_disp_atomic_commit_core(drm, interlock);
+                                nv50_disp_atomic_commit_wndw(state, interlock);
+                                nv50_disp_atomic_commit_core(state, interlock);
                                 memset(interlock, 0x00, sizeof(interlock));
                         }
                 }
@@ -1693,15 +1711,8 @@ nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
         /* Flush disable. */
         if (interlock[NV50_DISP_INTERLOCK_CORE]) {
                 if (atom->flush_disable) {
-                        for_each_new_plane_in_state(state, plane, new_plane_state, i) {
-                                struct nv50_wndw *wndw = nv50_wndw(plane);
-                                if (interlock[wndw->interlock.type] & wndw->interlock.data) {
-                                        if (wndw->func->update)
-                                                wndw->func->update(wndw, interlock);
-                                }
-                        }
-
-                        nv50_disp_atomic_commit_core(drm, interlock);
+                        nv50_disp_atomic_commit_wndw(state, interlock);
+                        nv50_disp_atomic_commit_core(state, interlock);
                         memset(interlock, 0x00, sizeof(interlock));
                 }
         }
@@ -1762,18 +1773,14 @@ nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
         }
 
         /* Flush update. */
-        for_each_new_plane_in_state(state, plane, new_plane_state, i) {
-                struct nv50_wndw *wndw = nv50_wndw(plane);
-                if (interlock[wndw->interlock.type] & wndw->interlock.data) {
-                        if (wndw->func->update)
-                                wndw->func->update(wndw, interlock);
-                }
-        }
+        nv50_disp_atomic_commit_wndw(state, interlock);
 
         if (interlock[NV50_DISP_INTERLOCK_CORE]) {
                 if (interlock[NV50_DISP_INTERLOCK_BASE] ||
+                    interlock[NV50_DISP_INTERLOCK_OVLY] ||
+                    interlock[NV50_DISP_INTERLOCK_WNDW] ||
                     !atom->state.legacy_cursor_update)
-                        nv50_disp_atomic_commit_core(drm, interlock);
+                        nv50_disp_atomic_commit_core(state, interlock);
                 else
                         disp->core->func->update(disp->core, interlock, false);
         }
@@ -1871,7 +1878,7 @@ nv50_disp_atomic_commit(struct drm_device *dev,
                 nv50_disp_atomic_commit_tail(state);
 
         drm_for_each_crtc(crtc, dev) {
-                if (crtc->state->enable) {
+                if (crtc->state->active) {
                         if (!drm->have_disp_power_ref) {
                                 drm->have_disp_power_ref = true;
                                 return 0;
@@ -2119,10 +2126,6 @@ nv50_display_destroy(struct drm_device *dev)
         kfree(disp);
 }
 
-MODULE_PARM_DESC(atomic, "Expose atomic ioctl (default: disabled)");
-static int nouveau_atomic = 0;
-module_param_named(atomic, nouveau_atomic, int, 0400);
-
 int
 nv50_display_create(struct drm_device *dev)
 {
@@ -2147,8 +2150,6 @@ nv50_display_create(struct drm_device *dev)
         disp->disp = &nouveau_display(dev)->disp;
         dev->mode_config.funcs = &nv50_disp_func;
         dev->driver->driver_features |= DRIVER_PREFER_XBGR_30BPP;
-        if (nouveau_atomic)
-                dev->driver->driver_features |= DRIVER_ATOMIC;
 
         /* small shared memory area we use for notifiers and semaphores */
         ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM,
diff --git a/drivers/gpu/drm/nouveau/nouveau_backlight.c b/drivers/gpu/drm/nouveau/nouveau_backlight.c
index debbbf0fd4bd..408b955e5c39 100644
--- a/drivers/gpu/drm/nouveau/nouveau_backlight.c
+++ b/drivers/gpu/drm/nouveau/nouveau_backlight.c
@@ -267,6 +267,7 @@ nouveau_backlight_init(struct drm_device *dev)
         struct nouveau_drm *drm = nouveau_drm(dev);
         struct nvif_device *device = &drm->client.device;
         struct drm_connector *connector;
+        struct drm_connector_list_iter conn_iter;
 
         INIT_LIST_HEAD(&drm->bl_connectors);
 
@@ -275,7 +276,8 @@ nouveau_backlight_init(struct drm_device *dev)
                 return 0;
         }
 
-        list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
+        drm_connector_list_iter_begin(dev, &conn_iter);
+        drm_for_each_connector_iter(connector, &conn_iter) {
                 if (connector->connector_type != DRM_MODE_CONNECTOR_LVDS &&
                     connector->connector_type != DRM_MODE_CONNECTOR_eDP)
                         continue;
@@ -292,7 +294,7 @@ nouveau_backlight_init(struct drm_device *dev)
                         break;
                 }
         }
-
+        drm_connector_list_iter_end(&conn_iter);
 
         return 0;
 }
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c
index 7b557c354307..af68eae4c626 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.c
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
@@ -1208,14 +1208,19 @@ nouveau_connector_create(struct drm_device *dev, int index)
         struct nouveau_display *disp = nouveau_display(dev);
         struct nouveau_connector *nv_connector = NULL;
         struct drm_connector *connector;
+        struct drm_connector_list_iter conn_iter;
         int type, ret = 0;
         bool dummy;
 
-        list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
+        drm_connector_list_iter_begin(dev, &conn_iter);
+        nouveau_for_each_non_mst_connector_iter(connector, &conn_iter) {
                 nv_connector = nouveau_connector(connector);
-                if (nv_connector->index == index)
+                if (nv_connector->index == index) {
+                        drm_connector_list_iter_end(&conn_iter);
                         return connector;
+                }
         }
+        drm_connector_list_iter_end(&conn_iter);
 
         nv_connector = kzalloc(sizeof(*nv_connector), GFP_KERNEL);
         if (!nv_connector)
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.h b/drivers/gpu/drm/nouveau/nouveau_connector.h
index a4d1a059bd3d..dc7454e7f19a 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.h
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.h
@@ -33,6 +33,7 @@
 #include <drm/drm_encoder.h>
 #include <drm/drm_dp_helper.h>
 #include "nouveau_crtc.h"
+#include "nouveau_encoder.h"
 
 struct nvkm_i2c_port;
 
@@ -60,19 +61,46 @@ static inline struct nouveau_connector *nouveau_connector(
         return container_of(con, struct nouveau_connector, base);
 }
 
+static inline bool
+nouveau_connector_is_mst(struct drm_connector *connector)
+{
+        const struct nouveau_encoder *nv_encoder;
+        const struct drm_encoder *encoder;
+
+        if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
+                return false;
+
+        nv_encoder = find_encoder(connector, DCB_OUTPUT_ANY);
+        if (!nv_encoder)
+                return false;
+
+        encoder = &nv_encoder->base.base;
+        return encoder->encoder_type == DRM_MODE_ENCODER_DPMST;
+}
+
+#define nouveau_for_each_non_mst_connector_iter(connector, iter) \
+        drm_for_each_connector_iter(connector, iter) \
+                for_each_if(!nouveau_connector_is_mst(connector))
+
 static inline struct nouveau_connector *
 nouveau_crtc_connector_get(struct nouveau_crtc *nv_crtc)
 {
         struct drm_device *dev = nv_crtc->base.dev;
         struct drm_connector *connector;
+        struct drm_connector_list_iter conn_iter;
+        struct nouveau_connector *nv_connector = NULL;
         struct drm_crtc *crtc = to_drm_crtc(nv_crtc);
 
-        list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
-                if (connector->encoder && connector->encoder->crtc == crtc)
-                        return nouveau_connector(connector);
+        drm_connector_list_iter_begin(dev, &conn_iter);
+        nouveau_for_each_non_mst_connector_iter(connector, &conn_iter) {
+                if (connector->encoder && connector->encoder->crtc == crtc) {
+                        nv_connector = nouveau_connector(connector);
+                        break;
+                }
         }
+        drm_connector_list_iter_end(&conn_iter);
 
-        return NULL;
+        return nv_connector;
 }
 
 struct drm_connector *
diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c
index 774b429142bc..ec7861457b84 100644
--- a/drivers/gpu/drm/nouveau/nouveau_display.c
+++ b/drivers/gpu/drm/nouveau/nouveau_display.c
@@ -404,6 +404,7 @@ nouveau_display_init(struct drm_device *dev)
         struct nouveau_display *disp = nouveau_display(dev);
         struct nouveau_drm *drm = nouveau_drm(dev);
         struct drm_connector *connector;
+        struct drm_connector_list_iter conn_iter;
         int ret;
 
         ret = disp->init(dev);
@@ -411,10 +412,12 @@ nouveau_display_init(struct drm_device *dev)
                 return ret;
 
         /* enable hotplug interrupts */
-        list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
+        drm_connector_list_iter_begin(dev, &conn_iter);
+        nouveau_for_each_non_mst_connector_iter(connector, &conn_iter) {
                 struct nouveau_connector *conn = nouveau_connector(connector);
                 nvif_notify_get(&conn->hpd);
         }
+        drm_connector_list_iter_end(&conn_iter);
 
         /* enable flip completion events */
         nvif_notify_get(&drm->flip);
@@ -427,6 +430,7 @@ nouveau_display_fini(struct drm_device *dev, bool suspend)
         struct nouveau_display *disp = nouveau_display(dev);
         struct nouveau_drm *drm = nouveau_drm(dev);
         struct drm_connector *connector;
+        struct drm_connector_list_iter conn_iter;
 
         if (!suspend) {
                 if (drm_drv_uses_atomic_modeset(dev))
@@ -439,10 +443,12 @@ nouveau_display_fini(struct drm_device *dev, bool suspend)
         nvif_notify_put(&drm->flip);
 
         /* disable hotplug interrupts */
-        list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
+        drm_connector_list_iter_begin(dev, &conn_iter);
+        nouveau_for_each_non_mst_connector_iter(connector, &conn_iter) {
                 struct nouveau_connector *conn = nouveau_connector(connector);
                 nvif_notify_put(&conn->hpd);
         }
+        drm_connector_list_iter_end(&conn_iter);
 
         drm_kms_helper_poll_disable(dev);
         disp->fini(dev);
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c
index 775443c9af94..f5d3158f0378 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@ -81,6 +81,10 @@ MODULE_PARM_DESC(modeset, "enable driver (default: auto, "
 int nouveau_modeset = -1;
 module_param_named(modeset, nouveau_modeset, int, 0400);
 
+MODULE_PARM_DESC(atomic, "Expose atomic ioctl (default: disabled)");
+static int nouveau_atomic = 0;
+module_param_named(atomic, nouveau_atomic, int, 0400);
+
 MODULE_PARM_DESC(runpm, "disable (0), force enable (1), optimus only default (-1)");
 static int nouveau_runtime_pm = -1;
 module_param_named(runpm, nouveau_runtime_pm, int, 0400);
@@ -509,6 +513,9 @@ static int nouveau_drm_probe(struct pci_dev *pdev,
 
         pci_set_master(pdev);
 
+        if (nouveau_atomic)
+                driver_pci.driver_features |= DRIVER_ATOMIC;
+
         ret = drm_get_pci_dev(pdev, pent, &driver_pci);
         if (ret) {
                 nvkm_device_del(&device);
@@ -874,22 +881,11 @@ nouveau_pmops_runtime_resume(struct device *dev)
 static int
 nouveau_pmops_runtime_idle(struct device *dev)
 {
-        struct pci_dev *pdev = to_pci_dev(dev);
-        struct drm_device *drm_dev = pci_get_drvdata(pdev);
-        struct nouveau_drm *drm = nouveau_drm(drm_dev);
-        struct drm_crtc *crtc;
-
         if (!nouveau_pmops_runtime()) {
                 pm_runtime_forbid(dev);
                 return -EBUSY;
         }
 
-        list_for_each_entry(crtc, &drm->dev->mode_config.crtc_list, head) {
-                if (crtc->enabled) {
-                        DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
-                        return -EBUSY;
-                }
-        }
         pm_runtime_mark_last_busy(dev);
         pm_runtime_autosuspend(dev);
         /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c
index 300daee74209..e6ccafcb9c41 100644
--- a/drivers/gpu/drm/nouveau/nouveau_gem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_gem.c
@@ -616,7 +616,7 @@ nouveau_gem_pushbuf_reloc_apply(struct nouveau_cli *cli,
                 struct nouveau_bo *nvbo;
                 uint32_t data;
 
-                if (unlikely(r->bo_index > req->nr_buffers)) {
+                if (unlikely(r->bo_index >= req->nr_buffers)) {
                         NV_PRINTK(err, cli, "reloc bo index invalid\n");
                         ret = -EINVAL;
                         break;
@@ -626,7 +626,7 @@ nouveau_gem_pushbuf_reloc_apply(struct nouveau_cli *cli,
                 if (b->presumed.valid)
                         continue;
 
-                if (unlikely(r->reloc_bo_index > req->nr_buffers)) {
+                if (unlikely(r->reloc_bo_index >= req->nr_buffers)) {
                         NV_PRINTK(err, cli, "reloc container bo index invalid\n");
                         ret = -EINVAL;
                         break;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c
index 73b5d46104bd..434d2fc5bb1c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c
@@ -140,6 +140,9 @@ nvkm_fb_init(struct nvkm_subdev *subdev)
         if (fb->func->init)
                 fb->func->init(fb);
 
+        if (fb->func->init_remapper)
+                fb->func->init_remapper(fb);
+
         if (fb->func->init_page) {
                 ret = fb->func->init_page(fb);
                 if (WARN_ON(ret))
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp100.c
index dffe1f5e1071..8205ce436b3e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp100.c
@@ -37,6 +37,14 @@ gp100_fb_init_unkn(struct nvkm_fb *base)
 }
 
 void
+gp100_fb_init_remapper(struct nvkm_fb *fb)
+{
+        struct nvkm_device *device = fb->subdev.device;
+        /* Disable address remapper. */
+        nvkm_mask(device, 0x100c14, 0x00040000, 0x00000000);
+}
+
+void
 gp100_fb_init(struct nvkm_fb *base)
 {
         struct gf100_fb *fb = gf100_fb(base);
@@ -56,6 +64,7 @@ gp100_fb = {
         .dtor = gf100_fb_dtor,
         .oneinit = gf100_fb_oneinit,
         .init = gp100_fb_init,
+        .init_remapper = gp100_fb_init_remapper,
         .init_page = gm200_fb_init_page,
         .init_unkn = gp100_fb_init_unkn,
         .ram_new = gp100_ram_new,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp102.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp102.c
index b84b9861ef26..b4d74e815674 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp102.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp102.c
@@ -31,6 +31,7 @@ gp102_fb = {
         .dtor = gf100_fb_dtor,
         .oneinit = gf100_fb_oneinit,
         .init = gp100_fb_init,
+        .init_remapper = gp100_fb_init_remapper,
         .init_page = gm200_fb_init_page,
         .ram_new = gp100_ram_new,
 };
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h
index 2857f31466bf..1e4ad61c19e1 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h
@@ -11,6 +11,7 @@ struct nvkm_fb_func {
         u32 (*tags)(struct nvkm_fb *);
         int (*oneinit)(struct nvkm_fb *);
         void (*init)(struct nvkm_fb *);
+        void (*init_remapper)(struct nvkm_fb *);
         int (*init_page)(struct nvkm_fb *);
         void (*init_unkn)(struct nvkm_fb *);
         void (*intr)(struct nvkm_fb *);
@@ -69,5 +70,6 @@ int gf100_fb_init_page(struct nvkm_fb *);
 
 int gm200_fb_init_page(struct nvkm_fb *);
 
+void gp100_fb_init_remapper(struct nvkm_fb *);
 void gp100_fb_init_unkn(struct nvkm_fb *);
 #endif
diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile
index 2589f4acd5ae..9c81301d0eed 100644
--- a/drivers/gpu/drm/sun4i/Makefile
+++ b/drivers/gpu/drm/sun4i/Makefile
@@ -32,7 +32,10 @@ obj-$(CONFIG_DRM_SUN4I)		+= sun4i-tcon.o
 obj-$(CONFIG_DRM_SUN4I)         += sun4i_tv.o
 obj-$(CONFIG_DRM_SUN4I)         += sun6i_drc.o
 
-obj-$(CONFIG_DRM_SUN4I_BACKEND) += sun4i-backend.o sun4i-frontend.o
+obj-$(CONFIG_DRM_SUN4I_BACKEND) += sun4i-backend.o
+ifdef CONFIG_DRM_SUN4I_BACKEND
+obj-$(CONFIG_DRM_SUN4I)         += sun4i-frontend.o
+endif
 obj-$(CONFIG_DRM_SUN4I_HDMI)    += sun4i-drm-hdmi.o
 obj-$(CONFIG_DRM_SUN6I_DSI)     += sun6i-dsi.o
 obj-$(CONFIG_DRM_SUN8I_DW_HDMI) += sun8i-drm-hdmi.o
diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
index 776c1513e582..a2bd5876c633 100644
--- a/drivers/gpu/drm/tegra/drm.c
+++ b/drivers/gpu/drm/tegra/drm.c
@@ -398,7 +398,7 @@ int tegra_drm_submit(struct tegra_drm_context *context,
                  * unaligned offset is malformed and cause commands stream
                  * corruption on the buffer address relocation.
                  */
-                if (offset & 3 || offset >= obj->gem.size) {
+                if (offset & 3 || offset > obj->gem.size) {
                         err = -EINVAL;
                         goto fail;
                 }
diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c
index 1d34619eb3fe..a951ec75d01f 100644
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
@@ -320,6 +320,9 @@ static int vc4_plane_setup_clipping_and_scaling(struct drm_plane_state *state)
                         vc4_state->x_scaling[0] = VC4_SCALING_TPZ;
                 if (vc4_state->y_scaling[0] == VC4_SCALING_NONE)
                         vc4_state->y_scaling[0] = VC4_SCALING_TPZ;
+        } else {
+                vc4_state->x_scaling[1] = VC4_SCALING_NONE;
+                vc4_state->y_scaling[1] = VC4_SCALING_NONE;
         }
 
         vc4_state->is_unity = (vc4_state->x_scaling[0] == VC4_SCALING_NONE &&
diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c
index f1d5f76e9c33..d88073e7d22d 100644
--- a/drivers/gpu/host1x/dev.c
+++ b/drivers/gpu/host1x/dev.c
@@ -218,6 +218,9 @@ static int host1x_probe(struct platform_device *pdev)
                 return err;
         }
 
+        if (IS_ENABLED(CONFIG_TEGRA_HOST1X_FIREWALL))
+                goto skip_iommu;
+
         host->group = iommu_group_get(&pdev->dev);
         if (host->group) {
                 struct iommu_domain_geometry *geometry;
diff --git a/drivers/gpu/host1x/job.c b/drivers/gpu/host1x/job.c
index e2f4a4d93d20..527a1cddb14f 100644
--- a/drivers/gpu/host1x/job.c
+++ b/drivers/gpu/host1x/job.c
@@ -569,7 +569,8 @@ void host1x_job_unpin(struct host1x_job *job)
         for (i = 0; i < job->num_unpins; i++) {
                 struct host1x_job_unpin_data *unpin = &job->unpins[i];
 
-                if (!IS_ENABLED(CONFIG_TEGRA_HOST1X_FIREWALL) && host->domain) {
+                if (!IS_ENABLED(CONFIG_TEGRA_HOST1X_FIREWALL) &&
+                    unpin->size && host->domain) {
                         iommu_unmap(host->domain, job->addr_phys[i],
                                     unpin->size);
                         free_iova(&host->iova,
diff --git a/drivers/gpu/ipu-v3/ipu-csi.c b/drivers/gpu/ipu-v3/ipu-csi.c
index caa05b0702e1..5450a2db1219 100644
--- a/drivers/gpu/ipu-v3/ipu-csi.c
+++ b/drivers/gpu/ipu-v3/ipu-csi.c
@@ -339,7 +339,8 @@ static void fill_csi_bus_cfg(struct ipu_csi_bus_config *csicfg,
                 break;
         case V4L2_MBUS_BT656:
                 csicfg->ext_vsync = 0;
-                if (V4L2_FIELD_HAS_BOTH(mbus_fmt->field))
+                if (V4L2_FIELD_HAS_BOTH(mbus_fmt->field) ||
+                    mbus_fmt->field == V4L2_FIELD_ALTERNATE)
                         csicfg->clk_mode = IPU_CSI_CLK_MODE_CCIR656_INTERLACED;
                 else
                         csicfg->clk_mode = IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE;