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authorEvan Quan <evan.quan@amd.com>2018-09-04 22:03:13 -0400
committerAlex Deucher <alexander.deucher@amd.com>2018-09-10 23:45:05 -0400
commit28968375a7ec95562e402b43f795e04fd320ae18 (patch)
treefccce429bbe9d15b706bf35d70d487c7e2436daa /drivers/gpu
parent989edc699f65bb1f32a31c03619abff5390b9c42 (diff)
drm/amd/powerplay: fix compile warning for wrong data type V2
do_div expects the 1st argument in 64bit instead of 32bit. Drop the usage of do_div as it seems unnecessary. V2: drop usage of do_div completely Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
index 3efd59e984a3..1e65ac01e0f5 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
@@ -1195,7 +1195,7 @@ static int vega20_set_sclk_od(
1195 int ret = 0; 1195 int ret = 0;
1196 1196
1197 od_sclk = golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value * value; 1197 od_sclk = golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value * value;
1198 do_div(od_sclk, 100); 1198 od_sclk /= 100;
1199 od_sclk += golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value; 1199 od_sclk += golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
1200 1200
1201 ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_GFXCLK_FMAX, od_sclk); 1201 ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_GFXCLK_FMAX, od_sclk);
@@ -1242,7 +1242,7 @@ static int vega20_set_mclk_od(
1242 int ret = 0; 1242 int ret = 0;
1243 1243
1244 od_mclk = golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value * value; 1244 od_mclk = golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value * value;
1245 do_div(od_mclk, 100); 1245 od_mclk /= 100;
1246 od_mclk += golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value; 1246 od_mclk += golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
1247 1247
1248 ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_UCLK_FMAX, od_mclk); 1248 ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_UCLK_FMAX, od_mclk);