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authorRex Zhu <Rex.Zhu@amd.com>2016-08-10 23:01:01 -0400
committerAlex Deucher <alexander.deucher@amd.com>2016-09-19 13:22:12 -0400
commit1486022088dea351805e4db4fc76c4d7c68733d6 (patch)
tree8c37221805728c4fd175347206293cb284fed29f /drivers/gpu
parentb859c2070354ad8a2512e1524533d9f3291174c7 (diff)
drm/amd/powerplay: implement fw image related smum interface for tonga.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c2
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/Makefile2
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c3214
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.h60
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c17
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.h37
6 files changed, 3329 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
index 42783bf7647c..3110bf0eeacc 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
@@ -800,7 +800,7 @@ static int tonga_process_firmware_header(struct pp_hwmgr *hwmgr)
800 800
801 if (0 == result) { 801 if (0 == result) {
802 data->soft_regs_start = tmp; 802 data->soft_regs_start = tmp;
803 tonga_smu->ulSoftRegsStart = tmp; 803 tonga_smu->soft_regs_start = tmp;
804 } 804 }
805 805
806 error |= (0 != result); 806 error |= (0 != result);
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/Makefile b/drivers/gpu/drm/amd/powerplay/smumgr/Makefile
index 7561239eb874..2ff4aa031b1a 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/Makefile
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/Makefile
@@ -3,7 +3,7 @@
3# It provides the smu management services for the driver. 3# It provides the smu management services for the driver.
4 4
5SMU_MGR = smumgr.o cz_smumgr.o tonga_smumgr.o fiji_smumgr.o fiji_smc.o\ 5SMU_MGR = smumgr.o cz_smumgr.o tonga_smumgr.o fiji_smumgr.o fiji_smc.o\
6 polaris10_smumgr.o iceland_smumgr.o polaris10_smc.o 6 polaris10_smumgr.o iceland_smumgr.o polaris10_smc.o tonga_smc.o
7 7
8AMD_PP_SMUMGR = $(addprefix $(AMD_PP_PATH)/smumgr/,$(SMU_MGR)) 8AMD_PP_SMUMGR = $(addprefix $(AMD_PP_PATH)/smumgr/,$(SMU_MGR))
9 9
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c
new file mode 100644
index 000000000000..3acdbffed88c
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c
@@ -0,0 +1,3214 @@
1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
8 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
9 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
10 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
11 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
12 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
13 * OTHER DEALINGS IN THE SOFTWARE.
14 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice shall be included in
19 * all copies or substantial portions of the Software.
20 *
21 *
22 */
23
24#include "tonga_smc.h"
25#include "smu7_dyn_defaults.h"
26
27#include "smu7_hwmgr.h"
28#include "hardwaremanager.h"
29#include "ppatomctrl.h"
30#include "pp_debug.h"
31#include "cgs_common.h"
32#include "atombios.h"
33#include "tonga_smumgr.h"
34#include "pppcielanes.h"
35#include "pp_endian.h"
36#include "smu7_ppsmc.h"
37
38#include "smu72_discrete.h"
39
40#include "smu/smu_7_1_2_d.h"
41#include "smu/smu_7_1_2_sh_mask.h"
42
43#include "gmc/gmc_8_1_d.h"
44#include "gmc/gmc_8_1_sh_mask.h"
45
46#include "bif/bif_5_0_d.h"
47#include "bif/bif_5_0_sh_mask.h"
48
49#include "dce/dce_10_0_d.h"
50#include "dce/dce_10_0_sh_mask.h"
51
52
53#define VOLTAGE_SCALE 4
54#define POWERTUNE_DEFAULT_SET_MAX 1
55#define VOLTAGE_VID_OFFSET_SCALE1 625
56#define VOLTAGE_VID_OFFSET_SCALE2 100
57#define MC_CG_ARB_FREQ_F1 0x0b
58#define VDDC_VDDCI_DELTA 200
59
60
61static struct tonga_pt_defaults tonga_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
62/* sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
63 * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT
64 */
65 {1, 0xF, 0xFD, 0x19,
66 5, 45, 0, 0xB0000,
67 {0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8,
68 0xC9, 0xC9, 0x2F, 0x4D, 0x61},
69 {0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203,
70 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4}
71 },
72};
73
74/* [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ] */
75static const uint16_t tonga_clock_stretcher_lookup_table[2][4] = {
76 {600, 1050, 3, 0},
77 {600, 1050, 6, 1}
78};
79
80/* [FF, SS] type, [] 4 voltage ranges,
81 * and [Floor Freq, Boundary Freq, VID min , VID max]
82 */
83static const uint32_t tonga_clock_stretcher_ddt_table[2][4][4] = {
84 { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
85 { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} }
86};
87
88/* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] */
89static const uint8_t tonga_clock_stretch_amount_conversion[2][6] = {
90 {0, 1, 3, 2, 4, 5},
91 {0, 2, 4, 5, 6, 5}
92};
93
94/* PPGen has the gain setting generated in x * 100 unit
95 * This function is to convert the unit to x * 4096(0x1000) unit.
96 * This is the unit expected by SMC firmware
97 */
98
99
100static int tonga_get_dependecy_volt_by_clk(struct pp_hwmgr *hwmgr,
101 phm_ppt_v1_clock_voltage_dependency_table *allowed_clock_voltage_table,
102 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
103{
104 uint32_t i = 0;
105 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
106 struct phm_ppt_v1_information *pptable_info =
107 (struct phm_ppt_v1_information *)(hwmgr->pptable);
108
109 /* clock - voltage dependency table is empty table */
110 if (allowed_clock_voltage_table->count == 0)
111 return -EINVAL;
112
113 for (i = 0; i < allowed_clock_voltage_table->count; i++) {
114 /* find first sclk bigger than request */
115 if (allowed_clock_voltage_table->entries[i].clk >= clock) {
116 voltage->VddGfx = phm_get_voltage_index(
117 pptable_info->vddgfx_lookup_table,
118 allowed_clock_voltage_table->entries[i].vddgfx);
119 voltage->Vddc = phm_get_voltage_index(
120 pptable_info->vddc_lookup_table,
121 allowed_clock_voltage_table->entries[i].vddc);
122
123 if (allowed_clock_voltage_table->entries[i].vddci)
124 voltage->Vddci =
125 phm_get_voltage_id(&data->vddci_voltage_table, allowed_clock_voltage_table->entries[i].vddci);
126 else
127 voltage->Vddci =
128 phm_get_voltage_id(&data->vddci_voltage_table,
129 allowed_clock_voltage_table->entries[i].vddc - VDDC_VDDCI_DELTA);
130
131
132 if (allowed_clock_voltage_table->entries[i].mvdd)
133 *mvdd = (uint32_t) allowed_clock_voltage_table->entries[i].mvdd;
134
135 voltage->Phases = 1;
136 return 0;
137 }
138 }
139
140 /* sclk is bigger than max sclk in the dependence table */
141 voltage->VddGfx = phm_get_voltage_index(pptable_info->vddgfx_lookup_table,
142 allowed_clock_voltage_table->entries[i-1].vddgfx);
143 voltage->Vddc = phm_get_voltage_index(pptable_info->vddc_lookup_table,
144 allowed_clock_voltage_table->entries[i-1].vddc);
145
146 if (allowed_clock_voltage_table->entries[i-1].vddci)
147 voltage->Vddci = phm_get_voltage_id(&data->vddci_voltage_table,
148 allowed_clock_voltage_table->entries[i-1].vddci);
149
150 if (allowed_clock_voltage_table->entries[i-1].mvdd)
151 *mvdd = (uint32_t) allowed_clock_voltage_table->entries[i-1].mvdd;
152
153 return 0;
154}
155
156
157/**
158 * Vddc table preparation for SMC.
159 *
160 * @param hwmgr the address of the hardware manager
161 * @param table the SMC DPM table structure to be populated
162 * @return always 0
163 */
164static int tonga_populate_smc_vddc_table(struct pp_hwmgr *hwmgr,
165 SMU72_Discrete_DpmTable *table)
166{
167 unsigned int count;
168 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
169
170 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
171 table->VddcLevelCount = data->vddc_voltage_table.count;
172 for (count = 0; count < table->VddcLevelCount; count++) {
173 table->VddcTable[count] =
174 PP_HOST_TO_SMC_US(data->vddc_voltage_table.entries[count].value * VOLTAGE_SCALE);
175 }
176 CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount);
177 }
178 return 0;
179}
180
181/**
182 * VddGfx table preparation for SMC.
183 *
184 * @param hwmgr the address of the hardware manager
185 * @param table the SMC DPM table structure to be populated
186 * @return always 0
187 */
188static int tonga_populate_smc_vdd_gfx_table(struct pp_hwmgr *hwmgr,
189 SMU72_Discrete_DpmTable *table)
190{
191 unsigned int count;
192 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
193
194 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
195 table->VddGfxLevelCount = data->vddgfx_voltage_table.count;
196 for (count = 0; count < data->vddgfx_voltage_table.count; count++) {
197 table->VddGfxTable[count] =
198 PP_HOST_TO_SMC_US(data->vddgfx_voltage_table.entries[count].value * VOLTAGE_SCALE);
199 }
200 CONVERT_FROM_HOST_TO_SMC_UL(table->VddGfxLevelCount);
201 }
202 return 0;
203}
204
205/**
206 * Vddci table preparation for SMC.
207 *
208 * @param *hwmgr The address of the hardware manager.
209 * @param *table The SMC DPM table structure to be populated.
210 * @return 0
211 */
212static int tonga_populate_smc_vdd_ci_table(struct pp_hwmgr *hwmgr,
213 SMU72_Discrete_DpmTable *table)
214{
215 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
216 uint32_t count;
217
218 table->VddciLevelCount = data->vddci_voltage_table.count;
219 for (count = 0; count < table->VddciLevelCount; count++) {
220 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
221 table->VddciTable[count] =
222 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE);
223 } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
224 table->SmioTable1.Pattern[count].Voltage =
225 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE);
226 /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level. */
227 table->SmioTable1.Pattern[count].Smio =
228 (uint8_t) count;
229 table->Smio[count] |=
230 data->vddci_voltage_table.entries[count].smio_low;
231 table->VddciTable[count] =
232 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE);
233 }
234 }
235
236 table->SmioMask1 = data->vddci_voltage_table.mask_low;
237 CONVERT_FROM_HOST_TO_SMC_UL(table->VddciLevelCount);
238
239 return 0;
240}
241
242/**
243 * Mvdd table preparation for SMC.
244 *
245 * @param *hwmgr The address of the hardware manager.
246 * @param *table The SMC DPM table structure to be populated.
247 * @return 0
248 */
249static int tonga_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
250 SMU72_Discrete_DpmTable *table)
251{
252 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
253 uint32_t count;
254
255 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
256 table->MvddLevelCount = data->mvdd_voltage_table.count;
257 for (count = 0; count < table->MvddLevelCount; count++) {
258 table->SmioTable2.Pattern[count].Voltage =
259 PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
260 /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
261 table->SmioTable2.Pattern[count].Smio =
262 (uint8_t) count;
263 table->Smio[count] |=
264 data->mvdd_voltage_table.entries[count].smio_low;
265 }
266 table->SmioMask2 = data->mvdd_voltage_table.mask_low;
267
268 CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount);
269 }
270
271 return 0;
272}
273
274/**
275 * Preparation of vddc and vddgfx CAC tables for SMC.
276 *
277 * @param hwmgr the address of the hardware manager
278 * @param table the SMC DPM table structure to be populated
279 * @return always 0
280 */
281static int tonga_populate_cac_tables(struct pp_hwmgr *hwmgr,
282 SMU72_Discrete_DpmTable *table)
283{
284 uint32_t count;
285 uint8_t index = 0;
286 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
287 struct phm_ppt_v1_information *pptable_info =
288 (struct phm_ppt_v1_information *)(hwmgr->pptable);
289 struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table =
290 pptable_info->vddgfx_lookup_table;
291 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table =
292 pptable_info->vddc_lookup_table;
293
294 /* table is already swapped, so in order to use the value from it
295 * we need to swap it back.
296 */
297 uint32_t vddc_level_count = PP_SMC_TO_HOST_UL(table->VddcLevelCount);
298 uint32_t vddgfx_level_count = PP_SMC_TO_HOST_UL(table->VddGfxLevelCount);
299
300 for (count = 0; count < vddc_level_count; count++) {
301 /* We are populating vddc CAC data to BapmVddc table in split and merged mode */
302 index = phm_get_voltage_index(vddc_lookup_table,
303 data->vddc_voltage_table.entries[count].value);
304 table->BapmVddcVidLoSidd[count] =
305 convert_to_vid(vddc_lookup_table->entries[index].us_cac_low);
306 table->BapmVddcVidHiSidd[count] =
307 convert_to_vid(vddc_lookup_table->entries[index].us_cac_mid);
308 table->BapmVddcVidHiSidd2[count] =
309 convert_to_vid(vddc_lookup_table->entries[index].us_cac_high);
310 }
311
312 if ((data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2)) {
313 /* We are populating vddgfx CAC data to BapmVddgfx table in split mode */
314 for (count = 0; count < vddgfx_level_count; count++) {
315 index = phm_get_voltage_index(vddgfx_lookup_table,
316 convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_mid));
317 table->BapmVddGfxVidHiSidd2[count] =
318 convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_high);
319 }
320 } else {
321 for (count = 0; count < vddc_level_count; count++) {
322 index = phm_get_voltage_index(vddc_lookup_table,
323 data->vddc_voltage_table.entries[count].value);
324 table->BapmVddGfxVidLoSidd[count] =
325 convert_to_vid(vddc_lookup_table->entries[index].us_cac_low);
326 table->BapmVddGfxVidHiSidd[count] =
327 convert_to_vid(vddc_lookup_table->entries[index].us_cac_mid);
328 table->BapmVddGfxVidHiSidd2[count] =
329 convert_to_vid(vddc_lookup_table->entries[index].us_cac_high);
330 }
331 }
332
333 return 0;
334}
335
336/**
337 * Preparation of voltage tables for SMC.
338 *
339 * @param hwmgr the address of the hardware manager
340 * @param table the SMC DPM table structure to be populated
341 * @return always 0
342 */
343
344static int tonga_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
345 SMU72_Discrete_DpmTable *table)
346{
347 int result;
348
349 result = tonga_populate_smc_vddc_table(hwmgr, table);
350 PP_ASSERT_WITH_CODE(0 == result,
351 "can not populate VDDC voltage table to SMC",
352 return -EINVAL);
353
354 result = tonga_populate_smc_vdd_ci_table(hwmgr, table);
355 PP_ASSERT_WITH_CODE(0 == result,
356 "can not populate VDDCI voltage table to SMC",
357 return -EINVAL);
358
359 result = tonga_populate_smc_vdd_gfx_table(hwmgr, table);
360 PP_ASSERT_WITH_CODE(0 == result,
361 "can not populate VDDGFX voltage table to SMC",
362 return -EINVAL);
363
364 result = tonga_populate_smc_mvdd_table(hwmgr, table);
365 PP_ASSERT_WITH_CODE(0 == result,
366 "can not populate MVDD voltage table to SMC",
367 return -EINVAL);
368
369 result = tonga_populate_cac_tables(hwmgr, table);
370 PP_ASSERT_WITH_CODE(0 == result,
371 "can not populate CAC voltage tables to SMC",
372 return -EINVAL);
373
374 return 0;
375}
376
377static int tonga_populate_ulv_level(struct pp_hwmgr *hwmgr,
378 struct SMU72_Discrete_Ulv *state)
379{
380 struct phm_ppt_v1_information *table_info =
381 (struct phm_ppt_v1_information *)(hwmgr->pptable);
382
383 state->CcPwrDynRm = 0;
384 state->CcPwrDynRm1 = 0;
385
386 state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
387 state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
388 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
389
390 state->VddcPhase = 1;
391
392 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
393 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
394 CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
395
396 return 0;
397}
398
399static int tonga_populate_ulv_state(struct pp_hwmgr *hwmgr,
400 struct SMU72_Discrete_DpmTable *table)
401{
402 return tonga_populate_ulv_level(hwmgr, &table->Ulv);
403}
404
405static int tonga_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU72_Discrete_DpmTable *table)
406{
407 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
408 struct smu7_dpm_table *dpm_table = &data->dpm_table;
409 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend);
410 uint32_t i;
411
412 /* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */
413 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
414 table->LinkLevel[i].PcieGenSpeed =
415 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
416 table->LinkLevel[i].PcieLaneCount =
417 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
418 table->LinkLevel[i].EnabledForActivity =
419 1;
420 table->LinkLevel[i].SPC =
421 (uint8_t)(data->pcie_spc_cap & 0xff);
422 table->LinkLevel[i].DownThreshold =
423 PP_HOST_TO_SMC_UL(5);
424 table->LinkLevel[i].UpThreshold =
425 PP_HOST_TO_SMC_UL(30);
426 }
427
428 smu_data->smc_state_table.LinkLevelCount =
429 (uint8_t)dpm_table->pcie_speed_table.count;
430 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
431 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
432
433 return 0;
434}
435
436/**
437 * Calculates the SCLK dividers using the provided engine clock
438 *
439 * @param hwmgr the address of the hardware manager
440 * @param engine_clock the engine clock to use to populate the structure
441 * @param sclk the SMC SCLK structure to be populated
442 */
443static int tonga_calculate_sclk_params(struct pp_hwmgr *hwmgr,
444 uint32_t engine_clock, SMU72_Discrete_GraphicsLevel *sclk)
445{
446 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
447 pp_atomctrl_clock_dividers_vi dividers;
448 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
449 uint32_t spll_func_cntl_3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
450 uint32_t spll_func_cntl_4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
451 uint32_t cg_spll_spread_spectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
452 uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
453 uint32_t reference_clock;
454 uint32_t reference_divider;
455 uint32_t fbdiv;
456 int result;
457
458 /* get the engine clock dividers for this clock value*/
459 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, &dividers);
460
461 PP_ASSERT_WITH_CODE(result == 0,
462 "Error retrieving Engine Clock dividers from VBIOS.", return result);
463
464 /* To get FBDIV we need to multiply this by 16384 and divide it by Fref.*/
465 reference_clock = atomctrl_get_reference_clock(hwmgr);
466
467 reference_divider = 1 + dividers.uc_pll_ref_div;
468
469 /* low 14 bits is fraction and high 12 bits is divider*/
470 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
471
472 /* SPLL_FUNC_CNTL setup*/
473 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
474 CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div);
475 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
476 CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div);
477
478 /* SPLL_FUNC_CNTL_3 setup*/
479 spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
480 CG_SPLL_FUNC_CNTL_3, SPLL_FB_DIV, fbdiv);
481
482 /* set to use fractional accumulation*/
483 spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
484 CG_SPLL_FUNC_CNTL_3, SPLL_DITHEN, 1);
485
486 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
487 PHM_PlatformCaps_EngineSpreadSpectrumSupport)) {
488 pp_atomctrl_internal_ss_info ss_info;
489
490 uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div;
491 if (0 == atomctrl_get_engine_clock_spread_spectrum(hwmgr, vcoFreq, &ss_info)) {
492 /*
493 * ss_info.speed_spectrum_percentage -- in unit of 0.01%
494 * ss_info.speed_spectrum_rate -- in unit of khz
495 */
496 /* clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2 */
497 uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate);
498
499 /* clkv = 2 * D * fbdiv / NS */
500 uint32_t clkV = 4 * ss_info.speed_spectrum_percentage * fbdiv / (clkS * 10000);
501
502 cg_spll_spread_spectrum =
503 PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, CLKS, clkS);
504 cg_spll_spread_spectrum =
505 PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, SSEN, 1);
506 cg_spll_spread_spectrum_2 =
507 PHM_SET_FIELD(cg_spll_spread_spectrum_2, CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clkV);
508 }
509 }
510
511 sclk->SclkFrequency = engine_clock;
512 sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
513 sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
514 sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
515 sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2;
516 sclk->SclkDid = (uint8_t)dividers.pll_post_divider;
517
518 return 0;
519}
520
521/**
522 * Populates single SMC SCLK structure using the provided engine clock
523 *
524 * @param hwmgr the address of the hardware manager
525 * @param engine_clock the engine clock to use to populate the structure
526 * @param sclk the SMC SCLK structure to be populated
527 */
528static int tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
529 uint32_t engine_clock,
530 uint16_t sclk_activity_level_threshold,
531 SMU72_Discrete_GraphicsLevel *graphic_level)
532{
533 int result;
534 uint32_t mvdd;
535 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
536 struct phm_ppt_v1_information *pptable_info =
537 (struct phm_ppt_v1_information *)(hwmgr->pptable);
538
539 result = tonga_calculate_sclk_params(hwmgr, engine_clock, graphic_level);
540
541 /* populate graphics levels*/
542 result = tonga_get_dependecy_volt_by_clk(hwmgr,
543 pptable_info->vdd_dep_on_sclk, engine_clock,
544 &graphic_level->MinVoltage, &mvdd);
545 PP_ASSERT_WITH_CODE((0 == result),
546 "can not find VDDC voltage value for VDDC "
547 "engine clock dependency table", return result);
548
549 /* SCLK frequency in units of 10KHz*/
550 graphic_level->SclkFrequency = engine_clock;
551 /* Indicates maximum activity level for this performance level. 50% for now*/
552 graphic_level->ActivityLevel = sclk_activity_level_threshold;
553
554 graphic_level->CcPwrDynRm = 0;
555 graphic_level->CcPwrDynRm1 = 0;
556 /* this level can be used if activity is high enough.*/
557 graphic_level->EnabledForActivity = 0;
558 /* this level can be used for throttling.*/
559 graphic_level->EnabledForThrottle = 1;
560 graphic_level->UpHyst = 0;
561 graphic_level->DownHyst = 0;
562 graphic_level->VoltageDownHyst = 0;
563 graphic_level->PowerThrottle = 0;
564
565 data->display_timing.min_clock_in_sr =
566 hwmgr->display_config.min_core_set_clock_in_sr;
567
568 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
569 PHM_PlatformCaps_SclkDeepSleep))
570 graphic_level->DeepSleepDivId =
571 smu7_get_sleep_divider_id_from_clock(engine_clock,
572 data->display_timing.min_clock_in_sr);
573
574 /* Default to slow, highest DPM level will be set to PPSMC_DISPLAY_WATERMARK_LOW later.*/
575 graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
576
577 if (0 == result) {
578 /* CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVoltage);*/
579 /* CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVddcPhases);*/
580 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SclkFrequency);
581 CONVERT_FROM_HOST_TO_SMC_US(graphic_level->ActivityLevel);
582 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl3);
583 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl4);
584 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum);
585 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum2);
586 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm);
587 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm1);
588 }
589
590 return result;
591}
592
593/**
594 * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
595 *
596 * @param hwmgr the address of the hardware manager
597 */
598int tonga_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
599{
600 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
601 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend);
602 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
603 struct smu7_dpm_table *dpm_table = &data->dpm_table;
604 struct phm_ppt_v1_pcie_table *pcie_table = pptable_info->pcie_table;
605 uint8_t pcie_entry_count = (uint8_t) data->dpm_table.pcie_speed_table.count;
606 uint32_t level_array_address = smu_data->dpm_table_start +
607 offsetof(SMU72_Discrete_DpmTable, GraphicsLevel);
608
609 uint32_t level_array_size = sizeof(SMU72_Discrete_GraphicsLevel) *
610 SMU72_MAX_LEVELS_GRAPHICS;
611
612 SMU72_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel;
613
614 uint32_t i, max_entry;
615 uint8_t highest_pcie_level_enabled = 0;
616 uint8_t lowest_pcie_level_enabled = 0, mid_pcie_level_enabled = 0;
617 uint8_t count = 0;
618 int result = 0;
619
620 memset(levels, 0x00, level_array_size);
621
622 for (i = 0; i < dpm_table->sclk_table.count; i++) {
623 result = tonga_populate_single_graphic_level(hwmgr,
624 dpm_table->sclk_table.dpm_levels[i].value,
625 (uint16_t)smu_data->activity_target[i],
626 &(smu_data->smc_state_table.GraphicsLevel[i]));
627 if (result != 0)
628 return result;
629
630 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
631 if (i > 1)
632 smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
633 }
634
635 /* Only enable level 0 for now. */
636 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
637
638 /* set highest level watermark to high */
639 if (dpm_table->sclk_table.count > 1)
640 smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark =
641 PPSMC_DISPLAY_WATERMARK_HIGH;
642
643 smu_data->smc_state_table.GraphicsDpmLevelCount =
644 (uint8_t)dpm_table->sclk_table.count;
645 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
646 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
647
648 if (pcie_table != NULL) {
649 PP_ASSERT_WITH_CODE((pcie_entry_count >= 1),
650 "There must be 1 or more PCIE levels defined in PPTable.",
651 return -EINVAL);
652 max_entry = pcie_entry_count - 1; /* for indexing, we need to decrement by 1.*/
653 for (i = 0; i < dpm_table->sclk_table.count; i++) {
654 smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel =
655 (uint8_t) ((i < max_entry) ? i : max_entry);
656 }
657 } else {
658 if (0 == data->dpm_level_enable_mask.pcie_dpm_enable_mask)
659 printk(KERN_ERR "[ powerplay ] Pcie Dpm Enablemask is 0 !");
660
661 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
662 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
663 (1<<(highest_pcie_level_enabled+1))) != 0)) {
664 highest_pcie_level_enabled++;
665 }
666
667 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
668 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
669 (1<<lowest_pcie_level_enabled)) == 0)) {
670 lowest_pcie_level_enabled++;
671 }
672
673 while ((count < highest_pcie_level_enabled) &&
674 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
675 (1<<(lowest_pcie_level_enabled+1+count))) == 0)) {
676 count++;
677 }
678 mid_pcie_level_enabled = (lowest_pcie_level_enabled+1+count) < highest_pcie_level_enabled ?
679 (lowest_pcie_level_enabled+1+count) : highest_pcie_level_enabled;
680
681
682 /* set pcieDpmLevel to highest_pcie_level_enabled*/
683 for (i = 2; i < dpm_table->sclk_table.count; i++)
684 smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled;
685
686 /* set pcieDpmLevel to lowest_pcie_level_enabled*/
687 smu_data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled;
688
689 /* set pcieDpmLevel to mid_pcie_level_enabled*/
690 smu_data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled;
691 }
692 /* level count will send to smc once at init smc table and never change*/
693 result = tonga_copy_bytes_to_smc(hwmgr->smumgr, level_array_address,
694 (uint8_t *)levels, (uint32_t)level_array_size,
695 SMC_RAM_END);
696
697 return result;
698}
699
700/**
701 * Populates the SMC MCLK structure using the provided memory clock
702 *
703 * @param hwmgr the address of the hardware manager
704 * @param memory_clock the memory clock to use to populate the structure
705 * @param sclk the SMC SCLK structure to be populated
706 */
707static int tonga_calculate_mclk_params(
708 struct pp_hwmgr *hwmgr,
709 uint32_t memory_clock,
710 SMU72_Discrete_MemoryLevel *mclk,
711 bool strobe_mode,
712 bool dllStateOn
713 )
714{
715 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
716
717 uint32_t dll_cntl = data->clock_registers.vDLL_CNTL;
718 uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;
719 uint32_t mpll_ad_func_cntl = data->clock_registers.vMPLL_AD_FUNC_CNTL;
720 uint32_t mpll_dq_func_cntl = data->clock_registers.vMPLL_DQ_FUNC_CNTL;
721 uint32_t mpll_func_cntl = data->clock_registers.vMPLL_FUNC_CNTL;
722 uint32_t mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1;
723 uint32_t mpll_func_cntl_2 = data->clock_registers.vMPLL_FUNC_CNTL_2;
724 uint32_t mpll_ss1 = data->clock_registers.vMPLL_SS1;
725 uint32_t mpll_ss2 = data->clock_registers.vMPLL_SS2;
726
727 pp_atomctrl_memory_clock_param mpll_param;
728 int result;
729
730 result = atomctrl_get_memory_pll_dividers_si(hwmgr,
731 memory_clock, &mpll_param, strobe_mode);
732 PP_ASSERT_WITH_CODE(
733 0 == result,
734 "Error retrieving Memory Clock Parameters from VBIOS.",
735 return result);
736
737 /* MPLL_FUNC_CNTL setup*/
738 mpll_func_cntl = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL,
739 mpll_param.bw_ctrl);
740
741 /* MPLL_FUNC_CNTL_1 setup*/
742 mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
743 MPLL_FUNC_CNTL_1, CLKF,
744 mpll_param.mpll_fb_divider.cl_kf);
745 mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
746 MPLL_FUNC_CNTL_1, CLKFRAC,
747 mpll_param.mpll_fb_divider.clk_frac);
748 mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
749 MPLL_FUNC_CNTL_1, VCO_MODE,
750 mpll_param.vco_mode);
751
752 /* MPLL_AD_FUNC_CNTL setup*/
753 mpll_ad_func_cntl = PHM_SET_FIELD(mpll_ad_func_cntl,
754 MPLL_AD_FUNC_CNTL, YCLK_POST_DIV,
755 mpll_param.mpll_post_divider);
756
757 if (data->is_memory_gddr5) {
758 /* MPLL_DQ_FUNC_CNTL setup*/
759 mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl,
760 MPLL_DQ_FUNC_CNTL, YCLK_SEL,
761 mpll_param.yclk_sel);
762 mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl,
763 MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV,
764 mpll_param.mpll_post_divider);
765 }
766
767 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
768 PHM_PlatformCaps_MemorySpreadSpectrumSupport)) {
769 /*
770 ************************************
771 Fref = Reference Frequency
772 NF = Feedback divider ratio
773 NR = Reference divider ratio
774 Fnom = Nominal VCO output frequency = Fref * NF / NR
775 Fs = Spreading Rate
776 D = Percentage down-spread / 2
777 Fint = Reference input frequency to PFD = Fref / NR
778 NS = Spreading rate divider ratio = int(Fint / (2 * Fs))
779 CLKS = NS - 1 = ISS_STEP_NUM[11:0]
780 NV = D * Fs / Fnom * 4 * ((Fnom/Fref * NR) ^ 2)
781 CLKV = 65536 * NV = ISS_STEP_SIZE[25:0]
782 *************************************
783 */
784 pp_atomctrl_internal_ss_info ss_info;
785 uint32_t freq_nom;
786 uint32_t tmp;
787 uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr);
788
789 /* for GDDR5 for all modes and DDR3 */
790 if (1 == mpll_param.qdr)
791 freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider);
792 else
793 freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider);
794
795 /* tmp = (freq_nom / reference_clock * reference_divider) ^ 2 Note: S.I. reference_divider = 1*/
796 tmp = (freq_nom / reference_clock);
797 tmp = tmp * tmp;
798
799 if (0 == atomctrl_get_memory_clock_spread_spectrum(hwmgr, freq_nom, &ss_info)) {
800 /* ss_info.speed_spectrum_percentage -- in unit of 0.01% */
801 /* ss.Info.speed_spectrum_rate -- in unit of khz */
802 /* CLKS = reference_clock / (2 * speed_spectrum_rate * reference_divider) * 10 */
803 /* = reference_clock * 5 / speed_spectrum_rate */
804 uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate;
805
806 /* CLKV = 65536 * speed_spectrum_percentage / 2 * spreadSpecrumRate / freq_nom * 4 / 100000 * ((freq_nom / reference_clock) ^ 2) */
807 /* = 131 * speed_spectrum_percentage * speed_spectrum_rate / 100 * ((freq_nom / reference_clock) ^ 2) / freq_nom */
808 uint32_t clkv =
809 (uint32_t)((((131 * ss_info.speed_spectrum_percentage *
810 ss_info.speed_spectrum_rate) / 100) * tmp) / freq_nom);
811
812 mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv);
813 mpll_ss2 = PHM_SET_FIELD(mpll_ss2, MPLL_SS2, CLKS, clks);
814 }
815 }
816
817 /* MCLK_PWRMGT_CNTL setup */
818 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
819 MCLK_PWRMGT_CNTL, DLL_SPEED, mpll_param.dll_speed);
820 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
821 MCLK_PWRMGT_CNTL, MRDCK0_PDNB, dllStateOn);
822 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
823 MCLK_PWRMGT_CNTL, MRDCK1_PDNB, dllStateOn);
824
825 /* Save the result data to outpupt memory level structure */
826 mclk->MclkFrequency = memory_clock;
827 mclk->MpllFuncCntl = mpll_func_cntl;
828 mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
829 mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
830 mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
831 mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
832 mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
833 mclk->DllCntl = dll_cntl;
834 mclk->MpllSs1 = mpll_ss1;
835 mclk->MpllSs2 = mpll_ss2;
836
837 return 0;
838}
839
840static uint8_t tonga_get_mclk_frequency_ratio(uint32_t memory_clock,
841 bool strobe_mode)
842{
843 uint8_t mc_para_index;
844
845 if (strobe_mode) {
846 if (memory_clock < 12500)
847 mc_para_index = 0x00;
848 else if (memory_clock > 47500)
849 mc_para_index = 0x0f;
850 else
851 mc_para_index = (uint8_t)((memory_clock - 10000) / 2500);
852 } else {
853 if (memory_clock < 65000)
854 mc_para_index = 0x00;
855 else if (memory_clock > 135000)
856 mc_para_index = 0x0f;
857 else
858 mc_para_index = (uint8_t)((memory_clock - 60000) / 5000);
859 }
860
861 return mc_para_index;
862}
863
864static uint8_t tonga_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock)
865{
866 uint8_t mc_para_index;
867
868 if (memory_clock < 10000)
869 mc_para_index = 0;
870 else if (memory_clock >= 80000)
871 mc_para_index = 0x0f;
872 else
873 mc_para_index = (uint8_t)((memory_clock - 10000) / 5000 + 1);
874
875 return mc_para_index;
876}
877
878
879static int tonga_populate_single_memory_level(
880 struct pp_hwmgr *hwmgr,
881 uint32_t memory_clock,
882 SMU72_Discrete_MemoryLevel *memory_level
883 )
884{
885 uint32_t mvdd = 0;
886 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
887 struct phm_ppt_v1_information *pptable_info =
888 (struct phm_ppt_v1_information *)(hwmgr->pptable);
889 int result = 0;
890 bool dll_state_on;
891 struct cgs_display_info info = {0};
892 uint32_t mclk_edc_wr_enable_threshold = 40000;
893 uint32_t mclk_stutter_mode_threshold = 30000;
894 uint32_t mclk_edc_enable_threshold = 40000;
895 uint32_t mclk_strobe_mode_threshold = 40000;
896
897 if (NULL != pptable_info->vdd_dep_on_mclk) {
898 result = tonga_get_dependecy_volt_by_clk(hwmgr,
899 pptable_info->vdd_dep_on_mclk,
900 memory_clock,
901 &memory_level->MinVoltage, &mvdd);
902 PP_ASSERT_WITH_CODE(
903 0 == result,
904 "can not find MinVddc voltage value from memory VDDC "
905 "voltage dependency table",
906 return result);
907 }
908
909 if (data->mvdd_control == SMU7_VOLTAGE_CONTROL_NONE)
910 memory_level->MinMvdd = data->vbios_boot_state.mvdd_bootup_value;
911 else
912 memory_level->MinMvdd = mvdd;
913
914 memory_level->EnabledForThrottle = 1;
915 memory_level->EnabledForActivity = 0;
916 memory_level->UpHyst = 0;
917 memory_level->DownHyst = 100;
918 memory_level->VoltageDownHyst = 0;
919
920 /* Indicates maximum activity level for this performance level.*/
921 memory_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
922 memory_level->StutterEnable = 0;
923 memory_level->StrobeEnable = 0;
924 memory_level->EdcReadEnable = 0;
925 memory_level->EdcWriteEnable = 0;
926 memory_level->RttEnable = 0;
927
928 /* default set to low watermark. Highest level will be set to high later.*/
929 memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
930
931 cgs_get_active_displays_info(hwmgr->device, &info);
932 data->display_timing.num_existing_displays = info.display_count;
933
934 if ((mclk_stutter_mode_threshold != 0) &&
935 (memory_clock <= mclk_stutter_mode_threshold) &&
936 (!data->is_uvd_enabled)
937 && (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE) & 0x1)
938 && (data->display_timing.num_existing_displays <= 2)
939 && (data->display_timing.num_existing_displays != 0))
940 memory_level->StutterEnable = 1;
941
942 /* decide strobe mode*/
943 memory_level->StrobeEnable = (mclk_strobe_mode_threshold != 0) &&
944 (memory_clock <= mclk_strobe_mode_threshold);
945
946 /* decide EDC mode and memory clock ratio*/
947 if (data->is_memory_gddr5) {
948 memory_level->StrobeRatio = tonga_get_mclk_frequency_ratio(memory_clock,
949 memory_level->StrobeEnable);
950
951 if ((mclk_edc_enable_threshold != 0) &&
952 (memory_clock > mclk_edc_enable_threshold)) {
953 memory_level->EdcReadEnable = 1;
954 }
955
956 if ((mclk_edc_wr_enable_threshold != 0) &&
957 (memory_clock > mclk_edc_wr_enable_threshold)) {
958 memory_level->EdcWriteEnable = 1;
959 }
960
961 if (memory_level->StrobeEnable) {
962 if (tonga_get_mclk_frequency_ratio(memory_clock, 1) >=
963 ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf)) {
964 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
965 } else {
966 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0;
967 }
968
969 } else {
970 dll_state_on = data->dll_default_on;
971 }
972 } else {
973 memory_level->StrobeRatio =
974 tonga_get_ddr3_mclk_frequency_ratio(memory_clock);
975 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
976 }
977
978 result = tonga_calculate_mclk_params(hwmgr,
979 memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
980
981 if (!result) {
982 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MinMvdd);
983 /* MCLK frequency in units of 10KHz*/
984 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkFrequency);
985 /* Indicates maximum activity level for this performance level.*/
986 CONVERT_FROM_HOST_TO_SMC_US(memory_level->ActivityLevel);
987 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl);
988 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_1);
989 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_2);
990 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllAdFuncCntl);
991 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllDqFuncCntl);
992 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkPwrmgtCntl);
993 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->DllCntl);
994 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs1);
995 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs2);
996 }
997
998 return result;
999}
1000
1001int tonga_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1002{
1003 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1004 struct tonga_smumgr *smu_data =
1005 (struct tonga_smumgr *)(hwmgr->smumgr->backend);
1006 struct smu7_dpm_table *dpm_table = &data->dpm_table;
1007 int result;
1008
1009 /* populate MCLK dpm table to SMU7 */
1010 uint32_t level_array_address =
1011 smu_data->dpm_table_start +
1012 offsetof(SMU72_Discrete_DpmTable, MemoryLevel);
1013 uint32_t level_array_size =
1014 sizeof(SMU72_Discrete_MemoryLevel) *
1015 SMU72_MAX_LEVELS_MEMORY;
1016 SMU72_Discrete_MemoryLevel *levels =
1017 smu_data->smc_state_table.MemoryLevel;
1018 uint32_t i;
1019
1020 memset(levels, 0x00, level_array_size);
1021
1022 for (i = 0; i < dpm_table->mclk_table.count; i++) {
1023 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1024 "can not populate memory level as memory clock is zero",
1025 return -EINVAL);
1026 result = tonga_populate_single_memory_level(
1027 hwmgr,
1028 dpm_table->mclk_table.dpm_levels[i].value,
1029 &(smu_data->smc_state_table.MemoryLevel[i]));
1030 if (result)
1031 return result;
1032 }
1033
1034 /* Only enable level 0 for now.*/
1035 smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
1036
1037 /*
1038 * in order to prevent MC activity from stutter mode to push DPM up.
1039 * the UVD change complements this by putting the MCLK in a higher state
1040 * by default such that we are not effected by up threshold or and MCLK DPM latency.
1041 */
1042 smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F;
1043 CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel);
1044
1045 smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count;
1046 data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
1047 /* set highest level watermark to high*/
1048 smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
1049
1050 /* level count will send to smc once at init smc table and never change*/
1051 result = tonga_copy_bytes_to_smc(hwmgr->smumgr,
1052 level_array_address, (uint8_t *)levels, (uint32_t)level_array_size,
1053 SMC_RAM_END);
1054
1055
1056 return result;
1057}
1058
1059static int tonga_populate_mvdd_value(struct pp_hwmgr *hwmgr,
1060 uint32_t mclk, SMIO_Pattern *smio_pattern)
1061{
1062 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1063 struct phm_ppt_v1_information *table_info =
1064 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1065 uint32_t i = 0;
1066
1067 if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
1068 /* find mvdd value which clock is more than request */
1069 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
1070 if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
1071 /* Always round to higher voltage. */
1072 smio_pattern->Voltage =
1073 data->mvdd_voltage_table.entries[i].value;
1074 break;
1075 }
1076 }
1077
1078 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
1079 "MVDD Voltage is outside the supported range.",
1080 return -EINVAL);
1081 } else {
1082 return -EINVAL;
1083 }
1084
1085 return 0;
1086}
1087
1088
1089static int tonga_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
1090 SMU72_Discrete_DpmTable *table)
1091{
1092 int result = 0;
1093 struct tonga_smumgr *smu_data =
1094 (struct tonga_smumgr *)(hwmgr->smumgr->backend);
1095 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1096 struct pp_atomctrl_clock_dividers_vi dividers;
1097
1098 SMIO_Pattern voltage_level;
1099 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
1100 uint32_t spll_func_cntl_2 = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;
1101 uint32_t dll_cntl = data->clock_registers.vDLL_CNTL;
1102 uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;
1103
1104 /* The ACPI state should not do DPM on DC (or ever).*/
1105 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1106
1107 table->ACPILevel.MinVoltage =
1108 smu_data->smc_state_table.GraphicsLevel[0].MinVoltage;
1109
1110 /* assign zero for now*/
1111 table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr);
1112
1113 /* get the engine clock dividers for this clock value*/
1114 result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
1115 table->ACPILevel.SclkFrequency, &dividers);
1116
1117 PP_ASSERT_WITH_CODE(result == 0,
1118 "Error retrieving Engine Clock dividers from VBIOS.",
1119 return result);
1120
1121 /* divider ID for required SCLK*/
1122 table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
1123 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1124 table->ACPILevel.DeepSleepDivId = 0;
1125
1126 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
1127 SPLL_PWRON, 0);
1128 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
1129 SPLL_RESET, 1);
1130 spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2, CG_SPLL_FUNC_CNTL_2,
1131 SCLK_MUX_SEL, 4);
1132
1133 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
1134 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
1135 table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
1136 table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
1137 table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
1138 table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
1139 table->ACPILevel.CcPwrDynRm = 0;
1140 table->ACPILevel.CcPwrDynRm1 = 0;
1141
1142
1143 /* For various features to be enabled/disabled while this level is active.*/
1144 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1145 /* SCLK frequency in units of 10KHz*/
1146 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
1147 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
1148 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
1149 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
1150 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
1151 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
1152 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
1153 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1154 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1155
1156 /* table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;*/
1157 table->MemoryACPILevel.MinVoltage =
1158 smu_data->smc_state_table.MemoryLevel[0].MinVoltage;
1159
1160 /* CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);*/
1161
1162 if (0 == tonga_populate_mvdd_value(hwmgr, 0, &voltage_level))
1163 table->MemoryACPILevel.MinMvdd =
1164 PP_HOST_TO_SMC_UL(voltage_level.Voltage * VOLTAGE_SCALE);
1165 else
1166 table->MemoryACPILevel.MinMvdd = 0;
1167
1168 /* Force reset on DLL*/
1169 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1170 MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1);
1171 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1172 MCLK_PWRMGT_CNTL, MRDCK1_RESET, 0x1);
1173
1174 /* Disable DLL in ACPIState*/
1175 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1176 MCLK_PWRMGT_CNTL, MRDCK0_PDNB, 0);
1177 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1178 MCLK_PWRMGT_CNTL, MRDCK1_PDNB, 0);
1179
1180 /* Enable DLL bypass signal*/
1181 dll_cntl = PHM_SET_FIELD(dll_cntl,
1182 DLL_CNTL, MRDCK0_BYPASS, 0);
1183 dll_cntl = PHM_SET_FIELD(dll_cntl,
1184 DLL_CNTL, MRDCK1_BYPASS, 0);
1185
1186 table->MemoryACPILevel.DllCntl =
1187 PP_HOST_TO_SMC_UL(dll_cntl);
1188 table->MemoryACPILevel.MclkPwrmgtCntl =
1189 PP_HOST_TO_SMC_UL(mclk_pwrmgt_cntl);
1190 table->MemoryACPILevel.MpllAdFuncCntl =
1191 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_AD_FUNC_CNTL);
1192 table->MemoryACPILevel.MpllDqFuncCntl =
1193 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_DQ_FUNC_CNTL);
1194 table->MemoryACPILevel.MpllFuncCntl =
1195 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL);
1196 table->MemoryACPILevel.MpllFuncCntl_1 =
1197 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_1);
1198 table->MemoryACPILevel.MpllFuncCntl_2 =
1199 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_2);
1200 table->MemoryACPILevel.MpllSs1 =
1201 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS1);
1202 table->MemoryACPILevel.MpllSs2 =
1203 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2);
1204
1205 table->MemoryACPILevel.EnabledForThrottle = 0;
1206 table->MemoryACPILevel.EnabledForActivity = 0;
1207 table->MemoryACPILevel.UpHyst = 0;
1208 table->MemoryACPILevel.DownHyst = 100;
1209 table->MemoryACPILevel.VoltageDownHyst = 0;
1210 /* Indicates maximum activity level for this performance level.*/
1211 table->MemoryACPILevel.ActivityLevel =
1212 PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
1213
1214 table->MemoryACPILevel.StutterEnable = 0;
1215 table->MemoryACPILevel.StrobeEnable = 0;
1216 table->MemoryACPILevel.EdcReadEnable = 0;
1217 table->MemoryACPILevel.EdcWriteEnable = 0;
1218 table->MemoryACPILevel.RttEnable = 0;
1219
1220 return result;
1221}
1222
1223static int tonga_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1224 SMU72_Discrete_DpmTable *table)
1225{
1226 int result = 0;
1227
1228 uint8_t count;
1229 pp_atomctrl_clock_dividers_vi dividers;
1230 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1231 struct phm_ppt_v1_information *pptable_info =
1232 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1233 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1234 pptable_info->mm_dep_table;
1235
1236 table->UvdLevelCount = (uint8_t) (mm_table->count);
1237 table->UvdBootLevel = 0;
1238
1239 for (count = 0; count < table->UvdLevelCount; count++) {
1240 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1241 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1242 table->UvdLevel[count].MinVoltage.Vddc =
1243 phm_get_voltage_index(pptable_info->vddc_lookup_table,
1244 mm_table->entries[count].vddc);
1245 table->UvdLevel[count].MinVoltage.VddGfx =
1246 (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) ?
1247 phm_get_voltage_index(pptable_info->vddgfx_lookup_table,
1248 mm_table->entries[count].vddgfx) : 0;
1249 table->UvdLevel[count].MinVoltage.Vddci =
1250 phm_get_voltage_id(&data->vddci_voltage_table,
1251 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1252 table->UvdLevel[count].MinVoltage.Phases = 1;
1253
1254 /* retrieve divider value for VBIOS */
1255 result = atomctrl_get_dfs_pll_dividers_vi(
1256 hwmgr,
1257 table->UvdLevel[count].VclkFrequency,
1258 &dividers);
1259
1260 PP_ASSERT_WITH_CODE((0 == result),
1261 "can not find divide id for Vclk clock",
1262 return result);
1263
1264 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1265
1266 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1267 table->UvdLevel[count].DclkFrequency, &dividers);
1268 PP_ASSERT_WITH_CODE((0 == result),
1269 "can not find divide id for Dclk clock",
1270 return result);
1271
1272 table->UvdLevel[count].DclkDivider =
1273 (uint8_t)dividers.pll_post_divider;
1274
1275 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1276 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1277 }
1278
1279 return result;
1280
1281}
1282
1283static int tonga_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1284 SMU72_Discrete_DpmTable *table)
1285{
1286 int result = 0;
1287
1288 uint8_t count;
1289 pp_atomctrl_clock_dividers_vi dividers;
1290 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1291 struct phm_ppt_v1_information *pptable_info =
1292 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1293 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1294 pptable_info->mm_dep_table;
1295
1296 table->VceLevelCount = (uint8_t) (mm_table->count);
1297 table->VceBootLevel = 0;
1298
1299 for (count = 0; count < table->VceLevelCount; count++) {
1300 table->VceLevel[count].Frequency =
1301 mm_table->entries[count].eclk;
1302 table->VceLevel[count].MinVoltage.Vddc =
1303 phm_get_voltage_index(pptable_info->vddc_lookup_table,
1304 mm_table->entries[count].vddc);
1305 table->VceLevel[count].MinVoltage.VddGfx =
1306 (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) ?
1307 phm_get_voltage_index(pptable_info->vddgfx_lookup_table,
1308 mm_table->entries[count].vddgfx) : 0;
1309 table->VceLevel[count].MinVoltage.Vddci =
1310 phm_get_voltage_id(&data->vddci_voltage_table,
1311 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1312 table->VceLevel[count].MinVoltage.Phases = 1;
1313
1314 /* retrieve divider value for VBIOS */
1315 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1316 table->VceLevel[count].Frequency, &dividers);
1317 PP_ASSERT_WITH_CODE((0 == result),
1318 "can not find divide id for VCE engine clock",
1319 return result);
1320
1321 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1322
1323 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1324 }
1325
1326 return result;
1327}
1328
1329static int tonga_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
1330 SMU72_Discrete_DpmTable *table)
1331{
1332 int result = 0;
1333 uint8_t count;
1334 pp_atomctrl_clock_dividers_vi dividers;
1335 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1336 struct phm_ppt_v1_information *pptable_info =
1337 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1338 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1339 pptable_info->mm_dep_table;
1340
1341 table->AcpLevelCount = (uint8_t) (mm_table->count);
1342 table->AcpBootLevel = 0;
1343
1344 for (count = 0; count < table->AcpLevelCount; count++) {
1345 table->AcpLevel[count].Frequency =
1346 pptable_info->mm_dep_table->entries[count].aclk;
1347 table->AcpLevel[count].MinVoltage.Vddc =
1348 phm_get_voltage_index(pptable_info->vddc_lookup_table,
1349 mm_table->entries[count].vddc);
1350 table->AcpLevel[count].MinVoltage.VddGfx =
1351 (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) ?
1352 phm_get_voltage_index(pptable_info->vddgfx_lookup_table,
1353 mm_table->entries[count].vddgfx) : 0;
1354 table->AcpLevel[count].MinVoltage.Vddci =
1355 phm_get_voltage_id(&data->vddci_voltage_table,
1356 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1357 table->AcpLevel[count].MinVoltage.Phases = 1;
1358
1359 /* retrieve divider value for VBIOS */
1360 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1361 table->AcpLevel[count].Frequency, &dividers);
1362 PP_ASSERT_WITH_CODE((0 == result),
1363 "can not find divide id for engine clock", return result);
1364
1365 table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1366
1367 CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency);
1368 }
1369
1370 return result;
1371}
1372
1373static int tonga_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
1374 SMU72_Discrete_DpmTable *table)
1375{
1376 int result = 0;
1377 uint8_t count;
1378 pp_atomctrl_clock_dividers_vi dividers;
1379 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1380 struct phm_ppt_v1_information *pptable_info =
1381 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1382 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1383 pptable_info->mm_dep_table;
1384
1385 table->SamuBootLevel = 0;
1386 table->SamuLevelCount = (uint8_t) (mm_table->count);
1387
1388 for (count = 0; count < table->SamuLevelCount; count++) {
1389 /* not sure whether we need evclk or not */
1390 table->SamuLevel[count].Frequency =
1391 pptable_info->mm_dep_table->entries[count].samclock;
1392 table->SamuLevel[count].MinVoltage.Vddc =
1393 phm_get_voltage_index(pptable_info->vddc_lookup_table,
1394 mm_table->entries[count].vddc);
1395 table->SamuLevel[count].MinVoltage.VddGfx =
1396 (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) ?
1397 phm_get_voltage_index(pptable_info->vddgfx_lookup_table,
1398 mm_table->entries[count].vddgfx) : 0;
1399 table->SamuLevel[count].MinVoltage.Vddci =
1400 phm_get_voltage_id(&data->vddci_voltage_table,
1401 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1402 table->SamuLevel[count].MinVoltage.Phases = 1;
1403
1404 /* retrieve divider value for VBIOS */
1405 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1406 table->SamuLevel[count].Frequency, &dividers);
1407 PP_ASSERT_WITH_CODE((0 == result),
1408 "can not find divide id for samu clock", return result);
1409
1410 table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1411
1412 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
1413 }
1414
1415 return result;
1416}
1417
1418static int tonga_populate_memory_timing_parameters(
1419 struct pp_hwmgr *hwmgr,
1420 uint32_t engine_clock,
1421 uint32_t memory_clock,
1422 struct SMU72_Discrete_MCArbDramTimingTableEntry *arb_regs
1423 )
1424{
1425 uint32_t dramTiming;
1426 uint32_t dramTiming2;
1427 uint32_t burstTime;
1428 int result;
1429
1430 result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1431 engine_clock, memory_clock);
1432
1433 PP_ASSERT_WITH_CODE(result == 0,
1434 "Error calling VBIOS to set DRAM_TIMING.", return result);
1435
1436 dramTiming = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1437 dramTiming2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1438 burstTime = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1439
1440 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dramTiming);
1441 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2);
1442 arb_regs->McArbBurstTime = (uint8_t)burstTime;
1443
1444 return 0;
1445}
1446
1447/**
1448 * Setup parameters for the MC ARB.
1449 *
1450 * @param hwmgr the address of the powerplay hardware manager.
1451 * @return always 0
1452 * This function is to be called from the SetPowerState table.
1453 */
1454static int tonga_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1455{
1456 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1457 struct tonga_smumgr *smu_data =
1458 (struct tonga_smumgr *)(hwmgr->smumgr->backend);
1459 int result = 0;
1460 SMU72_Discrete_MCArbDramTimingTable arb_regs;
1461 uint32_t i, j;
1462
1463 memset(&arb_regs, 0x00, sizeof(SMU72_Discrete_MCArbDramTimingTable));
1464
1465 for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1466 for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
1467 result = tonga_populate_memory_timing_parameters
1468 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value,
1469 data->dpm_table.mclk_table.dpm_levels[j].value,
1470 &arb_regs.entries[i][j]);
1471
1472 if (result)
1473 break;
1474 }
1475 }
1476
1477 if (0 == result) {
1478 result = tonga_copy_bytes_to_smc(
1479 hwmgr->smumgr,
1480 smu_data->arb_table_start,
1481 (uint8_t *)&arb_regs,
1482 sizeof(SMU72_Discrete_MCArbDramTimingTable),
1483 SMC_RAM_END
1484 );
1485 }
1486
1487 return result;
1488}
1489
1490static int tonga_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1491 SMU72_Discrete_DpmTable *table)
1492{
1493 int result = 0;
1494 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1495 struct tonga_smumgr *smu_data =
1496 (struct tonga_smumgr *)(hwmgr->smumgr->backend);
1497 table->GraphicsBootLevel = 0;
1498 table->MemoryBootLevel = 0;
1499
1500 /* find boot level from dpm table*/
1501 result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1502 data->vbios_boot_state.sclk_bootup_value,
1503 (uint32_t *)&(smu_data->smc_state_table.GraphicsBootLevel));
1504
1505 if (0 != result) {
1506 smu_data->smc_state_table.GraphicsBootLevel = 0;
1507 printk(KERN_ERR "[powerplay] VBIOS did not find boot engine "
1508 "clock value in dependency table. "
1509 "Using Graphics DPM level 0 !");
1510 result = 0;
1511 }
1512
1513 result = phm_find_boot_level(&(data->dpm_table.mclk_table),
1514 data->vbios_boot_state.mclk_bootup_value,
1515 (uint32_t *)&(smu_data->smc_state_table.MemoryBootLevel));
1516
1517 if (0 != result) {
1518 smu_data->smc_state_table.MemoryBootLevel = 0;
1519 printk(KERN_ERR "[powerplay] VBIOS did not find boot "
1520 "engine clock value in dependency table."
1521 "Using Memory DPM level 0 !");
1522 result = 0;
1523 }
1524
1525 table->BootVoltage.Vddc =
1526 phm_get_voltage_id(&(data->vddc_voltage_table),
1527 data->vbios_boot_state.vddc_bootup_value);
1528 table->BootVoltage.VddGfx =
1529 phm_get_voltage_id(&(data->vddgfx_voltage_table),
1530 data->vbios_boot_state.vddgfx_bootup_value);
1531 table->BootVoltage.Vddci =
1532 phm_get_voltage_id(&(data->vddci_voltage_table),
1533 data->vbios_boot_state.vddci_bootup_value);
1534 table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value;
1535
1536 CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
1537
1538 return result;
1539}
1540
1541
1542static int tonga_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1543{
1544 uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks,
1545 volt_with_cks, value;
1546 uint16_t clock_freq_u16;
1547 struct tonga_smumgr *smu_data =
1548 (struct tonga_smumgr *)(hwmgr->smumgr->backend);
1549 uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2,
1550 volt_offset = 0;
1551 struct phm_ppt_v1_information *table_info =
1552 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1553 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1554 table_info->vdd_dep_on_sclk;
1555 uint32_t hw_revision, dev_id;
1556 struct cgs_system_info sys_info = {0};
1557
1558 stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
1559
1560 sys_info.size = sizeof(struct cgs_system_info);
1561
1562 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_REV;
1563 cgs_query_system_info(hwmgr->device, &sys_info);
1564 hw_revision = (uint32_t)sys_info.value;
1565
1566 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV;
1567 cgs_query_system_info(hwmgr->device, &sys_info);
1568 dev_id = (uint32_t)sys_info.value;
1569
1570 /* Read SMU_Eefuse to read and calculate RO and determine
1571 * if the part is SS or FF. if RO >= 1660MHz, part is FF.
1572 */
1573 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1574 ixSMU_EFUSE_0 + (146 * 4));
1575 efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1576 ixSMU_EFUSE_0 + (148 * 4));
1577 efuse &= 0xFF000000;
1578 efuse = efuse >> 24;
1579 efuse2 &= 0xF;
1580
1581 if (efuse2 == 1)
1582 ro = (2300 - 1350) * efuse / 255 + 1350;
1583 else
1584 ro = (2500 - 1000) * efuse / 255 + 1000;
1585
1586 if (ro >= 1660)
1587 type = 0;
1588 else
1589 type = 1;
1590
1591 /* Populate Stretch amount */
1592 smu_data->smc_state_table.ClockStretcherAmount = stretch_amount;
1593
1594 /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
1595 for (i = 0; i < sclk_table->count; i++) {
1596 smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |=
1597 sclk_table->entries[i].cks_enable << i;
1598 if (ASICID_IS_TONGA_P(dev_id, hw_revision)) {
1599 volt_without_cks = (uint32_t)((7732 + 60 - ro - 20838 *
1600 (sclk_table->entries[i].clk/100) / 10000) * 1000 /
1601 (8730 - (5301 * (sclk_table->entries[i].clk/100) / 1000)));
1602 volt_with_cks = (uint32_t)((5250 + 51 - ro - 2404 *
1603 (sclk_table->entries[i].clk/100) / 100000) * 1000 /
1604 (6146 - (3193 * (sclk_table->entries[i].clk/100) / 1000)));
1605 } else {
1606 volt_without_cks = (uint32_t)((14041 *
1607 (sclk_table->entries[i].clk/100) / 10000 + 3571 + 75 - ro) * 1000 /
1608 (4026 - (13924 * (sclk_table->entries[i].clk/100) / 10000)));
1609 volt_with_cks = (uint32_t)((13946 *
1610 (sclk_table->entries[i].clk/100) / 10000 + 3320 + 45 - ro) * 1000 /
1611 (3664 - (11454 * (sclk_table->entries[i].clk/100) / 10000)));
1612 }
1613 if (volt_without_cks >= volt_with_cks)
1614 volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
1615 sclk_table->entries[i].cks_voffset) * 100 / 625) + 1);
1616 smu_data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
1617 }
1618
1619 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1620 STRETCH_ENABLE, 0x0);
1621 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1622 masterReset, 0x1);
1623 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1624 staticEnable, 0x1);
1625 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1626 masterReset, 0x0);
1627
1628 /* Populate CKS Lookup Table */
1629 if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
1630 stretch_amount2 = 0;
1631 else if (stretch_amount == 3 || stretch_amount == 4)
1632 stretch_amount2 = 1;
1633 else {
1634 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1635 PHM_PlatformCaps_ClockStretcher);
1636 PP_ASSERT_WITH_CODE(false,
1637 "Stretch Amount in PPTable not supported\n",
1638 return -EINVAL);
1639 }
1640
1641 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1642 ixPWR_CKS_CNTL);
1643 value &= 0xFFC2FF87;
1644 smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq =
1645 tonga_clock_stretcher_lookup_table[stretch_amount2][0];
1646 smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq =
1647 tonga_clock_stretcher_lookup_table[stretch_amount2][1];
1648 clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(smu_data->smc_state_table.
1649 GraphicsLevel[smu_data->smc_state_table.GraphicsDpmLevelCount - 1].
1650 SclkFrequency) / 100);
1651 if (tonga_clock_stretcher_lookup_table[stretch_amount2][0] <
1652 clock_freq_u16 &&
1653 tonga_clock_stretcher_lookup_table[stretch_amount2][1] >
1654 clock_freq_u16) {
1655 /* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */
1656 value |= (tonga_clock_stretcher_lookup_table[stretch_amount2][3]) << 16;
1657 /* Program PWR_CKS_CNTL. CKS_LDO_REFSEL */
1658 value |= (tonga_clock_stretcher_lookup_table[stretch_amount2][2]) << 18;
1659 /* Program PWR_CKS_CNTL. CKS_STRETCH_AMOUNT */
1660 value |= (tonga_clock_stretch_amount_conversion
1661 [tonga_clock_stretcher_lookup_table[stretch_amount2][3]]
1662 [stretch_amount]) << 3;
1663 }
1664 CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.CKS_LOOKUPTable.
1665 CKS_LOOKUPTableEntry[0].minFreq);
1666 CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.CKS_LOOKUPTable.
1667 CKS_LOOKUPTableEntry[0].maxFreq);
1668 smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting =
1669 tonga_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F;
1670 smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |=
1671 (tonga_clock_stretcher_lookup_table[stretch_amount2][3]) << 7;
1672
1673 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1674 ixPWR_CKS_CNTL, value);
1675
1676 /* Populate DDT Lookup Table */
1677 for (i = 0; i < 4; i++) {
1678 /* Assign the minimum and maximum VID stored
1679 * in the last row of Clock Stretcher Voltage Table.
1680 */
1681 smu_data->smc_state_table.ClockStretcherDataTable.
1682 ClockStretcherDataTableEntry[i].minVID =
1683 (uint8_t) tonga_clock_stretcher_ddt_table[type][i][2];
1684 smu_data->smc_state_table.ClockStretcherDataTable.
1685 ClockStretcherDataTableEntry[i].maxVID =
1686 (uint8_t) tonga_clock_stretcher_ddt_table[type][i][3];
1687 /* Loop through each SCLK and check the frequency
1688 * to see if it lies within the frequency for clock stretcher.
1689 */
1690 for (j = 0; j < smu_data->smc_state_table.GraphicsDpmLevelCount; j++) {
1691 cks_setting = 0;
1692 clock_freq = PP_SMC_TO_HOST_UL(
1693 smu_data->smc_state_table.GraphicsLevel[j].SclkFrequency);
1694 /* Check the allowed frequency against the sclk level[j].
1695 * Sclk's endianness has already been converted,
1696 * and it's in 10Khz unit,
1697 * as opposed to Data table, which is in Mhz unit.
1698 */
1699 if (clock_freq >= tonga_clock_stretcher_ddt_table[type][i][0] * 100) {
1700 cks_setting |= 0x2;
1701 if (clock_freq < tonga_clock_stretcher_ddt_table[type][i][1] * 100)
1702 cks_setting |= 0x1;
1703 }
1704 smu_data->smc_state_table.ClockStretcherDataTable.
1705 ClockStretcherDataTableEntry[i].setting |= cks_setting << (j * 2);
1706 }
1707 CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.
1708 ClockStretcherDataTable.
1709 ClockStretcherDataTableEntry[i].setting);
1710 }
1711
1712 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1713 ixPWR_CKS_CNTL);
1714 value &= 0xFFFFFFFE;
1715 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1716 ixPWR_CKS_CNTL, value);
1717
1718 return 0;
1719}
1720
1721/**
1722 * Populates the SMC VRConfig field in DPM table.
1723 *
1724 * @param hwmgr the address of the hardware manager
1725 * @param table the SMC DPM table structure to be populated
1726 * @return always 0
1727 */
1728static int tonga_populate_vr_config(struct pp_hwmgr *hwmgr,
1729 SMU72_Discrete_DpmTable *table)
1730{
1731 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1732 uint16_t config;
1733
1734 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
1735 /* Splitted mode */
1736 config = VR_SVI2_PLANE_1;
1737 table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT);
1738
1739 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1740 config = VR_SVI2_PLANE_2;
1741 table->VRConfig |= config;
1742 } else {
1743 printk(KERN_ERR "[ powerplay ] VDDC and VDDGFX should "
1744 "be both on SVI2 control in splitted mode !\n");
1745 }
1746 } else {
1747 /* Merged mode */
1748 config = VR_MERGED_WITH_VDDC;
1749 table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT);
1750
1751 /* Set Vddc Voltage Controller */
1752 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1753 config = VR_SVI2_PLANE_1;
1754 table->VRConfig |= config;
1755 } else {
1756 printk(KERN_ERR "[ powerplay ] VDDC should be on "
1757 "SVI2 control in merged mode !\n");
1758 }
1759 }
1760
1761 /* Set Vddci Voltage Controller */
1762 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
1763 config = VR_SVI2_PLANE_2; /* only in merged mode */
1764 table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);
1765 } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
1766 config = VR_SMIO_PATTERN_1;
1767 table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);
1768 }
1769
1770 /* Set Mvdd Voltage Controller */
1771 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1772 config = VR_SMIO_PATTERN_2;
1773 table->VRConfig |= (config<<VRCONF_MVDD_SHIFT);
1774 }
1775
1776 return 0;
1777}
1778
1779
1780/**
1781 * Initialize the ARB DRAM timing table's index field.
1782 *
1783 * @param hwmgr the address of the powerplay hardware manager.
1784 * @return always 0
1785 */
1786static int tonga_init_arb_table_index(struct pp_smumgr *smumgr)
1787{
1788 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(smumgr->backend);
1789 uint32_t tmp;
1790 int result;
1791
1792 /*
1793 * This is a read-modify-write on the first byte of the ARB table.
1794 * The first byte in the SMU72_Discrete_MCArbDramTimingTable structure
1795 * is the field 'current'.
1796 * This solution is ugly, but we never write the whole table only
1797 * individual fields in it.
1798 * In reality this field should not be in that structure
1799 * but in a soft register.
1800 */
1801 result = tonga_read_smc_sram_dword(smumgr,
1802 smu_data->arb_table_start, &tmp, SMC_RAM_END);
1803
1804 if (0 != result)
1805 return result;
1806
1807 tmp &= 0x00FFFFFF;
1808 tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
1809
1810 return tonga_write_smc_sram_dword(smumgr,
1811 smu_data->arb_table_start, tmp, SMC_RAM_END);
1812}
1813
1814
1815static int tonga_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
1816{
1817 struct tonga_smumgr *smu_data =
1818 (struct tonga_smumgr *)(hwmgr->smumgr->backend);
1819 struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults;
1820 SMU72_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table);
1821 struct phm_ppt_v1_information *table_info =
1822 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1823 struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table;
1824 int i, j, k;
1825 uint16_t *pdef1;
1826 uint16_t *pdef2;
1827
1828 dpm_table->DefaultTdp = PP_HOST_TO_SMC_US(
1829 (uint16_t)(cac_dtp_table->usTDP * 256));
1830 dpm_table->TargetTdp = PP_HOST_TO_SMC_US(
1831 (uint16_t)(cac_dtp_table->usConfigurableTDP * 256));
1832
1833 PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,
1834 "Target Operating Temp is out of Range !",
1835 );
1836
1837 dpm_table->GpuTjMax = (uint8_t)(cac_dtp_table->usTargetOperatingTemp);
1838 dpm_table->GpuTjHyst = 8;
1839
1840 dpm_table->DTEAmbientTempBase = defaults->dte_ambient_temp_base;
1841
1842 dpm_table->BAPM_TEMP_GRADIENT =
1843 PP_HOST_TO_SMC_UL(defaults->bamp_temp_gradient);
1844 pdef1 = defaults->bapmti_r;
1845 pdef2 = defaults->bapmti_rc;
1846
1847 for (i = 0; i < SMU72_DTE_ITERATIONS; i++) {
1848 for (j = 0; j < SMU72_DTE_SOURCES; j++) {
1849 for (k = 0; k < SMU72_DTE_SINKS; k++) {
1850 dpm_table->BAPMTI_R[i][j][k] =
1851 PP_HOST_TO_SMC_US(*pdef1);
1852 dpm_table->BAPMTI_RC[i][j][k] =
1853 PP_HOST_TO_SMC_US(*pdef2);
1854 pdef1++;
1855 pdef2++;
1856 }
1857 }
1858 }
1859
1860 return 0;
1861}
1862
1863static int tonga_populate_svi_load_line(struct pp_hwmgr *hwmgr)
1864{
1865 struct tonga_smumgr *smu_data =
1866 (struct tonga_smumgr *)(hwmgr->smumgr->backend);
1867 struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults;
1868
1869 smu_data->power_tune_table.SviLoadLineEn = defaults->svi_load_line_en;
1870 smu_data->power_tune_table.SviLoadLineVddC = defaults->svi_load_line_vddC;
1871 smu_data->power_tune_table.SviLoadLineTrimVddC = 3;
1872 smu_data->power_tune_table.SviLoadLineOffsetVddC = 0;
1873
1874 return 0;
1875}
1876
1877static int tonga_populate_tdc_limit(struct pp_hwmgr *hwmgr)
1878{
1879 uint16_t tdc_limit;
1880 struct tonga_smumgr *smu_data =
1881 (struct tonga_smumgr *)(hwmgr->smumgr->backend);
1882 struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults;
1883 struct phm_ppt_v1_information *table_info =
1884 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1885
1886 /* TDC number of fraction bits are changed from 8 to 7
1887 * for Fiji as requested by SMC team
1888 */
1889 tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 256);
1890 smu_data->power_tune_table.TDC_VDDC_PkgLimit =
1891 CONVERT_FROM_HOST_TO_SMC_US(tdc_limit);
1892 smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
1893 defaults->tdc_vddc_throttle_release_limit_perc;
1894 smu_data->power_tune_table.TDC_MAWt = defaults->tdc_mawt;
1895
1896 return 0;
1897}
1898
1899static int tonga_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
1900{
1901 struct tonga_smumgr *smu_data =
1902 (struct tonga_smumgr *)(hwmgr->smumgr->backend);
1903 struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults;
1904 uint32_t temp;
1905
1906 if (tonga_read_smc_sram_dword(hwmgr->smumgr,
1907 fuse_table_offset +
1908 offsetof(SMU72_Discrete_PmFuses, TdcWaterfallCtl),
1909 (uint32_t *)&temp, SMC_RAM_END))
1910 PP_ASSERT_WITH_CODE(false,
1911 "Attempt to read PmFuses.DW6 "
1912 "(SviLoadLineEn) from SMC Failed !",
1913 return -EINVAL);
1914 else
1915 smu_data->power_tune_table.TdcWaterfallCtl = defaults->tdc_waterfall_ctl;
1916
1917 return 0;
1918}
1919
1920static int tonga_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
1921{
1922 int i;
1923 struct tonga_smumgr *smu_data =
1924 (struct tonga_smumgr *)(hwmgr->smumgr->backend);
1925
1926 /* Currently not used. Set all to zero. */
1927 for (i = 0; i < 16; i++)
1928 smu_data->power_tune_table.LPMLTemperatureScaler[i] = 0;
1929
1930 return 0;
1931}
1932
1933static int tonga_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
1934{
1935 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend);
1936
1937 if ((hwmgr->thermal_controller.advanceFanControlParameters.
1938 usFanOutputSensitivity & (1 << 15)) ||
1939 (hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity == 0))
1940 hwmgr->thermal_controller.advanceFanControlParameters.
1941 usFanOutputSensitivity = hwmgr->thermal_controller.
1942 advanceFanControlParameters.usDefaultFanOutputSensitivity;
1943
1944 smu_data->power_tune_table.FuzzyFan_PwmSetDelta =
1945 PP_HOST_TO_SMC_US(hwmgr->thermal_controller.
1946 advanceFanControlParameters.usFanOutputSensitivity);
1947 return 0;
1948}
1949
1950static int tonga_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
1951{
1952 int i;
1953 struct tonga_smumgr *smu_data =
1954 (struct tonga_smumgr *)(hwmgr->smumgr->backend);
1955
1956 /* Currently not used. Set all to zero. */
1957 for (i = 0; i < 16; i++)
1958 smu_data->power_tune_table.GnbLPML[i] = 0;
1959
1960 return 0;
1961}
1962
1963static int tonga_min_max_vgnb_lpml_id_from_bapm_vddc(struct pp_hwmgr *hwmgr)
1964{
1965 return 0;
1966}
1967
1968static int tonga_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
1969{
1970 struct tonga_smumgr *smu_data =
1971 (struct tonga_smumgr *)(hwmgr->smumgr->backend);
1972 struct phm_ppt_v1_information *table_info =
1973 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1974 uint16_t hi_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
1975 uint16_t lo_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
1976 struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table;
1977
1978 hi_sidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
1979 lo_sidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256);
1980
1981 smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd =
1982 CONVERT_FROM_HOST_TO_SMC_US(hi_sidd);
1983 smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd =
1984 CONVERT_FROM_HOST_TO_SMC_US(lo_sidd);
1985
1986 return 0;
1987}
1988
1989static int tonga_populate_pm_fuses(struct pp_hwmgr *hwmgr)
1990{
1991 struct tonga_smumgr *smu_data =
1992 (struct tonga_smumgr *)(hwmgr->smumgr->backend);
1993 uint32_t pm_fuse_table_offset;
1994
1995 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1996 PHM_PlatformCaps_PowerContainment)) {
1997 if (tonga_read_smc_sram_dword(hwmgr->smumgr,
1998 SMU72_FIRMWARE_HEADER_LOCATION +
1999 offsetof(SMU72_Firmware_Header, PmFuseTable),
2000 &pm_fuse_table_offset, SMC_RAM_END))
2001 PP_ASSERT_WITH_CODE(false,
2002 "Attempt to get pm_fuse_table_offset Failed !",
2003 return -EINVAL);
2004
2005 /* DW6 */
2006 if (tonga_populate_svi_load_line(hwmgr))
2007 PP_ASSERT_WITH_CODE(false,
2008 "Attempt to populate SviLoadLine Failed !",
2009 return -EINVAL);
2010 /* DW7 */
2011 if (tonga_populate_tdc_limit(hwmgr))
2012 PP_ASSERT_WITH_CODE(false,
2013 "Attempt to populate TDCLimit Failed !",
2014 return -EINVAL);
2015 /* DW8 */
2016 if (tonga_populate_dw8(hwmgr, pm_fuse_table_offset))
2017 PP_ASSERT_WITH_CODE(false,
2018 "Attempt to populate TdcWaterfallCtl Failed !",
2019 return -EINVAL);
2020
2021 /* DW9-DW12 */
2022 if (tonga_populate_temperature_scaler(hwmgr) != 0)
2023 PP_ASSERT_WITH_CODE(false,
2024 "Attempt to populate LPMLTemperatureScaler Failed !",
2025 return -EINVAL);
2026
2027 /* DW13-DW14 */
2028 if (tonga_populate_fuzzy_fan(hwmgr))
2029 PP_ASSERT_WITH_CODE(false,
2030 "Attempt to populate Fuzzy Fan "
2031 "Control parameters Failed !",
2032 return -EINVAL);
2033
2034 /* DW15-DW18 */
2035 if (tonga_populate_gnb_lpml(hwmgr))
2036 PP_ASSERT_WITH_CODE(false,
2037 "Attempt to populate GnbLPML Failed !",
2038 return -EINVAL);
2039
2040 /* DW19 */
2041 if (tonga_min_max_vgnb_lpml_id_from_bapm_vddc(hwmgr))
2042 PP_ASSERT_WITH_CODE(false,
2043 "Attempt to populate GnbLPML "
2044 "Min and Max Vid Failed !",
2045 return -EINVAL);
2046
2047 /* DW20 */
2048 if (tonga_populate_bapm_vddc_base_leakage_sidd(hwmgr))
2049 PP_ASSERT_WITH_CODE(
2050 false,
2051 "Attempt to populate BapmVddCBaseLeakage "
2052 "Hi and Lo Sidd Failed !",
2053 return -EINVAL);
2054
2055 if (tonga_copy_bytes_to_smc(hwmgr->smumgr, pm_fuse_table_offset,
2056 (uint8_t *)&smu_data->power_tune_table,
2057 sizeof(struct SMU72_Discrete_PmFuses), SMC_RAM_END))
2058 PP_ASSERT_WITH_CODE(false,
2059 "Attempt to download PmFuseTable Failed !",
2060 return -EINVAL);
2061 }
2062 return 0;
2063}
2064
2065static int tonga_populate_mc_reg_address(struct pp_smumgr *smumgr,
2066 SMU72_Discrete_MCRegisters *mc_reg_table)
2067{
2068 const struct tonga_smumgr *smu_data = (struct tonga_smumgr *)smumgr->backend;
2069
2070 uint32_t i, j;
2071
2072 for (i = 0, j = 0; j < smu_data->mc_reg_table.last; j++) {
2073 if (smu_data->mc_reg_table.validflag & 1<<j) {
2074 PP_ASSERT_WITH_CODE(
2075 i < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE,
2076 "Index of mc_reg_table->address[] array "
2077 "out of boundary",
2078 return -EINVAL);
2079 mc_reg_table->address[i].s0 =
2080 PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s0);
2081 mc_reg_table->address[i].s1 =
2082 PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s1);
2083 i++;
2084 }
2085 }
2086
2087 mc_reg_table->last = (uint8_t)i;
2088
2089 return 0;
2090}
2091
2092/*convert register values from driver to SMC format */
2093static void tonga_convert_mc_registers(
2094 const struct tonga_mc_reg_entry *entry,
2095 SMU72_Discrete_MCRegisterSet *data,
2096 uint32_t num_entries, uint32_t valid_flag)
2097{
2098 uint32_t i, j;
2099
2100 for (i = 0, j = 0; j < num_entries; j++) {
2101 if (valid_flag & 1<<j) {
2102 data->value[i] = PP_HOST_TO_SMC_UL(entry->mc_data[j]);
2103 i++;
2104 }
2105 }
2106}
2107
2108static int tonga_convert_mc_reg_table_entry_to_smc(
2109 struct pp_smumgr *smumgr,
2110 const uint32_t memory_clock,
2111 SMU72_Discrete_MCRegisterSet *mc_reg_table_data
2112 )
2113{
2114 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(smumgr->backend);
2115 uint32_t i = 0;
2116
2117 for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) {
2118 if (memory_clock <=
2119 smu_data->mc_reg_table.mc_reg_table_entry[i].mclk_max) {
2120 break;
2121 }
2122 }
2123
2124 if ((i == smu_data->mc_reg_table.num_entries) && (i > 0))
2125 --i;
2126
2127 tonga_convert_mc_registers(&smu_data->mc_reg_table.mc_reg_table_entry[i],
2128 mc_reg_table_data, smu_data->mc_reg_table.last,
2129 smu_data->mc_reg_table.validflag);
2130
2131 return 0;
2132}
2133
2134static int tonga_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
2135 SMU72_Discrete_MCRegisters *mc_regs)
2136{
2137 int result = 0;
2138 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2139 int res;
2140 uint32_t i;
2141
2142 for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
2143 res = tonga_convert_mc_reg_table_entry_to_smc(
2144 hwmgr->smumgr,
2145 data->dpm_table.mclk_table.dpm_levels[i].value,
2146 &mc_regs->data[i]
2147 );
2148
2149 if (0 != res)
2150 result = res;
2151 }
2152
2153 return result;
2154}
2155
2156static int tonga_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
2157{
2158 struct pp_smumgr *smumgr = hwmgr->smumgr;
2159 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(smumgr->backend);
2160 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2161 uint32_t address;
2162 int32_t result;
2163
2164 if (0 == (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
2165 return 0;
2166
2167
2168 memset(&smu_data->mc_regs, 0, sizeof(SMU72_Discrete_MCRegisters));
2169
2170 result = tonga_convert_mc_reg_table_to_smc(hwmgr, &(smu_data->mc_regs));
2171
2172 if (result != 0)
2173 return result;
2174
2175
2176 address = smu_data->mc_reg_table_start +
2177 (uint32_t)offsetof(SMU72_Discrete_MCRegisters, data[0]);
2178
2179 return tonga_copy_bytes_to_smc(
2180 hwmgr->smumgr, address,
2181 (uint8_t *)&smu_data->mc_regs.data[0],
2182 sizeof(SMU72_Discrete_MCRegisterSet) *
2183 data->dpm_table.mclk_table.count,
2184 SMC_RAM_END);
2185}
2186
2187static int tonga_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
2188{
2189 int result;
2190 struct pp_smumgr *smumgr = hwmgr->smumgr;
2191 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(smumgr->backend);
2192
2193 memset(&smu_data->mc_regs, 0x00, sizeof(SMU72_Discrete_MCRegisters));
2194 result = tonga_populate_mc_reg_address(smumgr, &(smu_data->mc_regs));
2195 PP_ASSERT_WITH_CODE(0 == result,
2196 "Failed to initialize MCRegTable for the MC register addresses !",
2197 return result;);
2198
2199 result = tonga_convert_mc_reg_table_to_smc(hwmgr, &smu_data->mc_regs);
2200 PP_ASSERT_WITH_CODE(0 == result,
2201 "Failed to initialize MCRegTable for driver state !",
2202 return result;);
2203
2204 return tonga_copy_bytes_to_smc(smumgr, smu_data->mc_reg_table_start,
2205 (uint8_t *)&smu_data->mc_regs, sizeof(SMU72_Discrete_MCRegisters), SMC_RAM_END);
2206}
2207
2208static void tonga_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
2209{
2210 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend);
2211 struct phm_ppt_v1_information *table_info =
2212 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2213
2214 if (table_info &&
2215 table_info->cac_dtp_table->usPowerTuneDataSetID <= POWERTUNE_DEFAULT_SET_MAX &&
2216 table_info->cac_dtp_table->usPowerTuneDataSetID)
2217 smu_data->power_tune_defaults =
2218 &tonga_power_tune_data_set_array
2219 [table_info->cac_dtp_table->usPowerTuneDataSetID - 1];
2220 else
2221 smu_data->power_tune_defaults = &tonga_power_tune_data_set_array[0];
2222}
2223
2224/**
2225 * Initializes the SMC table and uploads it
2226 *
2227 * @param hwmgr the address of the powerplay hardware manager.
2228 * @param pInput the pointer to input data (PowerState)
2229 * @return always 0
2230 */
2231int tonga_init_smc_table(struct pp_hwmgr *hwmgr)
2232{
2233 int result;
2234 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2235 struct tonga_smumgr *smu_data =
2236 (struct tonga_smumgr *)(hwmgr->smumgr->backend);
2237 SMU72_Discrete_DpmTable *table = &(smu_data->smc_state_table);
2238 struct phm_ppt_v1_information *table_info =
2239 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2240
2241 uint8_t i;
2242 pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
2243
2244
2245 memset(&(smu_data->smc_state_table), 0x00, sizeof(smu_data->smc_state_table));
2246
2247 tonga_initialize_power_tune_defaults(hwmgr);
2248
2249 if (SMU7_VOLTAGE_CONTROL_NONE != data->voltage_control)
2250 tonga_populate_smc_voltage_tables(hwmgr, table);
2251
2252 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2253 PHM_PlatformCaps_AutomaticDCTransition))
2254 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
2255
2256
2257 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2258 PHM_PlatformCaps_StepVddc))
2259 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
2260
2261 if (data->is_memory_gddr5)
2262 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
2263
2264 i = PHM_READ_FIELD(hwmgr->device, CC_MC_MAX_CHANNEL, NOOFCHAN);
2265
2266 if (i == 1 || i == 0)
2267 table->SystemFlags |= 0x40;
2268
2269 if (data->ulv_supported && table_info->us_ulv_voltage_offset) {
2270 result = tonga_populate_ulv_state(hwmgr, table);
2271 PP_ASSERT_WITH_CODE(0 == result,
2272 "Failed to initialize ULV state !",
2273 return result;);
2274
2275 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2276 ixCG_ULV_PARAMETER, 0x40035);
2277 }
2278
2279 result = tonga_populate_smc_link_level(hwmgr, table);
2280 PP_ASSERT_WITH_CODE(0 == result,
2281 "Failed to initialize Link Level !", return result);
2282
2283 result = tonga_populate_all_graphic_levels(hwmgr);
2284 PP_ASSERT_WITH_CODE(0 == result,
2285 "Failed to initialize Graphics Level !", return result);
2286
2287 result = tonga_populate_all_memory_levels(hwmgr);
2288 PP_ASSERT_WITH_CODE(0 == result,
2289 "Failed to initialize Memory Level !", return result);
2290
2291 result = tonga_populate_smc_acpi_level(hwmgr, table);
2292 PP_ASSERT_WITH_CODE(0 == result,
2293 "Failed to initialize ACPI Level !", return result);
2294
2295 result = tonga_populate_smc_vce_level(hwmgr, table);
2296 PP_ASSERT_WITH_CODE(0 == result,
2297 "Failed to initialize VCE Level !", return result);
2298
2299 result = tonga_populate_smc_acp_level(hwmgr, table);
2300 PP_ASSERT_WITH_CODE(0 == result,
2301 "Failed to initialize ACP Level !", return result);
2302
2303 result = tonga_populate_smc_samu_level(hwmgr, table);
2304 PP_ASSERT_WITH_CODE(0 == result,
2305 "Failed to initialize SAMU Level !", return result);
2306
2307 /* Since only the initial state is completely set up at this
2308 * point (the other states are just copies of the boot state) we only
2309 * need to populate the ARB settings for the initial state.
2310 */
2311 result = tonga_program_memory_timing_parameters(hwmgr);
2312 PP_ASSERT_WITH_CODE(0 == result,
2313 "Failed to Write ARB settings for the initial state.",
2314 return result;);
2315
2316 result = tonga_populate_smc_uvd_level(hwmgr, table);
2317 PP_ASSERT_WITH_CODE(0 == result,
2318 "Failed to initialize UVD Level !", return result);
2319
2320 result = tonga_populate_smc_boot_level(hwmgr, table);
2321 PP_ASSERT_WITH_CODE(0 == result,
2322 "Failed to initialize Boot Level !", return result);
2323
2324 tonga_populate_bapm_parameters_in_dpm_table(hwmgr);
2325 PP_ASSERT_WITH_CODE(0 == result,
2326 "Failed to populate BAPM Parameters !", return result);
2327
2328 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2329 PHM_PlatformCaps_ClockStretcher)) {
2330 result = tonga_populate_clock_stretcher_data_table(hwmgr);
2331 PP_ASSERT_WITH_CODE(0 == result,
2332 "Failed to populate Clock Stretcher Data Table !",
2333 return result;);
2334 }
2335 table->GraphicsVoltageChangeEnable = 1;
2336 table->GraphicsThermThrottleEnable = 1;
2337 table->GraphicsInterval = 1;
2338 table->VoltageInterval = 1;
2339 table->ThermalInterval = 1;
2340 table->TemperatureLimitHigh =
2341 table_info->cac_dtp_table->usTargetOperatingTemp *
2342 SMU7_Q88_FORMAT_CONVERSION_UNIT;
2343 table->TemperatureLimitLow =
2344 (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
2345 SMU7_Q88_FORMAT_CONVERSION_UNIT;
2346 table->MemoryVoltageChangeEnable = 1;
2347 table->MemoryInterval = 1;
2348 table->VoltageResponseTime = 0;
2349 table->PhaseResponseTime = 0;
2350 table->MemoryThermThrottleEnable = 1;
2351
2352 /*
2353 * Cail reads current link status and reports it as cap (we cannot
2354 * change this due to some previous issues we had)
2355 * SMC drops the link status to lowest level after enabling
2356 * DPM by PowerPlay. After pnp or toggling CF, driver gets reloaded again
2357 * but this time Cail reads current link status which was set to low by
2358 * SMC and reports it as cap to powerplay
2359 * To avoid it, we set PCIeBootLinkLevel to highest dpm level
2360 */
2361 PP_ASSERT_WITH_CODE((1 <= data->dpm_table.pcie_speed_table.count),
2362 "There must be 1 or more PCIE levels defined in PPTable.",
2363 return -EINVAL);
2364
2365 table->PCIeBootLinkLevel = (uint8_t) (data->dpm_table.pcie_speed_table.count);
2366
2367 table->PCIeGenInterval = 1;
2368
2369 result = tonga_populate_vr_config(hwmgr, table);
2370 PP_ASSERT_WITH_CODE(0 == result,
2371 "Failed to populate VRConfig setting !", return result);
2372
2373 table->ThermGpio = 17;
2374 table->SclkStepSize = 0x4000;
2375
2376 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID,
2377 &gpio_pin_assignment)) {
2378 table->VRHotGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
2379 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2380 PHM_PlatformCaps_RegulatorHot);
2381 } else {
2382 table->VRHotGpio = SMU7_UNUSED_GPIO_PIN;
2383 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2384 PHM_PlatformCaps_RegulatorHot);
2385 }
2386
2387 if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
2388 &gpio_pin_assignment)) {
2389 table->AcDcGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
2390 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2391 PHM_PlatformCaps_AutomaticDCTransition);
2392 } else {
2393 table->AcDcGpio = SMU7_UNUSED_GPIO_PIN;
2394 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2395 PHM_PlatformCaps_AutomaticDCTransition);
2396 }
2397
2398 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2399 PHM_PlatformCaps_Falcon_QuickTransition);
2400
2401 if (0) {
2402 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2403 PHM_PlatformCaps_AutomaticDCTransition);
2404 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2405 PHM_PlatformCaps_Falcon_QuickTransition);
2406 }
2407
2408 if (atomctrl_get_pp_assign_pin(hwmgr,
2409 THERMAL_INT_OUTPUT_GPIO_PINID, &gpio_pin_assignment)) {
2410 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2411 PHM_PlatformCaps_ThermalOutGPIO);
2412
2413 table->ThermOutGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
2414
2415 table->ThermOutPolarity =
2416 (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) &
2417 (1 << gpio_pin_assignment.uc_gpio_pin_bit_shift))) ? 1 : 0;
2418
2419 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
2420
2421 /* if required, combine VRHot/PCC with thermal out GPIO*/
2422 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2423 PHM_PlatformCaps_RegulatorHot) &&
2424 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2425 PHM_PlatformCaps_CombinePCCWithThermalSignal)){
2426 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
2427 }
2428 } else {
2429 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2430 PHM_PlatformCaps_ThermalOutGPIO);
2431
2432 table->ThermOutGpio = 17;
2433 table->ThermOutPolarity = 1;
2434 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
2435 }
2436
2437 for (i = 0; i < SMU72_MAX_ENTRIES_SMIO; i++)
2438 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
2439
2440 CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2441 CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
2442 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
2443 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
2444 CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
2445 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2446 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2447 CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2448 CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2449
2450 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2451 result = tonga_copy_bytes_to_smc(
2452 hwmgr->smumgr,
2453 smu_data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable, SystemFlags),
2454 (uint8_t *)&(table->SystemFlags),
2455 sizeof(SMU72_Discrete_DpmTable) - 3 * sizeof(SMU72_PIDController),
2456 SMC_RAM_END);
2457
2458 PP_ASSERT_WITH_CODE(0 == result,
2459 "Failed to upload dpm data to SMC memory !", return result;);
2460
2461 result = tonga_init_arb_table_index(hwmgr->smumgr);
2462 PP_ASSERT_WITH_CODE(0 == result,
2463 "Failed to upload arb data to SMC memory !", return result);
2464
2465 tonga_populate_pm_fuses(hwmgr);
2466 PP_ASSERT_WITH_CODE((0 == result),
2467 "Failed to populate initialize pm fuses !", return result);
2468
2469 result = tonga_populate_initial_mc_reg_table(hwmgr);
2470 PP_ASSERT_WITH_CODE((0 == result),
2471 "Failed to populate initialize MC Reg table !", return result);
2472
2473 return 0;
2474}
2475
2476/**
2477* Set up the fan table to control the fan using the SMC.
2478* @param hwmgr the address of the powerplay hardware manager.
2479* @param pInput the pointer to input data
2480* @param pOutput the pointer to output data
2481* @param pStorage the pointer to temporary storage
2482* @param Result the last failure code
2483* @return result from set temperature range routine
2484*/
2485int tonga_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
2486{
2487 struct tonga_smumgr *smu_data =
2488 (struct tonga_smumgr *)(hwmgr->smumgr->backend);
2489 SMU72_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
2490 uint32_t duty100;
2491 uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;
2492 uint16_t fdo_min, slope1, slope2;
2493 uint32_t reference_clock;
2494 int res;
2495 uint64_t tmp64;
2496
2497 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2498 PHM_PlatformCaps_MicrocodeFanControl))
2499 return 0;
2500
2501 if (0 == smu_data->fan_table_start) {
2502 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2503 PHM_PlatformCaps_MicrocodeFanControl);
2504 return 0;
2505 }
2506
2507 duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
2508 CGS_IND_REG__SMC,
2509 CG_FDO_CTRL1, FMAX_DUTY100);
2510
2511 if (0 == duty100) {
2512 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2513 PHM_PlatformCaps_MicrocodeFanControl);
2514 return 0;
2515 }
2516
2517 tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin * duty100;
2518 do_div(tmp64, 10000);
2519 fdo_min = (uint16_t)tmp64;
2520
2521 t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed -
2522 hwmgr->thermal_controller.advanceFanControlParameters.usTMin;
2523 t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh -
2524 hwmgr->thermal_controller.advanceFanControlParameters.usTMed;
2525
2526 pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed -
2527 hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin;
2528 pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh -
2529 hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed;
2530
2531 slope1 = (uint16_t)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
2532 slope2 = (uint16_t)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
2533
2534 fan_table.TempMin = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMin) / 100);
2535 fan_table.TempMed = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMed) / 100);
2536 fan_table.TempMax = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMax) / 100);
2537
2538 fan_table.Slope1 = cpu_to_be16(slope1);
2539 fan_table.Slope2 = cpu_to_be16(slope2);
2540
2541 fan_table.FdoMin = cpu_to_be16(fdo_min);
2542
2543 fan_table.HystDown = cpu_to_be16(hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst);
2544
2545 fan_table.HystUp = cpu_to_be16(1);
2546
2547 fan_table.HystSlope = cpu_to_be16(1);
2548
2549 fan_table.TempRespLim = cpu_to_be16(5);
2550
2551 reference_clock = smu7_get_xclk(hwmgr);
2552
2553 fan_table.RefreshPeriod = cpu_to_be32((hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay * reference_clock) / 1600);
2554
2555 fan_table.FdoMax = cpu_to_be16((uint16_t)duty100);
2556
2557 fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_MULT_THERMAL_CTRL, TEMP_SEL);
2558
2559 fan_table.FanControl_GL_Flag = 1;
2560
2561 res = tonga_copy_bytes_to_smc(hwmgr->smumgr, smu_data->fan_table_start, (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), SMC_RAM_END);
2562/* TO DO FOR SOME DEVICE ID 0X692b, send this msg return invalid command.
2563 if (res == 0 && hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit != 0)
2564 res = (0 == smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetFanMinPwm, \
2565 hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit) ? 0 : -1);
2566
2567 if (res == 0 && hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit != 0)
2568 res = (0 == smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetFanSclkTarget, \
2569 hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit) ? 0 : -1);
2570
2571 if (0 != res)
2572 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl);
2573*/
2574 return 0;
2575}
2576
2577
2578static int tonga_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
2579{
2580 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2581
2582 if (data->need_update_smu7_dpm_table &
2583 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
2584 return tonga_program_memory_timing_parameters(hwmgr);
2585
2586 return 0;
2587}
2588
2589int tonga_update_sclk_threshold(struct pp_hwmgr *hwmgr)
2590{
2591 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2592 struct tonga_smumgr *smu_data =
2593 (struct tonga_smumgr *)(hwmgr->smumgr->backend);
2594
2595 int result = 0;
2596 uint32_t low_sclk_interrupt_threshold = 0;
2597
2598 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2599 PHM_PlatformCaps_SclkThrottleLowNotification)
2600 && (hwmgr->gfx_arbiter.sclk_threshold !=
2601 data->low_sclk_interrupt_threshold)) {
2602 data->low_sclk_interrupt_threshold =
2603 hwmgr->gfx_arbiter.sclk_threshold;
2604 low_sclk_interrupt_threshold =
2605 data->low_sclk_interrupt_threshold;
2606
2607 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
2608
2609 result = tonga_copy_bytes_to_smc(
2610 hwmgr->smumgr,
2611 smu_data->dpm_table_start +
2612 offsetof(SMU72_Discrete_DpmTable,
2613 LowSclkInterruptThreshold),
2614 (uint8_t *)&low_sclk_interrupt_threshold,
2615 sizeof(uint32_t),
2616 SMC_RAM_END);
2617 }
2618
2619 result = tonga_update_and_upload_mc_reg_table(hwmgr);
2620
2621 PP_ASSERT_WITH_CODE((0 == result),
2622 "Failed to upload MC reg table !",
2623 return result);
2624
2625 result = tonga_program_mem_timing_parameters(hwmgr);
2626 PP_ASSERT_WITH_CODE((result == 0),
2627 "Failed to program memory timing parameters !",
2628 );
2629
2630 return result;
2631}
2632
2633uint32_t tonga_get_offsetof(uint32_t type, uint32_t member)
2634{
2635 switch (type) {
2636 case SMU_SoftRegisters:
2637 switch (member) {
2638 case HandshakeDisables:
2639 return offsetof(SMU72_SoftRegisters, HandshakeDisables);
2640 case VoltageChangeTimeout:
2641 return offsetof(SMU72_SoftRegisters, VoltageChangeTimeout);
2642 case AverageGraphicsActivity:
2643 return offsetof(SMU72_SoftRegisters, AverageGraphicsActivity);
2644 case PreVBlankGap:
2645 return offsetof(SMU72_SoftRegisters, PreVBlankGap);
2646 case VBlankTimeout:
2647 return offsetof(SMU72_SoftRegisters, VBlankTimeout);
2648 }
2649 case SMU_Discrete_DpmTable:
2650 switch (member) {
2651 case UvdBootLevel:
2652 return offsetof(SMU72_Discrete_DpmTable, UvdBootLevel);
2653 case VceBootLevel:
2654 return offsetof(SMU72_Discrete_DpmTable, VceBootLevel);
2655 case SamuBootLevel:
2656 return offsetof(SMU72_Discrete_DpmTable, SamuBootLevel);
2657 case LowSclkInterruptThreshold:
2658 return offsetof(SMU72_Discrete_DpmTable, LowSclkInterruptThreshold);
2659 }
2660 }
2661 printk("cant't get the offset of type %x member %x\n", type, member);
2662 return 0;
2663}
2664
2665uint32_t tonga_get_mac_definition(uint32_t value)
2666{
2667 switch (value) {
2668 case SMU_MAX_LEVELS_GRAPHICS:
2669 return SMU72_MAX_LEVELS_GRAPHICS;
2670 case SMU_MAX_LEVELS_MEMORY:
2671 return SMU72_MAX_LEVELS_MEMORY;
2672 case SMU_MAX_LEVELS_LINK:
2673 return SMU72_MAX_LEVELS_LINK;
2674 case SMU_MAX_ENTRIES_SMIO:
2675 return SMU72_MAX_ENTRIES_SMIO;
2676 case SMU_MAX_LEVELS_VDDC:
2677 return SMU72_MAX_LEVELS_VDDC;
2678 case SMU_MAX_LEVELS_VDDGFX:
2679 return SMU72_MAX_LEVELS_VDDGFX;
2680 case SMU_MAX_LEVELS_VDDCI:
2681 return SMU72_MAX_LEVELS_VDDCI;
2682 case SMU_MAX_LEVELS_MVDD:
2683 return SMU72_MAX_LEVELS_MVDD;
2684 }
2685 printk("cant't get the mac value %x\n", value);
2686
2687 return 0;
2688}
2689
2690
2691static int tonga_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
2692{
2693 struct tonga_smumgr *smu_data =
2694 (struct tonga_smumgr *)(hwmgr->smumgr->backend);
2695 uint32_t mm_boot_level_offset, mm_boot_level_value;
2696 struct phm_ppt_v1_information *table_info =
2697 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2698
2699 smu_data->smc_state_table.UvdBootLevel = 0;
2700 if (table_info->mm_dep_table->count > 0)
2701 smu_data->smc_state_table.UvdBootLevel =
2702 (uint8_t) (table_info->mm_dep_table->count - 1);
2703 mm_boot_level_offset = smu_data->dpm_table_start +
2704 offsetof(SMU72_Discrete_DpmTable, UvdBootLevel);
2705 mm_boot_level_offset /= 4;
2706 mm_boot_level_offset *= 4;
2707 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
2708 CGS_IND_REG__SMC, mm_boot_level_offset);
2709 mm_boot_level_value &= 0x00FFFFFF;
2710 mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;
2711 cgs_write_ind_register(hwmgr->device,
2712 CGS_IND_REG__SMC,
2713 mm_boot_level_offset, mm_boot_level_value);
2714
2715 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2716 PHM_PlatformCaps_UVDDPM) ||
2717 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2718 PHM_PlatformCaps_StablePState))
2719 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
2720 PPSMC_MSG_UVDDPM_SetEnabledMask,
2721 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel));
2722 return 0;
2723}
2724
2725static int tonga_update_vce_smc_table(struct pp_hwmgr *hwmgr)
2726{
2727 struct tonga_smumgr *smu_data =
2728 (struct tonga_smumgr *)(hwmgr->smumgr->backend);
2729 uint32_t mm_boot_level_offset, mm_boot_level_value;
2730 struct phm_ppt_v1_information *table_info =
2731 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2732
2733
2734 smu_data->smc_state_table.VceBootLevel =
2735 (uint8_t) (table_info->mm_dep_table->count - 1);
2736
2737 mm_boot_level_offset = smu_data->dpm_table_start +
2738 offsetof(SMU72_Discrete_DpmTable, VceBootLevel);
2739 mm_boot_level_offset /= 4;
2740 mm_boot_level_offset *= 4;
2741 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
2742 CGS_IND_REG__SMC, mm_boot_level_offset);
2743 mm_boot_level_value &= 0xFF00FFFF;
2744 mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;
2745 cgs_write_ind_register(hwmgr->device,
2746 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
2747
2748 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2749 PHM_PlatformCaps_StablePState))
2750 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
2751 PPSMC_MSG_VCEDPM_SetEnabledMask,
2752 (uint32_t)1 << smu_data->smc_state_table.VceBootLevel);
2753 return 0;
2754}
2755
2756static int tonga_update_samu_smc_table(struct pp_hwmgr *hwmgr)
2757{
2758 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend);
2759 uint32_t mm_boot_level_offset, mm_boot_level_value;
2760
2761 smu_data->smc_state_table.SamuBootLevel = 0;
2762 mm_boot_level_offset = smu_data->dpm_table_start +
2763 offsetof(SMU72_Discrete_DpmTable, SamuBootLevel);
2764
2765 mm_boot_level_offset /= 4;
2766 mm_boot_level_offset *= 4;
2767 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
2768 CGS_IND_REG__SMC, mm_boot_level_offset);
2769 mm_boot_level_value &= 0xFFFFFF00;
2770 mm_boot_level_value |= smu_data->smc_state_table.SamuBootLevel << 0;
2771 cgs_write_ind_register(hwmgr->device,
2772 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
2773
2774 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2775 PHM_PlatformCaps_StablePState))
2776 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
2777 PPSMC_MSG_SAMUDPM_SetEnabledMask,
2778 (uint32_t)(1 << smu_data->smc_state_table.SamuBootLevel));
2779 return 0;
2780}
2781
2782int tonga_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
2783{
2784 switch (type) {
2785 case SMU_UVD_TABLE:
2786 tonga_update_uvd_smc_table(hwmgr);
2787 break;
2788 case SMU_VCE_TABLE:
2789 tonga_update_vce_smc_table(hwmgr);
2790 break;
2791 case SMU_SAMU_TABLE:
2792 tonga_update_samu_smc_table(hwmgr);
2793 break;
2794 default:
2795 break;
2796 }
2797 return 0;
2798}
2799
2800
2801/**
2802 * Get the location of various tables inside the FW image.
2803 *
2804 * @param hwmgr the address of the powerplay hardware manager.
2805 * @return always 0
2806 */
2807int tonga_process_firmware_header(struct pp_hwmgr *hwmgr)
2808{
2809 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2810 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend);
2811
2812 uint32_t tmp;
2813 int result;
2814 bool error = false;
2815
2816 result = tonga_read_smc_sram_dword(hwmgr->smumgr,
2817 SMU72_FIRMWARE_HEADER_LOCATION +
2818 offsetof(SMU72_Firmware_Header, DpmTable),
2819 &tmp, SMC_RAM_END);
2820
2821 if (0 == result)
2822 smu_data->dpm_table_start = tmp;
2823
2824 error |= (0 != result);
2825
2826 result = tonga_read_smc_sram_dword(hwmgr->smumgr,
2827 SMU72_FIRMWARE_HEADER_LOCATION +
2828 offsetof(SMU72_Firmware_Header, SoftRegisters),
2829 &tmp, SMC_RAM_END);
2830
2831 if (0 == result) {
2832 data->soft_regs_start = tmp;
2833 smu_data->soft_regs_start = tmp;
2834 }
2835
2836 error |= (0 != result);
2837
2838
2839 result = tonga_read_smc_sram_dword(hwmgr->smumgr,
2840 SMU72_FIRMWARE_HEADER_LOCATION +
2841 offsetof(SMU72_Firmware_Header, mcRegisterTable),
2842 &tmp, SMC_RAM_END);
2843
2844 if (0 == result)
2845 smu_data->mc_reg_table_start = tmp;
2846
2847
2848 result = tonga_read_smc_sram_dword(hwmgr->smumgr,
2849 SMU72_FIRMWARE_HEADER_LOCATION +
2850 offsetof(SMU72_Firmware_Header, FanTable),
2851 &tmp, SMC_RAM_END);
2852
2853 if (0 == result)
2854 smu_data->fan_table_start = tmp;
2855
2856 error |= (0 != result);
2857
2858 result = tonga_read_smc_sram_dword(hwmgr->smumgr,
2859 SMU72_FIRMWARE_HEADER_LOCATION +
2860 offsetof(SMU72_Firmware_Header, mcArbDramTimingTable),
2861 &tmp, SMC_RAM_END);
2862
2863 if (0 == result)
2864 smu_data->arb_table_start = tmp;
2865
2866 error |= (0 != result);
2867
2868 result = tonga_read_smc_sram_dword(hwmgr->smumgr,
2869 SMU72_FIRMWARE_HEADER_LOCATION +
2870 offsetof(SMU72_Firmware_Header, Version),
2871 &tmp, SMC_RAM_END);
2872
2873 if (0 == result)
2874 hwmgr->microcode_version_info.SMC = tmp;
2875
2876 error |= (0 != result);
2877
2878 return error ? 1 : 0;
2879}
2880
2881/*---------------------------MC----------------------------*/
2882
2883static uint8_t tonga_get_memory_modile_index(struct pp_hwmgr *hwmgr)
2884{
2885 return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));
2886}
2887
2888static bool tonga_check_s0_mc_reg_index(uint16_t in_reg, uint16_t *out_reg)
2889{
2890 bool result = true;
2891
2892 switch (in_reg) {
2893 case mmMC_SEQ_RAS_TIMING:
2894 *out_reg = mmMC_SEQ_RAS_TIMING_LP;
2895 break;
2896
2897 case mmMC_SEQ_DLL_STBY:
2898 *out_reg = mmMC_SEQ_DLL_STBY_LP;
2899 break;
2900
2901 case mmMC_SEQ_G5PDX_CMD0:
2902 *out_reg = mmMC_SEQ_G5PDX_CMD0_LP;
2903 break;
2904
2905 case mmMC_SEQ_G5PDX_CMD1:
2906 *out_reg = mmMC_SEQ_G5PDX_CMD1_LP;
2907 break;
2908
2909 case mmMC_SEQ_G5PDX_CTRL:
2910 *out_reg = mmMC_SEQ_G5PDX_CTRL_LP;
2911 break;
2912
2913 case mmMC_SEQ_CAS_TIMING:
2914 *out_reg = mmMC_SEQ_CAS_TIMING_LP;
2915 break;
2916
2917 case mmMC_SEQ_MISC_TIMING:
2918 *out_reg = mmMC_SEQ_MISC_TIMING_LP;
2919 break;
2920
2921 case mmMC_SEQ_MISC_TIMING2:
2922 *out_reg = mmMC_SEQ_MISC_TIMING2_LP;
2923 break;
2924
2925 case mmMC_SEQ_PMG_DVS_CMD:
2926 *out_reg = mmMC_SEQ_PMG_DVS_CMD_LP;
2927 break;
2928
2929 case mmMC_SEQ_PMG_DVS_CTL:
2930 *out_reg = mmMC_SEQ_PMG_DVS_CTL_LP;
2931 break;
2932
2933 case mmMC_SEQ_RD_CTL_D0:
2934 *out_reg = mmMC_SEQ_RD_CTL_D0_LP;
2935 break;
2936
2937 case mmMC_SEQ_RD_CTL_D1:
2938 *out_reg = mmMC_SEQ_RD_CTL_D1_LP;
2939 break;
2940
2941 case mmMC_SEQ_WR_CTL_D0:
2942 *out_reg = mmMC_SEQ_WR_CTL_D0_LP;
2943 break;
2944
2945 case mmMC_SEQ_WR_CTL_D1:
2946 *out_reg = mmMC_SEQ_WR_CTL_D1_LP;
2947 break;
2948
2949 case mmMC_PMG_CMD_EMRS:
2950 *out_reg = mmMC_SEQ_PMG_CMD_EMRS_LP;
2951 break;
2952
2953 case mmMC_PMG_CMD_MRS:
2954 *out_reg = mmMC_SEQ_PMG_CMD_MRS_LP;
2955 break;
2956
2957 case mmMC_PMG_CMD_MRS1:
2958 *out_reg = mmMC_SEQ_PMG_CMD_MRS1_LP;
2959 break;
2960
2961 case mmMC_SEQ_PMG_TIMING:
2962 *out_reg = mmMC_SEQ_PMG_TIMING_LP;
2963 break;
2964
2965 case mmMC_PMG_CMD_MRS2:
2966 *out_reg = mmMC_SEQ_PMG_CMD_MRS2_LP;
2967 break;
2968
2969 case mmMC_SEQ_WR_CTL_2:
2970 *out_reg = mmMC_SEQ_WR_CTL_2_LP;
2971 break;
2972
2973 default:
2974 result = false;
2975 break;
2976 }
2977
2978 return result;
2979}
2980
2981static int tonga_set_s0_mc_reg_index(struct tonga_mc_reg_table *table)
2982{
2983 uint32_t i;
2984 uint16_t address;
2985
2986 for (i = 0; i < table->last; i++) {
2987 table->mc_reg_address[i].s0 =
2988 tonga_check_s0_mc_reg_index(table->mc_reg_address[i].s1,
2989 &address) ?
2990 address :
2991 table->mc_reg_address[i].s1;
2992 }
2993 return 0;
2994}
2995
2996static int tonga_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table,
2997 struct tonga_mc_reg_table *ni_table)
2998{
2999 uint8_t i, j;
3000
3001 PP_ASSERT_WITH_CODE((table->last <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3002 "Invalid VramInfo table.", return -EINVAL);
3003 PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES),
3004 "Invalid VramInfo table.", return -EINVAL);
3005
3006 for (i = 0; i < table->last; i++)
3007 ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
3008
3009 ni_table->last = table->last;
3010
3011 for (i = 0; i < table->num_entries; i++) {
3012 ni_table->mc_reg_table_entry[i].mclk_max =
3013 table->mc_reg_table_entry[i].mclk_max;
3014 for (j = 0; j < table->last; j++) {
3015 ni_table->mc_reg_table_entry[i].mc_data[j] =
3016 table->mc_reg_table_entry[i].mc_data[j];
3017 }
3018 }
3019
3020 ni_table->num_entries = table->num_entries;
3021
3022 return 0;
3023}
3024
3025/**
3026 * VBIOS omits some information to reduce size, we need to recover them here.
3027 * 1. when we see mmMC_SEQ_MISC1, bit[31:16] EMRS1, need to be write to
3028 * mmMC_PMG_CMD_EMRS /_LP[15:0]. Bit[15:0] MRS, need to be update
3029 * mmMC_PMG_CMD_MRS/_LP[15:0]
3030 * 2. when we see mmMC_SEQ_RESERVE_M, bit[15:0] EMRS2, need to be write to
3031 * mmMC_PMG_CMD_MRS1/_LP[15:0].
3032 * 3. need to set these data for each clock range
3033 * @param hwmgr the address of the powerplay hardware manager.
3034 * @param table the address of MCRegTable
3035 * @return always 0
3036 */
3037static int tonga_set_mc_special_registers(struct pp_hwmgr *hwmgr,
3038 struct tonga_mc_reg_table *table)
3039{
3040 uint8_t i, j, k;
3041 uint32_t temp_reg;
3042 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3043
3044 for (i = 0, j = table->last; i < table->last; i++) {
3045 PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3046 "Invalid VramInfo table.", return -EINVAL);
3047
3048 switch (table->mc_reg_address[i].s1) {
3049
3050 case mmMC_SEQ_MISC1:
3051 temp_reg = cgs_read_register(hwmgr->device,
3052 mmMC_PMG_CMD_EMRS);
3053 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
3054 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP;
3055 for (k = 0; k < table->num_entries; k++) {
3056 table->mc_reg_table_entry[k].mc_data[j] =
3057 ((temp_reg & 0xffff0000)) |
3058 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
3059 }
3060 j++;
3061 PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3062 "Invalid VramInfo table.", return -EINVAL);
3063
3064 temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS);
3065 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
3066 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
3067 for (k = 0; k < table->num_entries; k++) {
3068 table->mc_reg_table_entry[k].mc_data[j] =
3069 (temp_reg & 0xffff0000) |
3070 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
3071
3072 if (!data->is_memory_gddr5)
3073 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
3074 }
3075 j++;
3076 PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3077 "Invalid VramInfo table.", return -EINVAL);
3078
3079 if (!data->is_memory_gddr5) {
3080 table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
3081 table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
3082 for (k = 0; k < table->num_entries; k++)
3083 table->mc_reg_table_entry[k].mc_data[j] =
3084 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
3085 j++;
3086 PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3087 "Invalid VramInfo table.", return -EINVAL);
3088 }
3089
3090 break;
3091
3092 case mmMC_SEQ_RESERVE_M:
3093 temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1);
3094 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1;
3095 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP;
3096 for (k = 0; k < table->num_entries; k++) {
3097 table->mc_reg_table_entry[k].mc_data[j] =
3098 (temp_reg & 0xffff0000) |
3099 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
3100 }
3101 j++;
3102 PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3103 "Invalid VramInfo table.", return -EINVAL);
3104 break;
3105
3106 default:
3107 break;
3108 }
3109
3110 }
3111
3112 table->last = j;
3113
3114 return 0;
3115}
3116
3117static int tonga_set_valid_flag(struct tonga_mc_reg_table *table)
3118{
3119 uint8_t i, j;
3120
3121 for (i = 0; i < table->last; i++) {
3122 for (j = 1; j < table->num_entries; j++) {
3123 if (table->mc_reg_table_entry[j-1].mc_data[i] !=
3124 table->mc_reg_table_entry[j].mc_data[i]) {
3125 table->validflag |= (1<<i);
3126 break;
3127 }
3128 }
3129 }
3130
3131 return 0;
3132}
3133
3134int tonga_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
3135{
3136 int result;
3137 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend);
3138 pp_atomctrl_mc_reg_table *table;
3139 struct tonga_mc_reg_table *ni_table = &smu_data->mc_reg_table;
3140 uint8_t module_index = tonga_get_memory_modile_index(hwmgr);
3141
3142 table = kzalloc(sizeof(pp_atomctrl_mc_reg_table), GFP_KERNEL);
3143
3144 if (NULL == table)
3145 return -ENOMEM;
3146
3147 /* Program additional LP registers that are no longer programmed by VBIOS */
3148 cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP,
3149 cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
3150 cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP,
3151 cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
3152 cgs_write_register(hwmgr->device, mmMC_SEQ_DLL_STBY_LP,
3153 cgs_read_register(hwmgr->device, mmMC_SEQ_DLL_STBY));
3154 cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0_LP,
3155 cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0));
3156 cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1_LP,
3157 cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1));
3158 cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL_LP,
3159 cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL));
3160 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD_LP,
3161 cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD));
3162 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL_LP,
3163 cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL));
3164 cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING_LP,
3165 cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING));
3166 cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP,
3167 cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
3168 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_EMRS_LP,
3169 cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS));
3170 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS_LP,
3171 cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS));
3172 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS1_LP,
3173 cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1));
3174 cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP,
3175 cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0));
3176 cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP,
3177 cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
3178 cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP,
3179 cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
3180 cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP,
3181 cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
3182 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP,
3183 cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
3184 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP,
3185 cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2));
3186 cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP,
3187 cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2));
3188
3189 memset(table, 0x00, sizeof(pp_atomctrl_mc_reg_table));
3190
3191 result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table);
3192
3193 if (0 == result)
3194 result = tonga_copy_vbios_smc_reg_table(table, ni_table);
3195
3196 if (0 == result) {
3197 tonga_set_s0_mc_reg_index(ni_table);
3198 result = tonga_set_mc_special_registers(hwmgr, ni_table);
3199 }
3200
3201 if (0 == result)
3202 tonga_set_valid_flag(ni_table);
3203
3204 kfree(table);
3205
3206 return result;
3207}
3208
3209bool tonga_is_dpm_running(struct pp_hwmgr *hwmgr)
3210{
3211 return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
3212 CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
3213 ? true : false;
3214}
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.h b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.h
new file mode 100644
index 000000000000..8ae169ff541d
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.h
@@ -0,0 +1,60 @@
1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef _TONGA_SMC_H
24#define _TONGA_SMC_H
25
26#include "smumgr.h"
27#include "smu72.h"
28
29
30#define ASICID_IS_TONGA_P(wDID, bRID) \
31 (((wDID == 0x6930) && ((bRID == 0xF0) || (bRID == 0xF1) || (bRID == 0xFF))) \
32 || ((wDID == 0x6920) && ((bRID == 0) || (bRID == 1))))
33
34
35struct tonga_pt_defaults {
36 uint8_t svi_load_line_en;
37 uint8_t svi_load_line_vddC;
38 uint8_t tdc_vddc_throttle_release_limit_perc;
39 uint8_t tdc_mawt;
40 uint8_t tdc_waterfall_ctl;
41 uint8_t dte_ambient_temp_base;
42 uint32_t display_cac;
43 uint32_t bamp_temp_gradient;
44 uint16_t bapmti_r[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS];
45 uint16_t bapmti_rc[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS];
46};
47
48int tonga_populate_all_graphic_levels(struct pp_hwmgr *hwmgr);
49int tonga_populate_all_memory_levels(struct pp_hwmgr *hwmgr);
50int tonga_init_smc_table(struct pp_hwmgr *hwmgr);
51int tonga_thermal_setup_fan_table(struct pp_hwmgr *hwmgr);
52int tonga_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type);
53int tonga_update_sclk_threshold(struct pp_hwmgr *hwmgr);
54uint32_t tonga_get_offsetof(uint32_t type, uint32_t member);
55uint32_t tonga_get_mac_definition(uint32_t value);
56int tonga_process_firmware_header(struct pp_hwmgr *hwmgr);
57int tonga_initialize_mc_reg_table(struct pp_hwmgr *hwmgr);
58bool tonga_is_dpm_running(struct pp_hwmgr *hwmgr);
59#endif
60
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
index f42c536b3af1..b543d6c0f96a 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
@@ -33,6 +33,7 @@
33#include "smu/smu_7_1_2_d.h" 33#include "smu/smu_7_1_2_d.h"
34#include "smu/smu_7_1_2_sh_mask.h" 34#include "smu/smu_7_1_2_sh_mask.h"
35#include "cgs_common.h" 35#include "cgs_common.h"
36#include "tonga_smc.h"
36 37
37#define TONGA_SMC_SIZE 0x20000 38#define TONGA_SMC_SIZE 0x20000
38#define BUFFER_SIZE 80000 39#define BUFFER_SIZE 80000
@@ -749,6 +750,8 @@ static int tonga_smu_init(struct pp_smumgr *smumgr)
749 struct tonga_smumgr *tonga_smu; 750 struct tonga_smumgr *tonga_smu;
750 uint8_t *internal_buf; 751 uint8_t *internal_buf;
751 uint64_t mc_addr = 0; 752 uint64_t mc_addr = 0;
753 int i;
754
752 /* Allocate memory for backend private data */ 755 /* Allocate memory for backend private data */
753 tonga_smu = (struct tonga_smumgr *)(smumgr->backend); 756 tonga_smu = (struct tonga_smumgr *)(smumgr->backend);
754 tonga_smu->header_buffer.data_size = 757 tonga_smu->header_buffer.data_size =
@@ -793,6 +796,9 @@ static int tonga_smu_init(struct pp_smumgr *smumgr)
793 (cgs_handle_t)tonga_smu->smu_buffer.handle); 796 (cgs_handle_t)tonga_smu->smu_buffer.handle);
794 return -1;); 797 return -1;);
795 798
799 for (i = 0; i < SMU72_MAX_LEVELS_GRAPHICS; i++)
800 tonga_smu->activity_target[i] = 30;
801
796 return 0; 802 return 0;
797} 803}
798 804
@@ -807,6 +813,17 @@ static const struct pp_smumgr_func tonga_smu_funcs = {
807 .send_msg_to_smc_with_parameter = &tonga_send_msg_to_smc_with_parameter, 813 .send_msg_to_smc_with_parameter = &tonga_send_msg_to_smc_with_parameter,
808 .download_pptable_settings = NULL, 814 .download_pptable_settings = NULL,
809 .upload_pptable_settings = NULL, 815 .upload_pptable_settings = NULL,
816 .update_smc_table = tonga_update_smc_table,
817 .get_offsetof = tonga_get_offsetof,
818 .process_firmware_header = tonga_process_firmware_header,
819 .init_smc_table = tonga_init_smc_table,
820 .update_sclk_threshold = tonga_update_sclk_threshold,
821 .thermal_setup_fan_table = tonga_thermal_setup_fan_table,
822 .populate_all_graphic_levels = tonga_populate_all_graphic_levels,
823 .populate_all_memory_levels = tonga_populate_all_memory_levels,
824 .get_mac_definition = tonga_get_mac_definition,
825 .initialize_mc_reg_table = tonga_initialize_mc_reg_table,
826 .is_dpm_running = tonga_is_dpm_running,
810}; 827};
811 828
812int tonga_smum_init(struct pp_smumgr *smumgr) 829int tonga_smum_init(struct pp_smumgr *smumgr)
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.h
index 33c788d7f05c..b2ad232506c1 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.h
@@ -24,6 +24,10 @@
24#ifndef _TONGA_SMUMGR_H_ 24#ifndef _TONGA_SMUMGR_H_
25#define _TONGA_SMUMGR_H_ 25#define _TONGA_SMUMGR_H_
26 26
27#include "smu72_discrete.h"
28
29#define SMC_RAM_END 0x40000
30
27struct tonga_buffer_entry { 31struct tonga_buffer_entry {
28 uint32_t data_size; 32 uint32_t data_size;
29 uint32_t mc_addr_low; 33 uint32_t mc_addr_low;
@@ -32,13 +36,44 @@ struct tonga_buffer_entry {
32 unsigned long handle; 36 unsigned long handle;
33}; 37};
34 38
39
40struct tonga_mc_reg_entry {
41 uint32_t mclk_max;
42 uint32_t mc_data[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE];
43};
44
45struct tonga_mc_reg_table {
46 uint8_t last; /* number of registers*/
47 uint8_t num_entries; /* number of entries in mc_reg_table_entry used*/
48 uint16_t validflag; /* indicate the corresponding register is valid or not. 1: valid, 0: invalid. bit0->address[0], bit1->address[1], etc.*/
49 struct tonga_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];
50 SMU72_Discrete_MCRegisterAddress mc_reg_address[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE];
51};
52
53
35struct tonga_smumgr { 54struct tonga_smumgr {
36 uint8_t *pHeader; 55 uint8_t *pHeader;
37 uint8_t *pMecImage; 56 uint8_t *pMecImage;
38 uint32_t ulSoftRegsStart; 57
58
59 uint32_t soft_regs_start;
60 uint32_t dpm_table_start;
61 uint32_t mc_reg_table_start;
62 uint32_t fan_table_start;
63 uint32_t arb_table_start;
39 64
40 struct tonga_buffer_entry header_buffer; 65 struct tonga_buffer_entry header_buffer;
41 struct tonga_buffer_entry smu_buffer; 66 struct tonga_buffer_entry smu_buffer;
67
68 struct SMU72_Discrete_DpmTable smc_state_table;
69 struct SMU72_Discrete_Ulv ulv_setting;
70 struct SMU72_Discrete_PmFuses power_tune_table;
71 struct tonga_pt_defaults *power_tune_defaults;
72 SMU72_Discrete_MCRegisters mc_regs;
73 struct tonga_mc_reg_table mc_reg_table;
74
75 uint32_t activity_target[SMU72_MAX_LEVELS_GRAPHICS];
76
42}; 77};
43 78
44extern int tonga_smum_init(struct pp_smumgr *smumgr); 79extern int tonga_smum_init(struct pp_smumgr *smumgr);
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-31 14:24:12 -0400