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authorGreg Kroah-Hartman <gregkh@linuxfoundation.org>2014-03-02 23:09:08 -0500
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2014-03-02 23:09:08 -0500
commit13df7977431e3b906a23bb75f29e0f40a8d73f87 (patch)
treebc2c78c3b816a65f90c31cccebdc15b38352c045 /drivers/gpu
parent6d8b3e1ad3d3815d9c87b8553493301e243af76a (diff)
parent0414855fdc4a40da05221fc6062cccbc0c30f169 (diff)
Merge 3.14-rc5 into driver-core-next
We want the fixes in here.
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/drm_ioctl.c12
-rw-r--r--drivers/gpu/drm/i2c/tda998x_drv.c4
-rw-r--r--drivers/gpu/drm/i915/intel_display.c14
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c19
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c21
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.h1
-rw-r--r--drivers/gpu/drm/nouveau/Makefile1
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/device/nv40.c10
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/disp/nv50.c2
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c2
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/nv50.c2
-rw-r--r--drivers/gpu/drm/nouveau/core/include/subdev/mc.h1
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/bios/base.c4
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/fb/nv1a.c2
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/mc/nv04.h1
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/mc/nv44.c2
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/mc/nv4c.c45
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_acpi.c26
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bo.c2
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drm.c3
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_vga.c4
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c31
-rw-r--r--drivers/gpu/drm/radeon/atombios_encoders.c7
-rw-r--r--drivers/gpu/drm/radeon/dce6_afmt.c15
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c4
-rw-r--r--drivers/gpu/drm/radeon/evergreen_hdmi.c26
-rw-r--r--drivers/gpu/drm/radeon/ni_dpm.c2
-rw-r--r--drivers/gpu/drm/radeon/r600_audio.c14
-rw-r--r--drivers/gpu/drm/radeon/r600_hdmi.c15
-rw-r--r--drivers/gpu/drm/radeon/radeon.h10
-rw-r--r--drivers/gpu/drm/radeon/radeon_atpx_handler.c3
-rw-r--r--drivers/gpu/drm/radeon/radeon_display.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_kms.c6
-rw-r--r--drivers/gpu/drm/radeon/radeon_ring.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_semaphore.c19
-rw-r--r--drivers/gpu/drm/radeon/radeon_uvd.c2
-rw-r--r--drivers/gpu/drm/radeon/rv770.c2
-rw-r--r--drivers/gpu/drm/radeon/rv770_dpm.c9
-rw-r--r--drivers/gpu/drm/radeon/si_dpm.c2
-rw-r--r--drivers/gpu/drm/tegra/drm.c2
-rw-r--r--drivers/gpu/drm/tegra/rgb.c11
-rw-r--r--drivers/gpu/drm/ttm/ttm_agp_backend.c1
-rw-r--r--drivers/gpu/drm/vmwgfx/svga3d_reg.h129
-rw-r--r--drivers/gpu/drm/vmwgfx/svga3d_surfacedefs.h11
-rw-r--r--drivers/gpu/drm/vmwgfx/svga_reg.h9
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_context.c9
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_drv.c3
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_drv.h3
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c9
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c3
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_mob.c35
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_resource.c3
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_shader.c16
-rw-r--r--drivers/gpu/host1x/job.c2
54 files changed, 415 insertions, 180 deletions
diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
index dffc836144cc..f4dc9b7a3831 100644
--- a/drivers/gpu/drm/drm_ioctl.c
+++ b/drivers/gpu/drm/drm_ioctl.c
@@ -296,6 +296,18 @@ int drm_getcap(struct drm_device *dev, void *data, struct drm_file *file_priv)
296 case DRM_CAP_ASYNC_PAGE_FLIP: 296 case DRM_CAP_ASYNC_PAGE_FLIP:
297 req->value = dev->mode_config.async_page_flip; 297 req->value = dev->mode_config.async_page_flip;
298 break; 298 break;
299 case DRM_CAP_CURSOR_WIDTH:
300 if (dev->mode_config.cursor_width)
301 req->value = dev->mode_config.cursor_width;
302 else
303 req->value = 64;
304 break;
305 case DRM_CAP_CURSOR_HEIGHT:
306 if (dev->mode_config.cursor_height)
307 req->value = dev->mode_config.cursor_height;
308 else
309 req->value = 64;
310 break;
299 default: 311 default:
300 return -EINVAL; 312 return -EINVAL;
301 } 313 }
diff --git a/drivers/gpu/drm/i2c/tda998x_drv.c b/drivers/gpu/drm/i2c/tda998x_drv.c
index fa18cf374470..faa77f543a07 100644
--- a/drivers/gpu/drm/i2c/tda998x_drv.c
+++ b/drivers/gpu/drm/i2c/tda998x_drv.c
@@ -1151,8 +1151,10 @@ tda998x_encoder_init(struct i2c_client *client,
1151 1151
1152 priv->current_page = 0xff; 1152 priv->current_page = 0xff;
1153 priv->cec = i2c_new_dummy(client->adapter, 0x34); 1153 priv->cec = i2c_new_dummy(client->adapter, 0x34);
1154 if (!priv->cec) 1154 if (!priv->cec) {
1155 kfree(priv);
1155 return -ENODEV; 1156 return -ENODEV;
1157 }
1156 priv->dpms = DRM_MODE_DPMS_OFF; 1158 priv->dpms = DRM_MODE_DPMS_OFF;
1157 1159
1158 encoder_slave->slave_priv = priv; 1160 encoder_slave->slave_priv = priv;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9fa24347963a..4c1672809493 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8586,6 +8586,20 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
8586 if (ring->id == RCS) 8586 if (ring->id == RCS)
8587 len += 6; 8587 len += 6;
8588 8588
8589 /*
8590 * BSpec MI_DISPLAY_FLIP for IVB:
8591 * "The full packet must be contained within the same cache line."
8592 *
8593 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
8594 * cacheline, if we ever start emitting more commands before
8595 * the MI_DISPLAY_FLIP we may need to first emit everything else,
8596 * then do the cacheline alignment, and finally emit the
8597 * MI_DISPLAY_FLIP.
8598 */
8599 ret = intel_ring_cacheline_align(ring);
8600 if (ret)
8601 goto err_unpin;
8602
8589 ret = intel_ring_begin(ring, len); 8603 ret = intel_ring_begin(ring, len);
8590 if (ret) 8604 if (ret)
8591 goto err_unpin; 8605 goto err_unpin;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 2f517b85b3f4..57552eb386b0 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -537,6 +537,7 @@ intel_dp_aux_native_write(struct intel_dp *intel_dp,
537 uint8_t msg[20]; 537 uint8_t msg[20];
538 int msg_bytes; 538 int msg_bytes;
539 uint8_t ack; 539 uint8_t ack;
540 int retry;
540 541
541 if (WARN_ON(send_bytes > 16)) 542 if (WARN_ON(send_bytes > 16))
542 return -E2BIG; 543 return -E2BIG;
@@ -548,19 +549,21 @@ intel_dp_aux_native_write(struct intel_dp *intel_dp,
548 msg[3] = send_bytes - 1; 549 msg[3] = send_bytes - 1;
549 memcpy(&msg[4], send, send_bytes); 550 memcpy(&msg[4], send, send_bytes);
550 msg_bytes = send_bytes + 4; 551 msg_bytes = send_bytes + 4;
551 for (;;) { 552 for (retry = 0; retry < 7; retry++) {
552 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); 553 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
553 if (ret < 0) 554 if (ret < 0)
554 return ret; 555 return ret;
555 ack >>= 4; 556 ack >>= 4;
556 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) 557 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)
557 break; 558 return send_bytes;
558 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER) 559 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
559 udelay(100); 560 usleep_range(400, 500);
560 else 561 else
561 return -EIO; 562 return -EIO;
562 } 563 }
563 return send_bytes; 564
565 DRM_ERROR("too many retries, giving up\n");
566 return -EIO;
564} 567}
565 568
566/* Write a single byte to the aux channel in native mode */ 569/* Write a single byte to the aux channel in native mode */
@@ -582,6 +585,7 @@ intel_dp_aux_native_read(struct intel_dp *intel_dp,
582 int reply_bytes; 585 int reply_bytes;
583 uint8_t ack; 586 uint8_t ack;
584 int ret; 587 int ret;
588 int retry;
585 589
586 if (WARN_ON(recv_bytes > 19)) 590 if (WARN_ON(recv_bytes > 19))
587 return -E2BIG; 591 return -E2BIG;
@@ -595,7 +599,7 @@ intel_dp_aux_native_read(struct intel_dp *intel_dp,
595 msg_bytes = 4; 599 msg_bytes = 4;
596 reply_bytes = recv_bytes + 1; 600 reply_bytes = recv_bytes + 1;
597 601
598 for (;;) { 602 for (retry = 0; retry < 7; retry++) {
599 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, 603 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
600 reply, reply_bytes); 604 reply, reply_bytes);
601 if (ret == 0) 605 if (ret == 0)
@@ -608,10 +612,13 @@ intel_dp_aux_native_read(struct intel_dp *intel_dp,
608 return ret - 1; 612 return ret - 1;
609 } 613 }
610 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER) 614 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
611 udelay(100); 615 usleep_range(400, 500);
612 else 616 else
613 return -EIO; 617 return -EIO;
614 } 618 }
619
620 DRM_ERROR("too many retries, giving up\n");
621 return -EIO;
615} 622}
616 623
617static int 624static int
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index b7f1742caf87..31b36c5ac894 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1653,6 +1653,27 @@ int intel_ring_begin(struct intel_ring_buffer *ring,
1653 return 0; 1653 return 0;
1654} 1654}
1655 1655
1656/* Align the ring tail to a cacheline boundary */
1657int intel_ring_cacheline_align(struct intel_ring_buffer *ring)
1658{
1659 int num_dwords = (64 - (ring->tail & 63)) / sizeof(uint32_t);
1660 int ret;
1661
1662 if (num_dwords == 0)
1663 return 0;
1664
1665 ret = intel_ring_begin(ring, num_dwords);
1666 if (ret)
1667 return ret;
1668
1669 while (num_dwords--)
1670 intel_ring_emit(ring, MI_NOOP);
1671
1672 intel_ring_advance(ring);
1673
1674 return 0;
1675}
1676
1656void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno) 1677void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno)
1657{ 1678{
1658 struct drm_i915_private *dev_priv = ring->dev->dev_private; 1679 struct drm_i915_private *dev_priv = ring->dev->dev_private;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 71a73f4fe252..0b243ce33714 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -233,6 +233,7 @@ intel_write_status_page(struct intel_ring_buffer *ring,
233void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring); 233void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);
234 234
235int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n); 235int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n);
236int __must_check intel_ring_cacheline_align(struct intel_ring_buffer *ring);
236static inline void intel_ring_emit(struct intel_ring_buffer *ring, 237static inline void intel_ring_emit(struct intel_ring_buffer *ring,
237 u32 data) 238 u32 data)
238{ 239{
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
index e88145ba1bf5..d310c195bdfe 100644
--- a/drivers/gpu/drm/nouveau/Makefile
+++ b/drivers/gpu/drm/nouveau/Makefile
@@ -141,6 +141,7 @@ nouveau-y += core/subdev/mc/base.o
141nouveau-y += core/subdev/mc/nv04.o 141nouveau-y += core/subdev/mc/nv04.o
142nouveau-y += core/subdev/mc/nv40.o 142nouveau-y += core/subdev/mc/nv40.o
143nouveau-y += core/subdev/mc/nv44.o 143nouveau-y += core/subdev/mc/nv44.o
144nouveau-y += core/subdev/mc/nv4c.o
144nouveau-y += core/subdev/mc/nv50.o 145nouveau-y += core/subdev/mc/nv50.o
145nouveau-y += core/subdev/mc/nv94.o 146nouveau-y += core/subdev/mc/nv94.o
146nouveau-y += core/subdev/mc/nv98.o 147nouveau-y += core/subdev/mc/nv98.o
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv40.c b/drivers/gpu/drm/nouveau/core/engine/device/nv40.c
index 1b653dd74a70..08b88591ed60 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nv40.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nv40.c
@@ -311,7 +311,7 @@ nv40_identify(struct nouveau_device *device)
311 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 311 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
312 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 312 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
313 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; 313 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
314 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; 314 device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
315 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; 315 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
316 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 316 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
317 device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; 317 device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
@@ -334,7 +334,7 @@ nv40_identify(struct nouveau_device *device)
334 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 334 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
335 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 335 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
336 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; 336 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
337 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; 337 device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
338 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; 338 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
339 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 339 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
340 device->oclass[NVDEV_SUBDEV_FB ] = nv4e_fb_oclass; 340 device->oclass[NVDEV_SUBDEV_FB ] = nv4e_fb_oclass;
@@ -357,7 +357,7 @@ nv40_identify(struct nouveau_device *device)
357 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 357 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
358 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 358 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
359 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; 359 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
360 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; 360 device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
361 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; 361 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
362 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 362 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
363 device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; 363 device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
@@ -380,7 +380,7 @@ nv40_identify(struct nouveau_device *device)
380 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 380 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
381 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 381 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
382 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; 382 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
383 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; 383 device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
384 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; 384 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
385 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 385 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
386 device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; 386 device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
@@ -403,7 +403,7 @@ nv40_identify(struct nouveau_device *device)
403 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 403 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
404 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 404 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
405 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; 405 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
406 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; 406 device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
407 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; 407 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
408 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 408 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
409 device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; 409 device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
index 940eaa5d8b9a..9ad722e4e087 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
@@ -1142,7 +1142,7 @@ nv50_disp_intr_unk20_2(struct nv50_disp_priv *priv, int head)
1142 if (conf != ~0) { 1142 if (conf != ~0) {
1143 if (outp.location == 0 && outp.type == DCB_OUTPUT_DP) { 1143 if (outp.location == 0 && outp.type == DCB_OUTPUT_DP) {
1144 u32 soff = (ffs(outp.or) - 1) * 0x08; 1144 u32 soff = (ffs(outp.or) - 1) * 0x08;
1145 u32 ctrl = nv_rd32(priv, 0x610798 + soff); 1145 u32 ctrl = nv_rd32(priv, 0x610794 + soff);
1146 u32 datarate; 1146 u32 datarate;
1147 1147
1148 switch ((ctrl & 0x000f0000) >> 16) { 1148 switch ((ctrl & 0x000f0000) >> 16) {
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
index 9a850fe19515..54c1b5b471cd 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
@@ -112,7 +112,7 @@ nve0_fifo_runlist_update(struct nve0_fifo_priv *priv, u32 engine)
112 112
113 nv_wr32(priv, 0x002270, cur->addr >> 12); 113 nv_wr32(priv, 0x002270, cur->addr >> 12);
114 nv_wr32(priv, 0x002274, (engine << 20) | (p >> 3)); 114 nv_wr32(priv, 0x002274, (engine << 20) | (p >> 3));
115 if (!nv_wait(priv, 0x002284 + (engine * 4), 0x00100000, 0x00000000)) 115 if (!nv_wait(priv, 0x002284 + (engine * 8), 0x00100000, 0x00000000))
116 nv_error(priv, "runlist %d update timeout\n", engine); 116 nv_error(priv, "runlist %d update timeout\n", engine);
117 mutex_unlock(&nv_subdev(priv)->mutex); 117 mutex_unlock(&nv_subdev(priv)->mutex);
118} 118}
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
index 30ed19c52e05..7a367c402978 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
@@ -539,7 +539,7 @@ nv50_priv_tp_trap(struct nv50_graph_priv *priv, int type, u32 ustatus_old,
539 ustatus &= ~0x04030000; 539 ustatus &= ~0x04030000;
540 } 540 }
541 if (ustatus && display) { 541 if (ustatus && display) {
542 nv_error("%s - TP%d:", name, i); 542 nv_error(priv, "%s - TP%d:", name, i);
543 nouveau_bitfield_print(nv50_mpc_traps, ustatus); 543 nouveau_bitfield_print(nv50_mpc_traps, ustatus);
544 pr_cont("\n"); 544 pr_cont("\n");
545 ustatus = 0; 545 ustatus = 0;
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/mc.h b/drivers/gpu/drm/nouveau/core/include/subdev/mc.h
index adc88b73d911..3c6738edd127 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/mc.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/mc.h
@@ -47,6 +47,7 @@ struct nouveau_mc_oclass {
47extern struct nouveau_oclass *nv04_mc_oclass; 47extern struct nouveau_oclass *nv04_mc_oclass;
48extern struct nouveau_oclass *nv40_mc_oclass; 48extern struct nouveau_oclass *nv40_mc_oclass;
49extern struct nouveau_oclass *nv44_mc_oclass; 49extern struct nouveau_oclass *nv44_mc_oclass;
50extern struct nouveau_oclass *nv4c_mc_oclass;
50extern struct nouveau_oclass *nv50_mc_oclass; 51extern struct nouveau_oclass *nv50_mc_oclass;
51extern struct nouveau_oclass *nv94_mc_oclass; 52extern struct nouveau_oclass *nv94_mc_oclass;
52extern struct nouveau_oclass *nv98_mc_oclass; 53extern struct nouveau_oclass *nv98_mc_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/base.c b/drivers/gpu/drm/nouveau/core/subdev/bios/base.c
index aa0fbbec7f08..ef0c9c4a8cc3 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/bios/base.c
@@ -130,6 +130,10 @@ nouveau_bios_shadow_prom(struct nouveau_bios *bios)
130 u16 pcir; 130 u16 pcir;
131 int i; 131 int i;
132 132
133 /* there is no prom on nv4x IGP's */
134 if (device->card_type == NV_40 && device->chipset >= 0x4c)
135 return;
136
133 /* enable access to rom */ 137 /* enable access to rom */
134 if (device->card_type >= NV_50) 138 if (device->card_type >= NV_50)
135 pcireg = 0x088050; 139 pcireg = 0x088050;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv1a.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv1a.c
index 9159a5ccee93..265d1253624a 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv1a.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nv1a.c
@@ -36,7 +36,7 @@ nv1a_fb_oclass = &(struct nv04_fb_impl) {
36 .fini = _nouveau_fb_fini, 36 .fini = _nouveau_fb_fini,
37 }, 37 },
38 .base.memtype = nv04_fb_memtype_valid, 38 .base.memtype = nv04_fb_memtype_valid,
39 .base.ram = &nv10_ram_oclass, 39 .base.ram = &nv1a_ram_oclass,
40 .tile.regions = 8, 40 .tile.regions = 8,
41 .tile.init = nv10_fb_tile_init, 41 .tile.init = nv10_fb_tile_init,
42 .tile.fini = nv10_fb_tile_fini, 42 .tile.fini = nv10_fb_tile_fini,
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nv04.h b/drivers/gpu/drm/nouveau/core/subdev/mc/nv04.h
index b0d5c31606c1..81a408e7d034 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/mc/nv04.h
+++ b/drivers/gpu/drm/nouveau/core/subdev/mc/nv04.h
@@ -14,6 +14,7 @@ int nv04_mc_ctor(struct nouveau_object *, struct nouveau_object *,
14extern const struct nouveau_mc_intr nv04_mc_intr[]; 14extern const struct nouveau_mc_intr nv04_mc_intr[];
15int nv04_mc_init(struct nouveau_object *); 15int nv04_mc_init(struct nouveau_object *);
16void nv40_mc_msi_rearm(struct nouveau_mc *); 16void nv40_mc_msi_rearm(struct nouveau_mc *);
17int nv44_mc_init(struct nouveau_object *object);
17int nv50_mc_init(struct nouveau_object *); 18int nv50_mc_init(struct nouveau_object *);
18extern const struct nouveau_mc_intr nv50_mc_intr[]; 19extern const struct nouveau_mc_intr nv50_mc_intr[];
19extern const struct nouveau_mc_intr nvc0_mc_intr[]; 20extern const struct nouveau_mc_intr nvc0_mc_intr[];
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nv44.c b/drivers/gpu/drm/nouveau/core/subdev/mc/nv44.c
index 3bfee5c6c4f2..cc4d0d2d886e 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/mc/nv44.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/mc/nv44.c
@@ -24,7 +24,7 @@
24 24
25#include "nv04.h" 25#include "nv04.h"
26 26
27static int 27int
28nv44_mc_init(struct nouveau_object *object) 28nv44_mc_init(struct nouveau_object *object)
29{ 29{
30 struct nv04_mc_priv *priv = (void *)object; 30 struct nv04_mc_priv *priv = (void *)object;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nv4c.c b/drivers/gpu/drm/nouveau/core/subdev/mc/nv4c.c
new file mode 100644
index 000000000000..a75c35ccf25c
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/mc/nv4c.c
@@ -0,0 +1,45 @@
1/*
2 * Copyright 2014 Ilia Mirkin
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ilia Mirkin
23 */
24
25#include "nv04.h"
26
27static void
28nv4c_mc_msi_rearm(struct nouveau_mc *pmc)
29{
30 struct nv04_mc_priv *priv = (void *)pmc;
31 nv_wr08(priv, 0x088050, 0xff);
32}
33
34struct nouveau_oclass *
35nv4c_mc_oclass = &(struct nouveau_mc_oclass) {
36 .base.handle = NV_SUBDEV(MC, 0x4c),
37 .base.ofuncs = &(struct nouveau_ofuncs) {
38 .ctor = nv04_mc_ctor,
39 .dtor = _nouveau_mc_dtor,
40 .init = nv44_mc_init,
41 .fini = _nouveau_mc_fini,
42 },
43 .intr = nv04_mc_intr,
44 .msi_rearm = nv4c_mc_msi_rearm,
45}.base;
diff --git a/drivers/gpu/drm/nouveau/nouveau_acpi.c b/drivers/gpu/drm/nouveau/nouveau_acpi.c
index 4ef83df2b246..83face3f608f 100644
--- a/drivers/gpu/drm/nouveau/nouveau_acpi.c
+++ b/drivers/gpu/drm/nouveau/nouveau_acpi.c
@@ -106,6 +106,29 @@ static int nouveau_optimus_dsm(acpi_handle handle, int func, int arg, uint32_t *
106 return 0; 106 return 0;
107} 107}
108 108
109/*
110 * On some platforms, _DSM(nouveau_op_dsm_muid, func0) has special
111 * requirements on the fourth parameter, so a private implementation
112 * instead of using acpi_check_dsm().
113 */
114static int nouveau_check_optimus_dsm(acpi_handle handle)
115{
116 int result;
117
118 /*
119 * Function 0 returns a Buffer containing available functions.
120 * The args parameter is ignored for function 0, so just put 0 in it
121 */
122 if (nouveau_optimus_dsm(handle, 0, 0, &result))
123 return 0;
124
125 /*
126 * ACPI Spec v4 9.14.1: if bit 0 is zero, no function is supported.
127 * If the n-th bit is enabled, function n is supported
128 */
129 return result & 1 && result & (1 << NOUVEAU_DSM_OPTIMUS_CAPS);
130}
131
109static int nouveau_dsm(acpi_handle handle, int func, int arg) 132static int nouveau_dsm(acpi_handle handle, int func, int arg)
110{ 133{
111 int ret = 0; 134 int ret = 0;
@@ -207,8 +230,7 @@ static int nouveau_dsm_pci_probe(struct pci_dev *pdev)
207 1 << NOUVEAU_DSM_POWER)) 230 1 << NOUVEAU_DSM_POWER))
208 retval |= NOUVEAU_DSM_HAS_MUX; 231 retval |= NOUVEAU_DSM_HAS_MUX;
209 232
210 if (acpi_check_dsm(dhandle, nouveau_op_dsm_muid, 0x00000100, 233 if (nouveau_check_optimus_dsm(dhandle))
211 1 << NOUVEAU_DSM_OPTIMUS_CAPS))
212 retval |= NOUVEAU_DSM_HAS_OPT; 234 retval |= NOUVEAU_DSM_HAS_OPT;
213 235
214 if (retval & NOUVEAU_DSM_HAS_OPT) { 236 if (retval & NOUVEAU_DSM_HAS_OPT) {
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
index 488686d490c0..4aed1714b9ab 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -1249,7 +1249,7 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
1249 mem->bus.is_iomem = !dev->agp->cant_use_aperture; 1249 mem->bus.is_iomem = !dev->agp->cant_use_aperture;
1250 } 1250 }
1251#endif 1251#endif
1252 if (!node->memtype) 1252 if (nv_device(drm->device)->card_type < NV_50 || !node->memtype)
1253 /* untiled */ 1253 /* untiled */
1254 break; 1254 break;
1255 /* fallthrough, tiled memory */ 1255 /* fallthrough, tiled memory */
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c
index 78c8e7146d56..89c484d8ac26 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@ -376,6 +376,8 @@ nouveau_drm_load(struct drm_device *dev, unsigned long flags)
376 if (ret) 376 if (ret)
377 goto fail_device; 377 goto fail_device;
378 378
379 dev->irq_enabled = true;
380
379 /* workaround an odd issue on nvc1 by disabling the device's 381 /* workaround an odd issue on nvc1 by disabling the device's
380 * nosnoop capability. hopefully won't cause issues until a 382 * nosnoop capability. hopefully won't cause issues until a
381 * better fix is found - assuming there is one... 383 * better fix is found - assuming there is one...
@@ -475,6 +477,7 @@ nouveau_drm_remove(struct pci_dev *pdev)
475 struct nouveau_drm *drm = nouveau_drm(dev); 477 struct nouveau_drm *drm = nouveau_drm(dev);
476 struct nouveau_object *device; 478 struct nouveau_object *device;
477 479
480 dev->irq_enabled = false;
478 device = drm->client.base.device; 481 device = drm->client.base.device;
479 drm_put_dev(dev); 482 drm_put_dev(dev);
480 483
diff --git a/drivers/gpu/drm/nouveau/nouveau_vga.c b/drivers/gpu/drm/nouveau/nouveau_vga.c
index 81638d7f2eff..471347edc27e 100644
--- a/drivers/gpu/drm/nouveau/nouveau_vga.c
+++ b/drivers/gpu/drm/nouveau/nouveau_vga.c
@@ -14,7 +14,9 @@ nouveau_vga_set_decode(void *priv, bool state)
14{ 14{
15 struct nouveau_device *device = nouveau_dev(priv); 15 struct nouveau_device *device = nouveau_dev(priv);
16 16
17 if (device->chipset >= 0x40) 17 if (device->card_type == NV_40 && device->chipset >= 0x4c)
18 nv_wr32(device, 0x088060, state);
19 else if (device->chipset >= 0x40)
18 nv_wr32(device, 0x088054, state); 20 nv_wr32(device, 0x088054, state);
19 else 21 else
20 nv_wr32(device, 0x001854, state); 22 nv_wr32(device, 0x001854, state);
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index a9338c85630f..daa4dd375ab1 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -559,7 +559,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
559 u32 adjusted_clock = mode->clock; 559 u32 adjusted_clock = mode->clock;
560 int encoder_mode = atombios_get_encoder_mode(encoder); 560 int encoder_mode = atombios_get_encoder_mode(encoder);
561 u32 dp_clock = mode->clock; 561 u32 dp_clock = mode->clock;
562 int bpc = radeon_get_monitor_bpc(connector); 562 int bpc = radeon_crtc->bpc;
563 bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock); 563 bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);
564 564
565 /* reset the pll flags */ 565 /* reset the pll flags */
@@ -1176,7 +1176,7 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1176 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); 1176 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
1177 1177
1178 /* Set NUM_BANKS. */ 1178 /* Set NUM_BANKS. */
1179 if (rdev->family >= CHIP_BONAIRE) { 1179 if (rdev->family >= CHIP_TAHITI) {
1180 unsigned tileb, index, num_banks, tile_split_bytes; 1180 unsigned tileb, index, num_banks, tile_split_bytes;
1181 1181
1182 /* Calculate the macrotile mode index. */ 1182 /* Calculate the macrotile mode index. */
@@ -1194,13 +1194,14 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1194 return -EINVAL; 1194 return -EINVAL;
1195 } 1195 }
1196 1196
1197 num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3; 1197 if (rdev->family >= CHIP_BONAIRE)
1198 num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;
1199 else
1200 num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3;
1198 fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks); 1201 fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks);
1199 } else { 1202 } else {
1200 /* SI and older. */ 1203 /* NI and older. */
1201 if (rdev->family >= CHIP_TAHITI) 1204 if (rdev->family >= CHIP_CAYMAN)
1202 tmp = rdev->config.si.tile_config;
1203 else if (rdev->family >= CHIP_CAYMAN)
1204 tmp = rdev->config.cayman.tile_config; 1205 tmp = rdev->config.cayman.tile_config;
1205 else 1206 else
1206 tmp = rdev->config.evergreen.tile_config; 1207 tmp = rdev->config.evergreen.tile_config;
@@ -1773,6 +1774,20 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1773 return ATOM_PPLL1; 1774 return ATOM_PPLL1;
1774 DRM_ERROR("unable to allocate a PPLL\n"); 1775 DRM_ERROR("unable to allocate a PPLL\n");
1775 return ATOM_PPLL_INVALID; 1776 return ATOM_PPLL_INVALID;
1777 } else if (ASIC_IS_DCE41(rdev)) {
1778 /* Don't share PLLs on DCE4.1 chips */
1779 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1780 if (rdev->clock.dp_extclk)
1781 /* skip PPLL programming if using ext clock */
1782 return ATOM_PPLL_INVALID;
1783 }
1784 pll_in_use = radeon_get_pll_use_mask(crtc);
1785 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1786 return ATOM_PPLL1;
1787 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1788 return ATOM_PPLL2;
1789 DRM_ERROR("unable to allocate a PPLL\n");
1790 return ATOM_PPLL_INVALID;
1776 } else if (ASIC_IS_DCE4(rdev)) { 1791 } else if (ASIC_IS_DCE4(rdev)) {
1777 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, 1792 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
1778 * depending on the asic: 1793 * depending on the asic:
@@ -1800,7 +1815,7 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1800 if (pll != ATOM_PPLL_INVALID) 1815 if (pll != ATOM_PPLL_INVALID)
1801 return pll; 1816 return pll;
1802 } 1817 }
1803 } else if (!ASIC_IS_DCE41(rdev)) { /* Don't share PLLs on DCE4.1 chips */ 1818 } else {
1804 /* use the same PPLL for all monitors with the same clock */ 1819 /* use the same PPLL for all monitors with the same clock */
1805 pll = radeon_get_shared_nondp_ppll(crtc); 1820 pll = radeon_get_shared_nondp_ppll(crtc);
1806 if (pll != ATOM_PPLL_INVALID) 1821 if (pll != ATOM_PPLL_INVALID)
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c
index a42d61571f49..2cec2ab02f80 100644
--- a/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -464,11 +464,12 @@ atombios_tv_setup(struct drm_encoder *encoder, int action)
464 464
465static u8 radeon_atom_get_bpc(struct drm_encoder *encoder) 465static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
466{ 466{
467 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
468 int bpc = 8; 467 int bpc = 8;
469 468
470 if (connector) 469 if (encoder->crtc) {
471 bpc = radeon_get_monitor_bpc(connector); 470 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
471 bpc = radeon_crtc->bpc;
472 }
472 473
473 switch (bpc) { 474 switch (bpc) {
474 case 0: 475 case 0:
diff --git a/drivers/gpu/drm/radeon/dce6_afmt.c b/drivers/gpu/drm/radeon/dce6_afmt.c
index 713a5d359901..94e858751994 100644
--- a/drivers/gpu/drm/radeon/dce6_afmt.c
+++ b/drivers/gpu/drm/radeon/dce6_afmt.c
@@ -278,13 +278,15 @@ static int dce6_audio_chipset_supported(struct radeon_device *rdev)
278 return !ASIC_IS_NODCE(rdev); 278 return !ASIC_IS_NODCE(rdev);
279} 279}
280 280
281static void dce6_audio_enable(struct radeon_device *rdev, 281void dce6_audio_enable(struct radeon_device *rdev,
282 struct r600_audio_pin *pin, 282 struct r600_audio_pin *pin,
283 bool enable) 283 bool enable)
284{ 284{
285 if (!pin)
286 return;
287
285 WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOTPLUG_CONTROL, 288 WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOTPLUG_CONTROL,
286 AUDIO_ENABLED); 289 enable ? AUDIO_ENABLED : 0);
287 DRM_INFO("%s audio %d support\n", enable ? "Enabling" : "Disabling", pin->id);
288} 290}
289 291
290static const u32 pin_offsets[7] = 292static const u32 pin_offsets[7] =
@@ -323,7 +325,8 @@ int dce6_audio_init(struct radeon_device *rdev)
323 rdev->audio.pin[i].connected = false; 325 rdev->audio.pin[i].connected = false;
324 rdev->audio.pin[i].offset = pin_offsets[i]; 326 rdev->audio.pin[i].offset = pin_offsets[i];
325 rdev->audio.pin[i].id = i; 327 rdev->audio.pin[i].id = i;
326 dce6_audio_enable(rdev, &rdev->audio.pin[i], true); 328 /* disable audio. it will be set up later */
329 dce6_audio_enable(rdev, &rdev->audio.pin[i], false);
327 } 330 }
328 331
329 return 0; 332 return 0;
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index f2b9e21ce4da..8a2c010b7dc5 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1680,7 +1680,7 @@ bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
1680 case RADEON_HPD_6: 1680 case RADEON_HPD_6:
1681 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) 1681 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
1682 connected = true; 1682 connected = true;
1683 break; 1683 break;
1684 default: 1684 default:
1685 break; 1685 break;
1686 } 1686 }
@@ -5475,9 +5475,9 @@ void evergreen_fini(struct radeon_device *rdev)
5475 radeon_wb_fini(rdev); 5475 radeon_wb_fini(rdev);
5476 radeon_ib_pool_fini(rdev); 5476 radeon_ib_pool_fini(rdev);
5477 radeon_irq_kms_fini(rdev); 5477 radeon_irq_kms_fini(rdev);
5478 evergreen_pcie_gart_fini(rdev);
5479 uvd_v1_0_fini(rdev); 5478 uvd_v1_0_fini(rdev);
5480 radeon_uvd_fini(rdev); 5479 radeon_uvd_fini(rdev);
5480 evergreen_pcie_gart_fini(rdev);
5481 r600_vram_scratch_fini(rdev); 5481 r600_vram_scratch_fini(rdev);
5482 radeon_gem_fini(rdev); 5482 radeon_gem_fini(rdev);
5483 radeon_fence_driver_fini(rdev); 5483 radeon_fence_driver_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c
index 0c6d5cef4cf1..05b0c95813fd 100644
--- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
+++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
@@ -306,6 +306,15 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
306 return; 306 return;
307 offset = dig->afmt->offset; 307 offset = dig->afmt->offset;
308 308
309 /* disable audio prior to setting up hw */
310 if (ASIC_IS_DCE6(rdev)) {
311 dig->afmt->pin = dce6_audio_get_pin(rdev);
312 dce6_audio_enable(rdev, dig->afmt->pin, false);
313 } else {
314 dig->afmt->pin = r600_audio_get_pin(rdev);
315 r600_audio_enable(rdev, dig->afmt->pin, false);
316 }
317
309 evergreen_audio_set_dto(encoder, mode->clock); 318 evergreen_audio_set_dto(encoder, mode->clock);
310 319
311 WREG32(HDMI_VBI_PACKET_CONTROL + offset, 320 WREG32(HDMI_VBI_PACKET_CONTROL + offset,
@@ -409,12 +418,16 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
409 WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF); 418 WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
410 WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001); 419 WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001);
411 WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001); 420 WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001);
421
422 /* enable audio after to setting up hw */
423 if (ASIC_IS_DCE6(rdev))
424 dce6_audio_enable(rdev, dig->afmt->pin, true);
425 else
426 r600_audio_enable(rdev, dig->afmt->pin, true);
412} 427}
413 428
414void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable) 429void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable)
415{ 430{
416 struct drm_device *dev = encoder->dev;
417 struct radeon_device *rdev = dev->dev_private;
418 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 431 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
419 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 432 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
420 433
@@ -427,15 +440,6 @@ void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable)
427 if (!enable && !dig->afmt->enabled) 440 if (!enable && !dig->afmt->enabled)
428 return; 441 return;
429 442
430 if (enable) {
431 if (ASIC_IS_DCE6(rdev))
432 dig->afmt->pin = dce6_audio_get_pin(rdev);
433 else
434 dig->afmt->pin = r600_audio_get_pin(rdev);
435 } else {
436 dig->afmt->pin = NULL;
437 }
438
439 dig->afmt->enabled = enable; 443 dig->afmt->enabled = enable;
440 444
441 DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n", 445 DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
diff --git a/drivers/gpu/drm/radeon/ni_dpm.c b/drivers/gpu/drm/radeon/ni_dpm.c
index 1217fbcbdcca..ca814276b075 100644
--- a/drivers/gpu/drm/radeon/ni_dpm.c
+++ b/drivers/gpu/drm/radeon/ni_dpm.c
@@ -2588,7 +2588,7 @@ static int ni_populate_sq_ramping_values(struct radeon_device *rdev,
2588 if (NISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT)) 2588 if (NISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2589 enable_sq_ramping = false; 2589 enable_sq_ramping = false;
2590 2590
2591 if (NISLANDS_DPM2_SQ_RAMP_LTI_RATIO <= (LTI_RATIO_MASK >> LTI_RATIO_SHIFT)) 2591 if (NISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2592 enable_sq_ramping = false; 2592 enable_sq_ramping = false;
2593 2593
2594 for (i = 0; i < state->performance_level_count; i++) { 2594 for (i = 0; i < state->performance_level_count; i++) {
diff --git a/drivers/gpu/drm/radeon/r600_audio.c b/drivers/gpu/drm/radeon/r600_audio.c
index 47fc2b886979..bffac10c4296 100644
--- a/drivers/gpu/drm/radeon/r600_audio.c
+++ b/drivers/gpu/drm/radeon/r600_audio.c
@@ -142,12 +142,15 @@ void r600_audio_update_hdmi(struct work_struct *work)
142} 142}
143 143
144/* enable the audio stream */ 144/* enable the audio stream */
145static void r600_audio_enable(struct radeon_device *rdev, 145void r600_audio_enable(struct radeon_device *rdev,
146 struct r600_audio_pin *pin, 146 struct r600_audio_pin *pin,
147 bool enable) 147 bool enable)
148{ 148{
149 u32 value = 0; 149 u32 value = 0;
150 150
151 if (!pin)
152 return;
153
151 if (ASIC_IS_DCE4(rdev)) { 154 if (ASIC_IS_DCE4(rdev)) {
152 if (enable) { 155 if (enable) {
153 value |= 0x81000000; /* Required to enable audio */ 156 value |= 0x81000000; /* Required to enable audio */
@@ -158,7 +161,6 @@ static void r600_audio_enable(struct radeon_device *rdev,
158 WREG32_P(R600_AUDIO_ENABLE, 161 WREG32_P(R600_AUDIO_ENABLE,
159 enable ? 0x81000000 : 0x0, ~0x81000000); 162 enable ? 0x81000000 : 0x0, ~0x81000000);
160 } 163 }
161 DRM_INFO("%s audio %d support\n", enable ? "Enabling" : "Disabling", pin->id);
162} 164}
163 165
164/* 166/*
@@ -178,8 +180,8 @@ int r600_audio_init(struct radeon_device *rdev)
178 rdev->audio.pin[0].status_bits = 0; 180 rdev->audio.pin[0].status_bits = 0;
179 rdev->audio.pin[0].category_code = 0; 181 rdev->audio.pin[0].category_code = 0;
180 rdev->audio.pin[0].id = 0; 182 rdev->audio.pin[0].id = 0;
181 183 /* disable audio. it will be set up later */
182 r600_audio_enable(rdev, &rdev->audio.pin[0], true); 184 r600_audio_enable(rdev, &rdev->audio.pin[0], false);
183 185
184 return 0; 186 return 0;
185} 187}
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c
index 3016fc14f502..85a2bb28aed2 100644
--- a/drivers/gpu/drm/radeon/r600_hdmi.c
+++ b/drivers/gpu/drm/radeon/r600_hdmi.c
@@ -329,9 +329,6 @@ static void dce3_2_afmt_write_speaker_allocation(struct drm_encoder *encoder)
329 u8 *sadb; 329 u8 *sadb;
330 int sad_count; 330 int sad_count;
331 331
332 /* XXX: setting this register causes hangs on some asics */
333 return;
334
335 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 332 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
336 if (connector->encoder == encoder) { 333 if (connector->encoder == encoder) {
337 radeon_connector = to_radeon_connector(connector); 334 radeon_connector = to_radeon_connector(connector);
@@ -460,6 +457,10 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod
460 return; 457 return;
461 offset = dig->afmt->offset; 458 offset = dig->afmt->offset;
462 459
460 /* disable audio prior to setting up hw */
461 dig->afmt->pin = r600_audio_get_pin(rdev);
462 r600_audio_enable(rdev, dig->afmt->pin, false);
463
463 r600_audio_set_dto(encoder, mode->clock); 464 r600_audio_set_dto(encoder, mode->clock);
464 465
465 WREG32(HDMI0_VBI_PACKET_CONTROL + offset, 466 WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
@@ -531,6 +532,9 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod
531 WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001); 532 WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001);
532 533
533 r600_hdmi_audio_workaround(encoder); 534 r600_hdmi_audio_workaround(encoder);
535
536 /* enable audio after to setting up hw */
537 r600_audio_enable(rdev, dig->afmt->pin, true);
534} 538}
535 539
536/* 540/*
@@ -651,11 +655,6 @@ void r600_hdmi_enable(struct drm_encoder *encoder, bool enable)
651 if (!enable && !dig->afmt->enabled) 655 if (!enable && !dig->afmt->enabled)
652 return; 656 return;
653 657
654 if (enable)
655 dig->afmt->pin = r600_audio_get_pin(rdev);
656 else
657 dig->afmt->pin = NULL;
658
659 /* Older chipsets require setting HDMI and routing manually */ 658 /* Older chipsets require setting HDMI and routing manually */
660 if (!ASIC_IS_DCE3(rdev)) { 659 if (!ASIC_IS_DCE3(rdev)) {
661 if (enable) 660 if (enable)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 4a8ac1cd6b4c..e887d027b6d0 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -135,6 +135,9 @@ extern int radeon_hard_reset;
135/* R600+ */ 135/* R600+ */
136#define R600_RING_TYPE_UVD_INDEX 5 136#define R600_RING_TYPE_UVD_INDEX 5
137 137
138/* number of hw syncs before falling back on blocking */
139#define RADEON_NUM_SYNCS 4
140
138/* hardcode those limit for now */ 141/* hardcode those limit for now */
139#define RADEON_VA_IB_OFFSET (1 << 20) 142#define RADEON_VA_IB_OFFSET (1 << 20)
140#define RADEON_VA_RESERVED_SIZE (8 << 20) 143#define RADEON_VA_RESERVED_SIZE (8 << 20)
@@ -554,7 +557,6 @@ int radeon_mode_dumb_mmap(struct drm_file *filp,
554/* 557/*
555 * Semaphores. 558 * Semaphores.
556 */ 559 */
557/* everything here is constant */
558struct radeon_semaphore { 560struct radeon_semaphore {
559 struct radeon_sa_bo *sa_bo; 561 struct radeon_sa_bo *sa_bo;
560 signed waiters; 562 signed waiters;
@@ -2745,6 +2747,12 @@ int radeon_vm_bo_rmv(struct radeon_device *rdev,
2745void r600_audio_update_hdmi(struct work_struct *work); 2747void r600_audio_update_hdmi(struct work_struct *work);
2746struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); 2748struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2747struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); 2749struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2750void r600_audio_enable(struct radeon_device *rdev,
2751 struct r600_audio_pin *pin,
2752 bool enable);
2753void dce6_audio_enable(struct radeon_device *rdev,
2754 struct r600_audio_pin *pin,
2755 bool enable);
2748 2756
2749/* 2757/*
2750 * R600 vram scratch functions 2758 * R600 vram scratch functions
diff --git a/drivers/gpu/drm/radeon/radeon_atpx_handler.c b/drivers/gpu/drm/radeon/radeon_atpx_handler.c
index 485848f889f5..fa9a9c02751e 100644
--- a/drivers/gpu/drm/radeon/radeon_atpx_handler.c
+++ b/drivers/gpu/drm/radeon/radeon_atpx_handler.c
@@ -219,7 +219,8 @@ static int radeon_atpx_verify_interface(struct radeon_atpx *atpx)
219 memcpy(&output, info->buffer.pointer, size); 219 memcpy(&output, info->buffer.pointer, size);
220 220
221 /* TODO: check version? */ 221 /* TODO: check version? */
222 printk("ATPX version %u\n", output.version); 222 printk("ATPX version %u, functions 0x%08x\n",
223 output.version, output.function_bits);
223 224
224 radeon_atpx_parse_functions(&atpx->functions, output.function_bits); 225 radeon_atpx_parse_functions(&atpx->functions, output.function_bits);
225 226
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index d680608f6f5b..fbd8b930f2be 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -571,6 +571,8 @@ static void radeon_crtc_init(struct drm_device *dev, int index)
571 radeon_crtc->max_cursor_width = CURSOR_WIDTH; 571 radeon_crtc->max_cursor_width = CURSOR_WIDTH;
572 radeon_crtc->max_cursor_height = CURSOR_HEIGHT; 572 radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
573 } 573 }
574 dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
575 dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
574 576
575#if 0 577#if 0
576 radeon_crtc->mode_set.crtc = &radeon_crtc->base; 578 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
index 114d1672d616..2aecd6dc2610 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -537,6 +537,10 @@ int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
537 537
538 radeon_vm_init(rdev, &fpriv->vm); 538 radeon_vm_init(rdev, &fpriv->vm);
539 539
540 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
541 if (r)
542 return r;
543
540 /* map the ib pool buffer read only into 544 /* map the ib pool buffer read only into
541 * virtual address space */ 545 * virtual address space */
542 bo_va = radeon_vm_bo_add(rdev, &fpriv->vm, 546 bo_va = radeon_vm_bo_add(rdev, &fpriv->vm,
@@ -544,6 +548,8 @@ int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
544 r = radeon_vm_bo_set_addr(rdev, bo_va, RADEON_VA_IB_OFFSET, 548 r = radeon_vm_bo_set_addr(rdev, bo_va, RADEON_VA_IB_OFFSET,
545 RADEON_VM_PAGE_READABLE | 549 RADEON_VM_PAGE_READABLE |
546 RADEON_VM_PAGE_SNOOPED); 550 RADEON_VM_PAGE_SNOOPED);
551
552 radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
547 if (r) { 553 if (r) {
548 radeon_vm_fini(rdev, &fpriv->vm); 554 radeon_vm_fini(rdev, &fpriv->vm);
549 kfree(fpriv); 555 kfree(fpriv);
diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c
index 1b783f0e6d3a..15e44a7281ab 100644
--- a/drivers/gpu/drm/radeon/radeon_ring.c
+++ b/drivers/gpu/drm/radeon/radeon_ring.c
@@ -139,7 +139,7 @@ int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
139 } 139 }
140 140
141 /* 64 dwords should be enough for fence too */ 141 /* 64 dwords should be enough for fence too */
142 r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_RINGS * 8); 142 r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_SYNCS * 8);
143 if (r) { 143 if (r) {
144 dev_err(rdev->dev, "scheduling IB failed (%d).\n", r); 144 dev_err(rdev->dev, "scheduling IB failed (%d).\n", r);
145 return r; 145 return r;
diff --git a/drivers/gpu/drm/radeon/radeon_semaphore.c b/drivers/gpu/drm/radeon/radeon_semaphore.c
index 2b42aa1914f2..9006b32d5eed 100644
--- a/drivers/gpu/drm/radeon/radeon_semaphore.c
+++ b/drivers/gpu/drm/radeon/radeon_semaphore.c
@@ -34,14 +34,15 @@
34int radeon_semaphore_create(struct radeon_device *rdev, 34int radeon_semaphore_create(struct radeon_device *rdev,
35 struct radeon_semaphore **semaphore) 35 struct radeon_semaphore **semaphore)
36{ 36{
37 uint32_t *cpu_addr;
37 int i, r; 38 int i, r;
38 39
39 *semaphore = kmalloc(sizeof(struct radeon_semaphore), GFP_KERNEL); 40 *semaphore = kmalloc(sizeof(struct radeon_semaphore), GFP_KERNEL);
40 if (*semaphore == NULL) { 41 if (*semaphore == NULL) {
41 return -ENOMEM; 42 return -ENOMEM;
42 } 43 }
43 r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, 44 r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, &(*semaphore)->sa_bo,
44 &(*semaphore)->sa_bo, 8, 8, true); 45 8 * RADEON_NUM_SYNCS, 8, true);
45 if (r) { 46 if (r) {
46 kfree(*semaphore); 47 kfree(*semaphore);
47 *semaphore = NULL; 48 *semaphore = NULL;
@@ -49,7 +50,10 @@ int radeon_semaphore_create(struct radeon_device *rdev,
49 } 50 }
50 (*semaphore)->waiters = 0; 51 (*semaphore)->waiters = 0;
51 (*semaphore)->gpu_addr = radeon_sa_bo_gpu_addr((*semaphore)->sa_bo); 52 (*semaphore)->gpu_addr = radeon_sa_bo_gpu_addr((*semaphore)->sa_bo);
52 *((uint64_t*)radeon_sa_bo_cpu_addr((*semaphore)->sa_bo)) = 0; 53
54 cpu_addr = radeon_sa_bo_cpu_addr((*semaphore)->sa_bo);
55 for (i = 0; i < RADEON_NUM_SYNCS; ++i)
56 cpu_addr[i] = 0;
53 57
54 for (i = 0; i < RADEON_NUM_RINGS; ++i) 58 for (i = 0; i < RADEON_NUM_RINGS; ++i)
55 (*semaphore)->sync_to[i] = NULL; 59 (*semaphore)->sync_to[i] = NULL;
@@ -125,6 +129,7 @@ int radeon_semaphore_sync_rings(struct radeon_device *rdev,
125 struct radeon_semaphore *semaphore, 129 struct radeon_semaphore *semaphore,
126 int ring) 130 int ring)
127{ 131{
132 unsigned count = 0;
128 int i, r; 133 int i, r;
129 134
130 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 135 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
@@ -140,6 +145,12 @@ int radeon_semaphore_sync_rings(struct radeon_device *rdev,
140 return -EINVAL; 145 return -EINVAL;
141 } 146 }
142 147
148 if (++count > RADEON_NUM_SYNCS) {
149 /* not enough room, wait manually */
150 radeon_fence_wait_locked(fence);
151 continue;
152 }
153
143 /* allocate enough space for sync command */ 154 /* allocate enough space for sync command */
144 r = radeon_ring_alloc(rdev, &rdev->ring[i], 16); 155 r = radeon_ring_alloc(rdev, &rdev->ring[i], 16);
145 if (r) { 156 if (r) {
@@ -164,6 +175,8 @@ int radeon_semaphore_sync_rings(struct radeon_device *rdev,
164 175
165 radeon_ring_commit(rdev, &rdev->ring[i]); 176 radeon_ring_commit(rdev, &rdev->ring[i]);
166 radeon_fence_note_sync(fence, ring); 177 radeon_fence_note_sync(fence, ring);
178
179 semaphore->gpu_addr += 8;
167 } 180 }
168 181
169 return 0; 182 return 0;
diff --git a/drivers/gpu/drm/radeon/radeon_uvd.c b/drivers/gpu/drm/radeon/radeon_uvd.c
index 6781fee1eaad..3e6804b2b2ef 100644
--- a/drivers/gpu/drm/radeon/radeon_uvd.c
+++ b/drivers/gpu/drm/radeon/radeon_uvd.c
@@ -171,6 +171,8 @@ void radeon_uvd_fini(struct radeon_device *rdev)
171 171
172 radeon_bo_unref(&rdev->uvd.vcpu_bo); 172 radeon_bo_unref(&rdev->uvd.vcpu_bo);
173 173
174 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX]);
175
174 release_firmware(rdev->uvd_fw); 176 release_firmware(rdev->uvd_fw);
175} 177}
176 178
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 6c772e58c784..4e37a42305d8 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -1955,9 +1955,9 @@ void rv770_fini(struct radeon_device *rdev)
1955 radeon_wb_fini(rdev); 1955 radeon_wb_fini(rdev);
1956 radeon_ib_pool_fini(rdev); 1956 radeon_ib_pool_fini(rdev);
1957 radeon_irq_kms_fini(rdev); 1957 radeon_irq_kms_fini(rdev);
1958 rv770_pcie_gart_fini(rdev);
1959 uvd_v1_0_fini(rdev); 1958 uvd_v1_0_fini(rdev);
1960 radeon_uvd_fini(rdev); 1959 radeon_uvd_fini(rdev);
1960 rv770_pcie_gart_fini(rdev);
1961 r600_vram_scratch_fini(rdev); 1961 r600_vram_scratch_fini(rdev);
1962 radeon_gem_fini(rdev); 1962 radeon_gem_fini(rdev);
1963 radeon_fence_driver_fini(rdev); 1963 radeon_fence_driver_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/rv770_dpm.c b/drivers/gpu/drm/radeon/rv770_dpm.c
index 5b2ea8ac0731..b5f63f5e22a3 100644
--- a/drivers/gpu/drm/radeon/rv770_dpm.c
+++ b/drivers/gpu/drm/radeon/rv770_dpm.c
@@ -2526,14 +2526,7 @@ u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low)
2526bool rv770_dpm_vblank_too_short(struct radeon_device *rdev) 2526bool rv770_dpm_vblank_too_short(struct radeon_device *rdev)
2527{ 2527{
2528 u32 vblank_time = r600_dpm_get_vblank_time(rdev); 2528 u32 vblank_time = r600_dpm_get_vblank_time(rdev);
2529 u32 switch_limit = 300; 2529 u32 switch_limit = 200; /* 300 */
2530
2531 /* quirks */
2532 /* ASUS K70AF */
2533 if ((rdev->pdev->device == 0x9553) &&
2534 (rdev->pdev->subsystem_vendor == 0x1043) &&
2535 (rdev->pdev->subsystem_device == 0x1c42))
2536 switch_limit = 200;
2537 2530
2538 /* RV770 */ 2531 /* RV770 */
2539 /* mclk switching doesn't seem to work reliably on desktop RV770s */ 2532 /* mclk switching doesn't seem to work reliably on desktop RV770s */
diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c
index eafb0e6bc67e..0a2f5b4bca43 100644
--- a/drivers/gpu/drm/radeon/si_dpm.c
+++ b/drivers/gpu/drm/radeon/si_dpm.c
@@ -2395,7 +2395,7 @@ static int si_populate_sq_ramping_values(struct radeon_device *rdev,
2395 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT)) 2395 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2396 enable_sq_ramping = false; 2396 enable_sq_ramping = false;
2397 2397
2398 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO <= (LTI_RATIO_MASK >> LTI_RATIO_SHIFT)) 2398 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2399 enable_sq_ramping = false; 2399 enable_sq_ramping = false;
2400 2400
2401 for (i = 0; i < state->performance_level_count; i++) { 2401 for (i = 0; i < state->performance_level_count; i++) {
diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
index 88a529008ce0..c71594754f46 100644
--- a/drivers/gpu/drm/tegra/drm.c
+++ b/drivers/gpu/drm/tegra/drm.c
@@ -104,7 +104,7 @@ static void tegra_drm_context_free(struct tegra_drm_context *context)
104 104
105static void tegra_drm_lastclose(struct drm_device *drm) 105static void tegra_drm_lastclose(struct drm_device *drm)
106{ 106{
107#ifdef CONFIG_TEGRA_DRM_FBDEV 107#ifdef CONFIG_DRM_TEGRA_FBDEV
108 struct tegra_drm *tegra = drm->dev_private; 108 struct tegra_drm *tegra = drm->dev_private;
109 109
110 tegra_fbdev_restore_mode(tegra->fbdev); 110 tegra_fbdev_restore_mode(tegra->fbdev);
diff --git a/drivers/gpu/drm/tegra/rgb.c b/drivers/gpu/drm/tegra/rgb.c
index 338f7f6561d7..0266fb40479e 100644
--- a/drivers/gpu/drm/tegra/rgb.c
+++ b/drivers/gpu/drm/tegra/rgb.c
@@ -15,6 +15,7 @@
15struct tegra_rgb { 15struct tegra_rgb {
16 struct tegra_output output; 16 struct tegra_output output;
17 struct tegra_dc *dc; 17 struct tegra_dc *dc;
18 bool enabled;
18 19
19 struct clk *clk_parent; 20 struct clk *clk_parent;
20 struct clk *clk; 21 struct clk *clk;
@@ -89,6 +90,9 @@ static int tegra_output_rgb_enable(struct tegra_output *output)
89 struct tegra_rgb *rgb = to_rgb(output); 90 struct tegra_rgb *rgb = to_rgb(output);
90 unsigned long value; 91 unsigned long value;
91 92
93 if (rgb->enabled)
94 return 0;
95
92 tegra_dc_write_regs(rgb->dc, rgb_enable, ARRAY_SIZE(rgb_enable)); 96 tegra_dc_write_regs(rgb->dc, rgb_enable, ARRAY_SIZE(rgb_enable));
93 97
94 value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL; 98 value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL;
@@ -122,6 +126,8 @@ static int tegra_output_rgb_enable(struct tegra_output *output)
122 tegra_dc_writel(rgb->dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); 126 tegra_dc_writel(rgb->dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
123 tegra_dc_writel(rgb->dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); 127 tegra_dc_writel(rgb->dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
124 128
129 rgb->enabled = true;
130
125 return 0; 131 return 0;
126} 132}
127 133
@@ -130,6 +136,9 @@ static int tegra_output_rgb_disable(struct tegra_output *output)
130 struct tegra_rgb *rgb = to_rgb(output); 136 struct tegra_rgb *rgb = to_rgb(output);
131 unsigned long value; 137 unsigned long value;
132 138
139 if (!rgb->enabled)
140 return 0;
141
133 value = tegra_dc_readl(rgb->dc, DC_CMD_DISPLAY_POWER_CONTROL); 142 value = tegra_dc_readl(rgb->dc, DC_CMD_DISPLAY_POWER_CONTROL);
134 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | 143 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
135 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE); 144 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
@@ -144,6 +153,8 @@ static int tegra_output_rgb_disable(struct tegra_output *output)
144 153
145 tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable)); 154 tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable));
146 155
156 rgb->enabled = false;
157
147 return 0; 158 return 0;
148} 159}
149 160
diff --git a/drivers/gpu/drm/ttm/ttm_agp_backend.c b/drivers/gpu/drm/ttm/ttm_agp_backend.c
index 3302f99e7497..764be36397fd 100644
--- a/drivers/gpu/drm/ttm/ttm_agp_backend.c
+++ b/drivers/gpu/drm/ttm/ttm_agp_backend.c
@@ -126,6 +126,7 @@ struct ttm_tt *ttm_agp_tt_create(struct ttm_bo_device *bdev,
126 agp_be->ttm.func = &ttm_agp_func; 126 agp_be->ttm.func = &ttm_agp_func;
127 127
128 if (ttm_tt_init(&agp_be->ttm, bdev, size, page_flags, dummy_read_page)) { 128 if (ttm_tt_init(&agp_be->ttm, bdev, size, page_flags, dummy_read_page)) {
129 kfree(agp_be);
129 return NULL; 130 return NULL;
130 } 131 }
131 132
diff --git a/drivers/gpu/drm/vmwgfx/svga3d_reg.h b/drivers/gpu/drm/vmwgfx/svga3d_reg.h
index b645647b7776..f58dc7dd15c5 100644
--- a/drivers/gpu/drm/vmwgfx/svga3d_reg.h
+++ b/drivers/gpu/drm/vmwgfx/svga3d_reg.h
@@ -261,12 +261,7 @@ typedef enum SVGA3dSurfaceFormat {
261 /* Planar video formats. */ 261 /* Planar video formats. */
262 SVGA3D_YV12 = 121, 262 SVGA3D_YV12 = 121,
263 263
264 /* Shader constant formats. */ 264 SVGA3D_FORMAT_MAX = 122,
265 SVGA3D_SURFACE_SHADERCONST_FLOAT = 122,
266 SVGA3D_SURFACE_SHADERCONST_INT = 123,
267 SVGA3D_SURFACE_SHADERCONST_BOOL = 124,
268
269 SVGA3D_FORMAT_MAX = 125,
270} SVGA3dSurfaceFormat; 265} SVGA3dSurfaceFormat;
271 266
272typedef uint32 SVGA3dColor; /* a, r, g, b */ 267typedef uint32 SVGA3dColor; /* a, r, g, b */
@@ -1223,9 +1218,19 @@ typedef enum {
1223#define SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL 1129 1218#define SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL 1129
1224 1219
1225#define SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE 1130 1220#define SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE 1130
1226 1221#define SVGA_3D_CMD_GB_SCREEN_DMA 1131
1222#define SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH 1132
1223#define SVGA_3D_CMD_GB_MOB_FENCE 1133
1224#define SVGA_3D_CMD_DEFINE_GB_SURFACE_V2 1134
1227#define SVGA_3D_CMD_DEFINE_GB_MOB64 1135 1225#define SVGA_3D_CMD_DEFINE_GB_MOB64 1135
1228#define SVGA_3D_CMD_REDEFINE_GB_MOB64 1136 1226#define SVGA_3D_CMD_REDEFINE_GB_MOB64 1136
1227#define SVGA_3D_CMD_NOP_ERROR 1137
1228
1229#define SVGA_3D_CMD_RESERVED1 1138
1230#define SVGA_3D_CMD_RESERVED2 1139
1231#define SVGA_3D_CMD_RESERVED3 1140
1232#define SVGA_3D_CMD_RESERVED4 1141
1233#define SVGA_3D_CMD_RESERVED5 1142
1229 1234
1230#define SVGA_3D_CMD_MAX 1142 1235#define SVGA_3D_CMD_MAX 1142
1231#define SVGA_3D_CMD_FUTURE_MAX 3000 1236#define SVGA_3D_CMD_FUTURE_MAX 3000
@@ -1973,8 +1978,7 @@ struct {
1973 uint32 sizeInBytes; 1978 uint32 sizeInBytes;
1974 uint32 validSizeInBytes; 1979 uint32 validSizeInBytes;
1975 SVGAMobFormat ptDepth; 1980 SVGAMobFormat ptDepth;
1976} 1981} __packed
1977__attribute__((__packed__))
1978SVGA3dCmdSetOTableBase; /* SVGA_3D_CMD_SET_OTABLE_BASE */ 1982SVGA3dCmdSetOTableBase; /* SVGA_3D_CMD_SET_OTABLE_BASE */
1979 1983
1980typedef 1984typedef
@@ -1984,15 +1988,13 @@ struct {
1984 uint32 sizeInBytes; 1988 uint32 sizeInBytes;
1985 uint32 validSizeInBytes; 1989 uint32 validSizeInBytes;
1986 SVGAMobFormat ptDepth; 1990 SVGAMobFormat ptDepth;
1987} 1991} __packed
1988__attribute__((__packed__))
1989SVGA3dCmdSetOTableBase64; /* SVGA_3D_CMD_SET_OTABLE_BASE64 */ 1992SVGA3dCmdSetOTableBase64; /* SVGA_3D_CMD_SET_OTABLE_BASE64 */
1990 1993
1991typedef 1994typedef
1992struct { 1995struct {
1993 SVGAOTableType type; 1996 SVGAOTableType type;
1994} 1997} __packed
1995__attribute__((__packed__))
1996SVGA3dCmdReadbackOTable; /* SVGA_3D_CMD_READBACK_OTABLE */ 1998SVGA3dCmdReadbackOTable; /* SVGA_3D_CMD_READBACK_OTABLE */
1997 1999
1998/* 2000/*
@@ -2005,8 +2007,7 @@ struct SVGA3dCmdDefineGBMob {
2005 SVGAMobFormat ptDepth; 2007 SVGAMobFormat ptDepth;
2006 PPN base; 2008 PPN base;
2007 uint32 sizeInBytes; 2009 uint32 sizeInBytes;
2008} 2010} __packed
2009__attribute__((__packed__))
2010SVGA3dCmdDefineGBMob; /* SVGA_3D_CMD_DEFINE_GB_MOB */ 2011SVGA3dCmdDefineGBMob; /* SVGA_3D_CMD_DEFINE_GB_MOB */
2011 2012
2012 2013
@@ -2017,8 +2018,7 @@ SVGA3dCmdDefineGBMob; /* SVGA_3D_CMD_DEFINE_GB_MOB */
2017typedef 2018typedef
2018struct SVGA3dCmdDestroyGBMob { 2019struct SVGA3dCmdDestroyGBMob {
2019 SVGAMobId mobid; 2020 SVGAMobId mobid;
2020} 2021} __packed
2021__attribute__((__packed__))
2022SVGA3dCmdDestroyGBMob; /* SVGA_3D_CMD_DESTROY_GB_MOB */ 2022SVGA3dCmdDestroyGBMob; /* SVGA_3D_CMD_DESTROY_GB_MOB */
2023 2023
2024/* 2024/*
@@ -2031,8 +2031,7 @@ struct SVGA3dCmdRedefineGBMob {
2031 SVGAMobFormat ptDepth; 2031 SVGAMobFormat ptDepth;
2032 PPN base; 2032 PPN base;
2033 uint32 sizeInBytes; 2033 uint32 sizeInBytes;
2034} 2034} __packed
2035__attribute__((__packed__))
2036SVGA3dCmdRedefineGBMob; /* SVGA_3D_CMD_REDEFINE_GB_MOB */ 2035SVGA3dCmdRedefineGBMob; /* SVGA_3D_CMD_REDEFINE_GB_MOB */
2037 2036
2038/* 2037/*
@@ -2045,8 +2044,7 @@ struct SVGA3dCmdDefineGBMob64 {
2045 SVGAMobFormat ptDepth; 2044 SVGAMobFormat ptDepth;
2046 PPN64 base; 2045 PPN64 base;
2047 uint32 sizeInBytes; 2046 uint32 sizeInBytes;
2048} 2047} __packed
2049__attribute__((__packed__))
2050SVGA3dCmdDefineGBMob64; /* SVGA_3D_CMD_DEFINE_GB_MOB64 */ 2048SVGA3dCmdDefineGBMob64; /* SVGA_3D_CMD_DEFINE_GB_MOB64 */
2051 2049
2052/* 2050/*
@@ -2059,8 +2057,7 @@ struct SVGA3dCmdRedefineGBMob64 {
2059 SVGAMobFormat ptDepth; 2057 SVGAMobFormat ptDepth;
2060 PPN64 base; 2058 PPN64 base;
2061 uint32 sizeInBytes; 2059 uint32 sizeInBytes;
2062} 2060} __packed
2063__attribute__((__packed__))
2064SVGA3dCmdRedefineGBMob64; /* SVGA_3D_CMD_REDEFINE_GB_MOB64 */ 2061SVGA3dCmdRedefineGBMob64; /* SVGA_3D_CMD_REDEFINE_GB_MOB64 */
2065 2062
2066/* 2063/*
@@ -2070,8 +2067,7 @@ SVGA3dCmdRedefineGBMob64; /* SVGA_3D_CMD_REDEFINE_GB_MOB64 */
2070typedef 2067typedef
2071struct SVGA3dCmdUpdateGBMobMapping { 2068struct SVGA3dCmdUpdateGBMobMapping {
2072 SVGAMobId mobid; 2069 SVGAMobId mobid;
2073} 2070} __packed
2074__attribute__((__packed__))
2075SVGA3dCmdUpdateGBMobMapping; /* SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING */ 2071SVGA3dCmdUpdateGBMobMapping; /* SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING */
2076 2072
2077/* 2073/*
@@ -2087,7 +2083,8 @@ struct SVGA3dCmdDefineGBSurface {
2087 uint32 multisampleCount; 2083 uint32 multisampleCount;
2088 SVGA3dTextureFilter autogenFilter; 2084 SVGA3dTextureFilter autogenFilter;
2089 SVGA3dSize size; 2085 SVGA3dSize size;
2090} SVGA3dCmdDefineGBSurface; /* SVGA_3D_CMD_DEFINE_GB_SURFACE */ 2086} __packed
2087SVGA3dCmdDefineGBSurface; /* SVGA_3D_CMD_DEFINE_GB_SURFACE */
2091 2088
2092/* 2089/*
2093 * Destroy a guest-backed surface. 2090 * Destroy a guest-backed surface.
@@ -2096,7 +2093,8 @@ struct SVGA3dCmdDefineGBSurface {
2096typedef 2093typedef
2097struct SVGA3dCmdDestroyGBSurface { 2094struct SVGA3dCmdDestroyGBSurface {
2098 uint32 sid; 2095 uint32 sid;
2099} SVGA3dCmdDestroyGBSurface; /* SVGA_3D_CMD_DESTROY_GB_SURFACE */ 2096} __packed
2097SVGA3dCmdDestroyGBSurface; /* SVGA_3D_CMD_DESTROY_GB_SURFACE */
2100 2098
2101/* 2099/*
2102 * Bind a guest-backed surface to an object. 2100 * Bind a guest-backed surface to an object.
@@ -2106,7 +2104,8 @@ typedef
2106struct SVGA3dCmdBindGBSurface { 2104struct SVGA3dCmdBindGBSurface {
2107 uint32 sid; 2105 uint32 sid;
2108 SVGAMobId mobid; 2106 SVGAMobId mobid;
2109} SVGA3dCmdBindGBSurface; /* SVGA_3D_CMD_BIND_GB_SURFACE */ 2107} __packed
2108SVGA3dCmdBindGBSurface; /* SVGA_3D_CMD_BIND_GB_SURFACE */
2110 2109
2111/* 2110/*
2112 * Conditionally bind a mob to a guest backed surface if testMobid 2111 * Conditionally bind a mob to a guest backed surface if testMobid
@@ -2123,7 +2122,7 @@ struct{
2123 SVGAMobId testMobid; 2122 SVGAMobId testMobid;
2124 SVGAMobId mobid; 2123 SVGAMobId mobid;
2125 uint32 flags; 2124 uint32 flags;
2126} 2125} __packed
2127SVGA3dCmdCondBindGBSurface; /* SVGA_3D_CMD_COND_BIND_GB_SURFACE */ 2126SVGA3dCmdCondBindGBSurface; /* SVGA_3D_CMD_COND_BIND_GB_SURFACE */
2128 2127
2129/* 2128/*
@@ -2135,7 +2134,8 @@ typedef
2135struct SVGA3dCmdUpdateGBImage { 2134struct SVGA3dCmdUpdateGBImage {
2136 SVGA3dSurfaceImageId image; 2135 SVGA3dSurfaceImageId image;
2137 SVGA3dBox box; 2136 SVGA3dBox box;
2138} SVGA3dCmdUpdateGBImage; /* SVGA_3D_CMD_UPDATE_GB_IMAGE */ 2137} __packed
2138SVGA3dCmdUpdateGBImage; /* SVGA_3D_CMD_UPDATE_GB_IMAGE */
2139 2139
2140/* 2140/*
2141 * Update an entire guest-backed surface. 2141 * Update an entire guest-backed surface.
@@ -2145,7 +2145,8 @@ struct SVGA3dCmdUpdateGBImage {
2145typedef 2145typedef
2146struct SVGA3dCmdUpdateGBSurface { 2146struct SVGA3dCmdUpdateGBSurface {
2147 uint32 sid; 2147 uint32 sid;
2148} SVGA3dCmdUpdateGBSurface; /* SVGA_3D_CMD_UPDATE_GB_SURFACE */ 2148} __packed
2149SVGA3dCmdUpdateGBSurface; /* SVGA_3D_CMD_UPDATE_GB_SURFACE */
2149 2150
2150/* 2151/*
2151 * Readback an image in a guest-backed surface. 2152 * Readback an image in a guest-backed surface.
@@ -2155,7 +2156,8 @@ struct SVGA3dCmdUpdateGBSurface {
2155typedef 2156typedef
2156struct SVGA3dCmdReadbackGBImage { 2157struct SVGA3dCmdReadbackGBImage {
2157 SVGA3dSurfaceImageId image; 2158 SVGA3dSurfaceImageId image;
2158} SVGA3dCmdReadbackGBImage; /* SVGA_3D_CMD_READBACK_GB_IMAGE*/ 2159} __packed
2160SVGA3dCmdReadbackGBImage; /* SVGA_3D_CMD_READBACK_GB_IMAGE*/
2159 2161
2160/* 2162/*
2161 * Readback an entire guest-backed surface. 2163 * Readback an entire guest-backed surface.
@@ -2165,7 +2167,8 @@ struct SVGA3dCmdReadbackGBImage {
2165typedef 2167typedef
2166struct SVGA3dCmdReadbackGBSurface { 2168struct SVGA3dCmdReadbackGBSurface {
2167 uint32 sid; 2169 uint32 sid;
2168} SVGA3dCmdReadbackGBSurface; /* SVGA_3D_CMD_READBACK_GB_SURFACE */ 2170} __packed
2171SVGA3dCmdReadbackGBSurface; /* SVGA_3D_CMD_READBACK_GB_SURFACE */
2169 2172
2170/* 2173/*
2171 * Readback a sub rect of an image in a guest-backed surface. After 2174 * Readback a sub rect of an image in a guest-backed surface. After
@@ -2179,7 +2182,7 @@ struct SVGA3dCmdReadbackGBImagePartial {
2179 SVGA3dSurfaceImageId image; 2182 SVGA3dSurfaceImageId image;
2180 SVGA3dBox box; 2183 SVGA3dBox box;
2181 uint32 invertBox; 2184 uint32 invertBox;
2182} 2185} __packed
2183SVGA3dCmdReadbackGBImagePartial; /* SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL */ 2186SVGA3dCmdReadbackGBImagePartial; /* SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL */
2184 2187
2185/* 2188/*
@@ -2190,7 +2193,8 @@ SVGA3dCmdReadbackGBImagePartial; /* SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL */
2190typedef 2193typedef
2191struct SVGA3dCmdInvalidateGBImage { 2194struct SVGA3dCmdInvalidateGBImage {
2192 SVGA3dSurfaceImageId image; 2195 SVGA3dSurfaceImageId image;
2193} SVGA3dCmdInvalidateGBImage; /* SVGA_3D_CMD_INVALIDATE_GB_IMAGE */ 2196} __packed
2197SVGA3dCmdInvalidateGBImage; /* SVGA_3D_CMD_INVALIDATE_GB_IMAGE */
2194 2198
2195/* 2199/*
2196 * Invalidate an entire guest-backed surface. 2200 * Invalidate an entire guest-backed surface.
@@ -2200,7 +2204,8 @@ struct SVGA3dCmdInvalidateGBImage {
2200typedef 2204typedef
2201struct SVGA3dCmdInvalidateGBSurface { 2205struct SVGA3dCmdInvalidateGBSurface {
2202 uint32 sid; 2206 uint32 sid;
2203} SVGA3dCmdInvalidateGBSurface; /* SVGA_3D_CMD_INVALIDATE_GB_SURFACE */ 2207} __packed
2208SVGA3dCmdInvalidateGBSurface; /* SVGA_3D_CMD_INVALIDATE_GB_SURFACE */
2204 2209
2205/* 2210/*
2206 * Invalidate a sub rect of an image in a guest-backed surface. After 2211 * Invalidate a sub rect of an image in a guest-backed surface. After
@@ -2214,7 +2219,7 @@ struct SVGA3dCmdInvalidateGBImagePartial {
2214 SVGA3dSurfaceImageId image; 2219 SVGA3dSurfaceImageId image;
2215 SVGA3dBox box; 2220 SVGA3dBox box;
2216 uint32 invertBox; 2221 uint32 invertBox;
2217} 2222} __packed
2218SVGA3dCmdInvalidateGBImagePartial; /* SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL */ 2223SVGA3dCmdInvalidateGBImagePartial; /* SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL */
2219 2224
2220/* 2225/*
@@ -2224,7 +2229,8 @@ SVGA3dCmdInvalidateGBImagePartial; /* SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL */
2224typedef 2229typedef
2225struct SVGA3dCmdDefineGBContext { 2230struct SVGA3dCmdDefineGBContext {
2226 uint32 cid; 2231 uint32 cid;
2227} SVGA3dCmdDefineGBContext; /* SVGA_3D_CMD_DEFINE_GB_CONTEXT */ 2232} __packed
2233SVGA3dCmdDefineGBContext; /* SVGA_3D_CMD_DEFINE_GB_CONTEXT */
2228 2234
2229/* 2235/*
2230 * Destroy a guest-backed context. 2236 * Destroy a guest-backed context.
@@ -2233,7 +2239,8 @@ struct SVGA3dCmdDefineGBContext {
2233typedef 2239typedef
2234struct SVGA3dCmdDestroyGBContext { 2240struct SVGA3dCmdDestroyGBContext {
2235 uint32 cid; 2241 uint32 cid;
2236} SVGA3dCmdDestroyGBContext; /* SVGA_3D_CMD_DESTROY_GB_CONTEXT */ 2242} __packed
2243SVGA3dCmdDestroyGBContext; /* SVGA_3D_CMD_DESTROY_GB_CONTEXT */
2237 2244
2238/* 2245/*
2239 * Bind a guest-backed context. 2246 * Bind a guest-backed context.
@@ -2252,7 +2259,8 @@ struct SVGA3dCmdBindGBContext {
2252 uint32 cid; 2259 uint32 cid;
2253 SVGAMobId mobid; 2260 SVGAMobId mobid;
2254 uint32 validContents; 2261 uint32 validContents;
2255} SVGA3dCmdBindGBContext; /* SVGA_3D_CMD_BIND_GB_CONTEXT */ 2262} __packed
2263SVGA3dCmdBindGBContext; /* SVGA_3D_CMD_BIND_GB_CONTEXT */
2256 2264
2257/* 2265/*
2258 * Readback a guest-backed context. 2266 * Readback a guest-backed context.
@@ -2262,7 +2270,8 @@ struct SVGA3dCmdBindGBContext {
2262typedef 2270typedef
2263struct SVGA3dCmdReadbackGBContext { 2271struct SVGA3dCmdReadbackGBContext {
2264 uint32 cid; 2272 uint32 cid;
2265} SVGA3dCmdReadbackGBContext; /* SVGA_3D_CMD_READBACK_GB_CONTEXT */ 2273} __packed
2274SVGA3dCmdReadbackGBContext; /* SVGA_3D_CMD_READBACK_GB_CONTEXT */
2266 2275
2267/* 2276/*
2268 * Invalidate a guest-backed context. 2277 * Invalidate a guest-backed context.
@@ -2270,7 +2279,8 @@ struct SVGA3dCmdReadbackGBContext {
2270typedef 2279typedef
2271struct SVGA3dCmdInvalidateGBContext { 2280struct SVGA3dCmdInvalidateGBContext {
2272 uint32 cid; 2281 uint32 cid;
2273} SVGA3dCmdInvalidateGBContext; /* SVGA_3D_CMD_INVALIDATE_GB_CONTEXT */ 2282} __packed
2283SVGA3dCmdInvalidateGBContext; /* SVGA_3D_CMD_INVALIDATE_GB_CONTEXT */
2274 2284
2275/* 2285/*
2276 * Define a guest-backed shader. 2286 * Define a guest-backed shader.
@@ -2281,7 +2291,8 @@ struct SVGA3dCmdDefineGBShader {
2281 uint32 shid; 2291 uint32 shid;
2282 SVGA3dShaderType type; 2292 SVGA3dShaderType type;
2283 uint32 sizeInBytes; 2293 uint32 sizeInBytes;
2284} SVGA3dCmdDefineGBShader; /* SVGA_3D_CMD_DEFINE_GB_SHADER */ 2294} __packed
2295SVGA3dCmdDefineGBShader; /* SVGA_3D_CMD_DEFINE_GB_SHADER */
2285 2296
2286/* 2297/*
2287 * Bind a guest-backed shader. 2298 * Bind a guest-backed shader.
@@ -2291,7 +2302,8 @@ typedef struct SVGA3dCmdBindGBShader {
2291 uint32 shid; 2302 uint32 shid;
2292 SVGAMobId mobid; 2303 SVGAMobId mobid;
2293 uint32 offsetInBytes; 2304 uint32 offsetInBytes;
2294} SVGA3dCmdBindGBShader; /* SVGA_3D_CMD_BIND_GB_SHADER */ 2305} __packed
2306SVGA3dCmdBindGBShader; /* SVGA_3D_CMD_BIND_GB_SHADER */
2295 2307
2296/* 2308/*
2297 * Destroy a guest-backed shader. 2309 * Destroy a guest-backed shader.
@@ -2299,7 +2311,8 @@ typedef struct SVGA3dCmdBindGBShader {
2299 2311
2300typedef struct SVGA3dCmdDestroyGBShader { 2312typedef struct SVGA3dCmdDestroyGBShader {
2301 uint32 shid; 2313 uint32 shid;
2302} SVGA3dCmdDestroyGBShader; /* SVGA_3D_CMD_DESTROY_GB_SHADER */ 2314} __packed
2315SVGA3dCmdDestroyGBShader; /* SVGA_3D_CMD_DESTROY_GB_SHADER */
2303 2316
2304typedef 2317typedef
2305struct { 2318struct {
@@ -2314,14 +2327,16 @@ struct {
2314 * Note that FLOAT and INT constants are 4-dwords in length, while 2327 * Note that FLOAT and INT constants are 4-dwords in length, while
2315 * BOOL constants are 1-dword in length. 2328 * BOOL constants are 1-dword in length.
2316 */ 2329 */
2317} SVGA3dCmdSetGBShaderConstInline; 2330} __packed
2331SVGA3dCmdSetGBShaderConstInline;
2318/* SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE */ 2332/* SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE */
2319 2333
2320typedef 2334typedef
2321struct { 2335struct {
2322 uint32 cid; 2336 uint32 cid;
2323 SVGA3dQueryType type; 2337 SVGA3dQueryType type;
2324} SVGA3dCmdBeginGBQuery; /* SVGA_3D_CMD_BEGIN_GB_QUERY */ 2338} __packed
2339SVGA3dCmdBeginGBQuery; /* SVGA_3D_CMD_BEGIN_GB_QUERY */
2325 2340
2326typedef 2341typedef
2327struct { 2342struct {
@@ -2329,7 +2344,8 @@ struct {
2329 SVGA3dQueryType type; 2344 SVGA3dQueryType type;
2330 SVGAMobId mobid; 2345 SVGAMobId mobid;
2331 uint32 offset; 2346 uint32 offset;
2332} SVGA3dCmdEndGBQuery; /* SVGA_3D_CMD_END_GB_QUERY */ 2347} __packed
2348SVGA3dCmdEndGBQuery; /* SVGA_3D_CMD_END_GB_QUERY */
2333 2349
2334 2350
2335/* 2351/*
@@ -2346,21 +2362,22 @@ struct {
2346 SVGA3dQueryType type; 2362 SVGA3dQueryType type;
2347 SVGAMobId mobid; 2363 SVGAMobId mobid;
2348 uint32 offset; 2364 uint32 offset;
2349} SVGA3dCmdWaitForGBQuery; /* SVGA_3D_CMD_WAIT_FOR_GB_QUERY */ 2365} __packed
2366SVGA3dCmdWaitForGBQuery; /* SVGA_3D_CMD_WAIT_FOR_GB_QUERY */
2350 2367
2351typedef 2368typedef
2352struct { 2369struct {
2353 SVGAMobId mobid; 2370 SVGAMobId mobid;
2354 uint32 fbOffset; 2371 uint32 fbOffset;
2355 uint32 initalized; 2372 uint32 initalized;
2356} 2373} __packed
2357SVGA3dCmdEnableGart; /* SVGA_3D_CMD_ENABLE_GART */ 2374SVGA3dCmdEnableGart; /* SVGA_3D_CMD_ENABLE_GART */
2358 2375
2359typedef 2376typedef
2360struct { 2377struct {
2361 SVGAMobId mobid; 2378 SVGAMobId mobid;
2362 uint32 gartOffset; 2379 uint32 gartOffset;
2363} 2380} __packed
2364SVGA3dCmdMapMobIntoGart; /* SVGA_3D_CMD_MAP_MOB_INTO_GART */ 2381SVGA3dCmdMapMobIntoGart; /* SVGA_3D_CMD_MAP_MOB_INTO_GART */
2365 2382
2366 2383
@@ -2368,7 +2385,7 @@ typedef
2368struct { 2385struct {
2369 uint32 gartOffset; 2386 uint32 gartOffset;
2370 uint32 numPages; 2387 uint32 numPages;
2371} 2388} __packed
2372SVGA3dCmdUnmapGartRange; /* SVGA_3D_CMD_UNMAP_GART_RANGE */ 2389SVGA3dCmdUnmapGartRange; /* SVGA_3D_CMD_UNMAP_GART_RANGE */
2373 2390
2374 2391
@@ -2385,27 +2402,27 @@ struct {
2385 int32 xRoot; 2402 int32 xRoot;
2386 int32 yRoot; 2403 int32 yRoot;
2387 uint32 flags; 2404 uint32 flags;
2388} 2405} __packed
2389SVGA3dCmdDefineGBScreenTarget; /* SVGA_3D_CMD_DEFINE_GB_SCREENTARGET */ 2406SVGA3dCmdDefineGBScreenTarget; /* SVGA_3D_CMD_DEFINE_GB_SCREENTARGET */
2390 2407
2391typedef 2408typedef
2392struct { 2409struct {
2393 uint32 stid; 2410 uint32 stid;
2394} 2411} __packed
2395SVGA3dCmdDestroyGBScreenTarget; /* SVGA_3D_CMD_DESTROY_GB_SCREENTARGET */ 2412SVGA3dCmdDestroyGBScreenTarget; /* SVGA_3D_CMD_DESTROY_GB_SCREENTARGET */
2396 2413
2397typedef 2414typedef
2398struct { 2415struct {
2399 uint32 stid; 2416 uint32 stid;
2400 SVGA3dSurfaceImageId image; 2417 SVGA3dSurfaceImageId image;
2401} 2418} __packed
2402SVGA3dCmdBindGBScreenTarget; /* SVGA_3D_CMD_BIND_GB_SCREENTARGET */ 2419SVGA3dCmdBindGBScreenTarget; /* SVGA_3D_CMD_BIND_GB_SCREENTARGET */
2403 2420
2404typedef 2421typedef
2405struct { 2422struct {
2406 uint32 stid; 2423 uint32 stid;
2407 SVGA3dBox box; 2424 SVGA3dBox box;
2408} 2425} __packed
2409SVGA3dCmdUpdateGBScreenTarget; /* SVGA_3D_CMD_UPDATE_GB_SCREENTARGET */ 2426SVGA3dCmdUpdateGBScreenTarget; /* SVGA_3D_CMD_UPDATE_GB_SCREENTARGET */
2410 2427
2411/* 2428/*
diff --git a/drivers/gpu/drm/vmwgfx/svga3d_surfacedefs.h b/drivers/gpu/drm/vmwgfx/svga3d_surfacedefs.h
index 8369c3ba10fe..ef3385096145 100644
--- a/drivers/gpu/drm/vmwgfx/svga3d_surfacedefs.h
+++ b/drivers/gpu/drm/vmwgfx/svga3d_surfacedefs.h
@@ -38,8 +38,11 @@
38 38
39#define DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y)) 39#define DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y))
40#define max_t(type, x, y) ((x) > (y) ? (x) : (y)) 40#define max_t(type, x, y) ((x) > (y) ? (x) : (y))
41#define min_t(type, x, y) ((x) < (y) ? (x) : (y))
41#define surf_size_struct SVGA3dSize 42#define surf_size_struct SVGA3dSize
42#define u32 uint32 43#define u32 uint32
44#define u64 uint64_t
45#define U32_MAX ((u32)~0U)
43 46
44#endif /* __KERNEL__ */ 47#endif /* __KERNEL__ */
45 48
@@ -704,8 +707,8 @@ static const struct svga3d_surface_desc svga3d_surface_descs[] = {
704 707
705static inline u32 clamped_umul32(u32 a, u32 b) 708static inline u32 clamped_umul32(u32 a, u32 b)
706{ 709{
707 uint64_t tmp = (uint64_t) a*b; 710 u64 tmp = (u64) a*b;
708 return (tmp > (uint64_t) ((u32) -1)) ? (u32) -1 : tmp; 711 return (tmp > (u64) U32_MAX) ? U32_MAX : tmp;
709} 712}
710 713
711static inline const struct svga3d_surface_desc * 714static inline const struct svga3d_surface_desc *
@@ -834,7 +837,7 @@ svga3dsurface_get_serialized_size(SVGA3dSurfaceFormat format,
834 bool cubemap) 837 bool cubemap)
835{ 838{
836 const struct svga3d_surface_desc *desc = svga3dsurface_get_desc(format); 839 const struct svga3d_surface_desc *desc = svga3dsurface_get_desc(format);
837 u32 total_size = 0; 840 u64 total_size = 0;
838 u32 mip; 841 u32 mip;
839 842
840 for (mip = 0; mip < num_mip_levels; mip++) { 843 for (mip = 0; mip < num_mip_levels; mip++) {
@@ -847,7 +850,7 @@ svga3dsurface_get_serialized_size(SVGA3dSurfaceFormat format,
847 if (cubemap) 850 if (cubemap)
848 total_size *= SVGA3D_MAX_SURFACE_FACES; 851 total_size *= SVGA3D_MAX_SURFACE_FACES;
849 852
850 return total_size; 853 return (u32) min_t(u64, total_size, (u64) U32_MAX);
851} 854}
852 855
853 856
diff --git a/drivers/gpu/drm/vmwgfx/svga_reg.h b/drivers/gpu/drm/vmwgfx/svga_reg.h
index 71defa4d2d75..11323dd5196f 100644
--- a/drivers/gpu/drm/vmwgfx/svga_reg.h
+++ b/drivers/gpu/drm/vmwgfx/svga_reg.h
@@ -169,10 +169,17 @@ enum {
169 SVGA_REG_TRACES = 45, /* Enable trace-based updates even when FIFO is on */ 169 SVGA_REG_TRACES = 45, /* Enable trace-based updates even when FIFO is on */
170 SVGA_REG_GMRS_MAX_PAGES = 46, /* Maximum number of 4KB pages for all GMRs */ 170 SVGA_REG_GMRS_MAX_PAGES = 46, /* Maximum number of 4KB pages for all GMRs */
171 SVGA_REG_MEMORY_SIZE = 47, /* Total dedicated device memory excluding FIFO */ 171 SVGA_REG_MEMORY_SIZE = 47, /* Total dedicated device memory excluding FIFO */
172 SVGA_REG_COMMAND_LOW = 48, /* Lower 32 bits and submits commands */
173 SVGA_REG_COMMAND_HIGH = 49, /* Upper 32 bits of command buffer PA */
172 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM = 50, /* Max primary memory */ 174 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM = 50, /* Max primary memory */
173 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB = 51, /* Suggested limit on mob mem */ 175 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB = 51, /* Suggested limit on mob mem */
174 SVGA_REG_DEV_CAP = 52, /* Write dev cap index, read value */ 176 SVGA_REG_DEV_CAP = 52, /* Write dev cap index, read value */
175 SVGA_REG_TOP = 53, /* Must be 1 more than the last register */ 177 SVGA_REG_CMD_PREPEND_LOW = 53,
178 SVGA_REG_CMD_PREPEND_HIGH = 54,
179 SVGA_REG_SCREENTARGET_MAX_WIDTH = 55,
180 SVGA_REG_SCREENTARGET_MAX_HEIGHT = 56,
181 SVGA_REG_MOB_MAX_SIZE = 57,
182 SVGA_REG_TOP = 58, /* Must be 1 more than the last register */
176 183
177 SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */ 184 SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */
178 /* Next 768 (== 256*3) registers exist for colormap */ 185 /* Next 768 (== 256*3) registers exist for colormap */
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_context.c b/drivers/gpu/drm/vmwgfx/vmwgfx_context.c
index 9426c53fb483..1e80152674b5 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_context.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_context.c
@@ -551,8 +551,7 @@ static int vmw_context_scrub_shader(struct vmw_ctx_bindinfo *bi, bool rebind)
551 cmd->header.size = sizeof(cmd->body); 551 cmd->header.size = sizeof(cmd->body);
552 cmd->body.cid = bi->ctx->id; 552 cmd->body.cid = bi->ctx->id;
553 cmd->body.type = bi->i1.shader_type; 553 cmd->body.type = bi->i1.shader_type;
554 cmd->body.shid = 554 cmd->body.shid = ((rebind) ? bi->res->id : SVGA3D_INVALID_ID);
555 cpu_to_le32((rebind) ? bi->res->id : SVGA3D_INVALID_ID);
556 vmw_fifo_commit(dev_priv, sizeof(*cmd)); 555 vmw_fifo_commit(dev_priv, sizeof(*cmd));
557 556
558 return 0; 557 return 0;
@@ -585,8 +584,7 @@ static int vmw_context_scrub_render_target(struct vmw_ctx_bindinfo *bi,
585 cmd->header.size = sizeof(cmd->body); 584 cmd->header.size = sizeof(cmd->body);
586 cmd->body.cid = bi->ctx->id; 585 cmd->body.cid = bi->ctx->id;
587 cmd->body.type = bi->i1.rt_type; 586 cmd->body.type = bi->i1.rt_type;
588 cmd->body.target.sid = 587 cmd->body.target.sid = ((rebind) ? bi->res->id : SVGA3D_INVALID_ID);
589 cpu_to_le32((rebind) ? bi->res->id : SVGA3D_INVALID_ID);
590 cmd->body.target.face = 0; 588 cmd->body.target.face = 0;
591 cmd->body.target.mipmap = 0; 589 cmd->body.target.mipmap = 0;
592 vmw_fifo_commit(dev_priv, sizeof(*cmd)); 590 vmw_fifo_commit(dev_priv, sizeof(*cmd));
@@ -628,8 +626,7 @@ static int vmw_context_scrub_texture(struct vmw_ctx_bindinfo *bi,
628 cmd->body.c.cid = bi->ctx->id; 626 cmd->body.c.cid = bi->ctx->id;
629 cmd->body.s1.stage = bi->i1.texture_stage; 627 cmd->body.s1.stage = bi->i1.texture_stage;
630 cmd->body.s1.name = SVGA3D_TS_BIND_TEXTURE; 628 cmd->body.s1.name = SVGA3D_TS_BIND_TEXTURE;
631 cmd->body.s1.value = 629 cmd->body.s1.value = ((rebind) ? bi->res->id : SVGA3D_INVALID_ID);
632 cpu_to_le32((rebind) ? bi->res->id : SVGA3D_INVALID_ID);
633 vmw_fifo_commit(dev_priv, sizeof(*cmd)); 630 vmw_fifo_commit(dev_priv, sizeof(*cmd));
634 631
635 return 0; 632 return 0;
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
index 3bdc0adc656d..0083cbf99edf 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
@@ -667,6 +667,7 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
667 dev_priv->memory_size = 512*1024*1024; 667 dev_priv->memory_size = 512*1024*1024;
668 } 668 }
669 dev_priv->max_mob_pages = 0; 669 dev_priv->max_mob_pages = 0;
670 dev_priv->max_mob_size = 0;
670 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 671 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
671 uint64_t mem_size = 672 uint64_t mem_size =
672 vmw_read(dev_priv, 673 vmw_read(dev_priv,
@@ -676,6 +677,8 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
676 dev_priv->prim_bb_mem = 677 dev_priv->prim_bb_mem =
677 vmw_read(dev_priv, 678 vmw_read(dev_priv,
678 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); 679 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM);
680 dev_priv->max_mob_size =
681 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE);
679 } else 682 } else
680 dev_priv->prim_bb_mem = dev_priv->vram_size; 683 dev_priv->prim_bb_mem = dev_priv->vram_size;
681 684
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
index ecaa302a6154..07831554dad7 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
@@ -40,7 +40,7 @@
40#include <drm/ttm/ttm_module.h> 40#include <drm/ttm/ttm_module.h>
41#include "vmwgfx_fence.h" 41#include "vmwgfx_fence.h"
42 42
43#define VMWGFX_DRIVER_DATE "20121114" 43#define VMWGFX_DRIVER_DATE "20140228"
44#define VMWGFX_DRIVER_MAJOR 2 44#define VMWGFX_DRIVER_MAJOR 2
45#define VMWGFX_DRIVER_MINOR 5 45#define VMWGFX_DRIVER_MINOR 5
46#define VMWGFX_DRIVER_PATCHLEVEL 0 46#define VMWGFX_DRIVER_PATCHLEVEL 0
@@ -386,6 +386,7 @@ struct vmw_private {
386 uint32_t max_gmr_ids; 386 uint32_t max_gmr_ids;
387 uint32_t max_gmr_pages; 387 uint32_t max_gmr_pages;
388 uint32_t max_mob_pages; 388 uint32_t max_mob_pages;
389 uint32_t max_mob_size;
389 uint32_t memory_size; 390 uint32_t memory_size;
390 bool has_gmr; 391 bool has_gmr;
391 bool has_mob; 392 bool has_mob;
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
index 269b85cc875a..efb575a7996c 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
@@ -602,7 +602,7 @@ static int vmw_cmd_cid_check(struct vmw_private *dev_priv,
602{ 602{
603 struct vmw_cid_cmd { 603 struct vmw_cid_cmd {
604 SVGA3dCmdHeader header; 604 SVGA3dCmdHeader header;
605 __le32 cid; 605 uint32_t cid;
606 } *cmd; 606 } *cmd;
607 607
608 cmd = container_of(header, struct vmw_cid_cmd, header); 608 cmd = container_of(header, struct vmw_cid_cmd, header);
@@ -1835,7 +1835,7 @@ static int vmw_cmd_check_not_3d(struct vmw_private *dev_priv,
1835 return 0; 1835 return 0;
1836} 1836}
1837 1837
1838static const struct vmw_cmd_entry const vmw_cmd_entries[SVGA_3D_CMD_MAX] = { 1838static const struct vmw_cmd_entry vmw_cmd_entries[SVGA_3D_CMD_MAX] = {
1839 VMW_CMD_DEF(SVGA_3D_CMD_SURFACE_DEFINE, &vmw_cmd_invalid, 1839 VMW_CMD_DEF(SVGA_3D_CMD_SURFACE_DEFINE, &vmw_cmd_invalid,
1840 false, false, false), 1840 false, false, false),
1841 VMW_CMD_DEF(SVGA_3D_CMD_SURFACE_DESTROY, &vmw_cmd_invalid, 1841 VMW_CMD_DEF(SVGA_3D_CMD_SURFACE_DESTROY, &vmw_cmd_invalid,
@@ -2032,6 +2032,9 @@ static int vmw_cmd_check(struct vmw_private *dev_priv,
2032 goto out_invalid; 2032 goto out_invalid;
2033 2033
2034 entry = &vmw_cmd_entries[cmd_id]; 2034 entry = &vmw_cmd_entries[cmd_id];
2035 if (unlikely(!entry->func))
2036 goto out_invalid;
2037
2035 if (unlikely(!entry->user_allow && !sw_context->kernel)) 2038 if (unlikely(!entry->user_allow && !sw_context->kernel))
2036 goto out_privileged; 2039 goto out_privileged;
2037 2040
@@ -2469,7 +2472,7 @@ int vmw_execbuf_process(struct drm_file *file_priv,
2469 if (dev_priv->has_mob) { 2472 if (dev_priv->has_mob) {
2470 ret = vmw_rebind_contexts(sw_context); 2473 ret = vmw_rebind_contexts(sw_context);
2471 if (unlikely(ret != 0)) 2474 if (unlikely(ret != 0))
2472 goto out_err; 2475 goto out_unlock_binding;
2473 } 2476 }
2474 2477
2475 cmd = vmw_fifo_reserve(dev_priv, command_size); 2478 cmd = vmw_fifo_reserve(dev_priv, command_size);
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c b/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
index f9881f9e62bd..47b70949bf3a 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
@@ -102,6 +102,9 @@ int vmw_getparam_ioctl(struct drm_device *dev, void *data,
102 vmw_fp->gb_aware = true; 102 vmw_fp->gb_aware = true;
103 param->value = dev_priv->max_mob_pages * PAGE_SIZE; 103 param->value = dev_priv->max_mob_pages * PAGE_SIZE;
104 break; 104 break;
105 case DRM_VMW_PARAM_MAX_MOB_SIZE:
106 param->value = dev_priv->max_mob_size;
107 break;
105 default: 108 default:
106 DRM_ERROR("Illegal vmwgfx get param request: %d\n", 109 DRM_ERROR("Illegal vmwgfx get param request: %d\n",
107 param->param); 110 param->param);
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_mob.c b/drivers/gpu/drm/vmwgfx/vmwgfx_mob.c
index d4a5a19cb8c3..04a64b8cd3cd 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_mob.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_mob.c
@@ -188,18 +188,20 @@ static void vmw_takedown_otable_base(struct vmw_private *dev_priv,
188 188
189 bo = otable->page_table->pt_bo; 189 bo = otable->page_table->pt_bo;
190 cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd)); 190 cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));
191 if (unlikely(cmd == NULL)) 191 if (unlikely(cmd == NULL)) {
192 DRM_ERROR("Failed reserving FIFO space for OTable setup.\n"); 192 DRM_ERROR("Failed reserving FIFO space for OTable "
193 193 "takedown.\n");
194 memset(cmd, 0, sizeof(*cmd)); 194 } else {
195 cmd->header.id = SVGA_3D_CMD_SET_OTABLE_BASE; 195 memset(cmd, 0, sizeof(*cmd));
196 cmd->header.size = sizeof(cmd->body); 196 cmd->header.id = SVGA_3D_CMD_SET_OTABLE_BASE;
197 cmd->body.type = type; 197 cmd->header.size = sizeof(cmd->body);
198 cmd->body.baseAddress = 0; 198 cmd->body.type = type;
199 cmd->body.sizeInBytes = 0; 199 cmd->body.baseAddress = 0;
200 cmd->body.validSizeInBytes = 0; 200 cmd->body.sizeInBytes = 0;
201 cmd->body.ptDepth = SVGA3D_MOBFMT_INVALID; 201 cmd->body.validSizeInBytes = 0;
202 vmw_fifo_commit(dev_priv, sizeof(*cmd)); 202 cmd->body.ptDepth = SVGA3D_MOBFMT_INVALID;
203 vmw_fifo_commit(dev_priv, sizeof(*cmd));
204 }
203 205
204 if (bo) { 206 if (bo) {
205 int ret; 207 int ret;
@@ -562,11 +564,12 @@ void vmw_mob_unbind(struct vmw_private *dev_priv,
562 if (unlikely(cmd == NULL)) { 564 if (unlikely(cmd == NULL)) {
563 DRM_ERROR("Failed reserving FIFO space for Memory " 565 DRM_ERROR("Failed reserving FIFO space for Memory "
564 "Object unbinding.\n"); 566 "Object unbinding.\n");
567 } else {
568 cmd->header.id = SVGA_3D_CMD_DESTROY_GB_MOB;
569 cmd->header.size = sizeof(cmd->body);
570 cmd->body.mobid = mob->id;
571 vmw_fifo_commit(dev_priv, sizeof(*cmd));
565 } 572 }
566 cmd->header.id = SVGA_3D_CMD_DESTROY_GB_MOB;
567 cmd->header.size = sizeof(cmd->body);
568 cmd->body.mobid = mob->id;
569 vmw_fifo_commit(dev_priv, sizeof(*cmd));
570 if (bo) { 573 if (bo) {
571 vmw_fence_single_bo(bo, NULL); 574 vmw_fence_single_bo(bo, NULL);
572 ttm_bo_unreserve(bo); 575 ttm_bo_unreserve(bo);
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c b/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
index 2aa4bc6a4d60..9757b57f8388 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
@@ -427,8 +427,7 @@ int vmw_dmabuf_init(struct vmw_private *dev_priv,
427 INIT_LIST_HEAD(&vmw_bo->res_list); 427 INIT_LIST_HEAD(&vmw_bo->res_list);
428 428
429 ret = ttm_bo_init(bdev, &vmw_bo->base, size, 429 ret = ttm_bo_init(bdev, &vmw_bo->base, size,
430 (user) ? ttm_bo_type_device : 430 ttm_bo_type_device, placement,
431 ttm_bo_type_kernel, placement,
432 0, interruptible, 431 0, interruptible,
433 NULL, acc_size, NULL, bo_free); 432 NULL, acc_size, NULL, bo_free);
434 return ret; 433 return ret;
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_shader.c b/drivers/gpu/drm/vmwgfx/vmwgfx_shader.c
index 217d941b8176..ee3856578a12 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_shader.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_shader.c
@@ -371,13 +371,13 @@ int vmw_shader_destroy_ioctl(struct drm_device *dev, void *data,
371 TTM_REF_USAGE); 371 TTM_REF_USAGE);
372} 372}
373 373
374int vmw_shader_alloc(struct vmw_private *dev_priv, 374static int vmw_shader_alloc(struct vmw_private *dev_priv,
375 struct vmw_dma_buffer *buffer, 375 struct vmw_dma_buffer *buffer,
376 size_t shader_size, 376 size_t shader_size,
377 size_t offset, 377 size_t offset,
378 SVGA3dShaderType shader_type, 378 SVGA3dShaderType shader_type,
379 struct ttm_object_file *tfile, 379 struct ttm_object_file *tfile,
380 u32 *handle) 380 u32 *handle)
381{ 381{
382 struct vmw_user_shader *ushader; 382 struct vmw_user_shader *ushader;
383 struct vmw_resource *res, *tmp; 383 struct vmw_resource *res, *tmp;
@@ -779,6 +779,8 @@ vmw_compat_shader_man_create(struct vmw_private *dev_priv)
779 int ret; 779 int ret;
780 780
781 man = kzalloc(sizeof(*man), GFP_KERNEL); 781 man = kzalloc(sizeof(*man), GFP_KERNEL);
782 if (man == NULL)
783 return ERR_PTR(-ENOMEM);
782 784
783 man->dev_priv = dev_priv; 785 man->dev_priv = dev_priv;
784 INIT_LIST_HEAD(&man->list); 786 INIT_LIST_HEAD(&man->list);
diff --git a/drivers/gpu/host1x/job.c b/drivers/gpu/host1x/job.c
index 1146e3bba6e1..112f27e51bc7 100644
--- a/drivers/gpu/host1x/job.c
+++ b/drivers/gpu/host1x/job.c
@@ -538,7 +538,7 @@ int host1x_job_pin(struct host1x_job *job, struct device *dev)
538 538
539 g->base = job->gather_addr_phys[i]; 539 g->base = job->gather_addr_phys[i];
540 540
541 for (j = 0; j < job->num_gathers; j++) 541 for (j = i + 1; j < job->num_gathers; j++)
542 if (job->gathers[j].bo == g->bo) 542 if (job->gathers[j].bo == g->bo)
543 job->gathers[j].handled = true; 543 job->gathers[j].handled = true;
544 544
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-31 02:19:35 -0400