Merge tag 'v4.16-rc7' into x86/mm, to fix up conflict

 Conflicts:
	arch/x86/mm/init_64.c

Signed-off-by: Ingo Molnar <mingo@kernel.org>

49 files changed, 344 insertions, 134 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
index 74d2efaec52f..7a073ac5f9c6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
@@ -69,25 +69,18 @@ void amdgpu_connector_hotplug(struct drm_connector *connector)
                 /* don't do anything if sink is not display port, i.e.,
                  * passive dp->(dvi|hdmi) adaptor
                  */
-                if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
-                        int saved_dpms = connector->dpms;
-                        /* Only turn off the display if it's physically disconnected */
-                        if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
-                                drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
-                        } else if (amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) {
-                                /* Don't try to start link training before we
-                                 * have the dpcd */
-                                if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
-                                        return;
-
-                                /* set it to OFF so that drm_helper_connector_dpms()
-                                 * won't return immediately since the current state
-                                 * is ON at this point.
-                                 */
-                                connector->dpms = DRM_MODE_DPMS_OFF;
-                                drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
-                        }
-                        connector->dpms = saved_dpms;
+                if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT &&
+                    amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) &&
+                    amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) {
+                        /* Don't start link training before we have the DPCD */
+                        if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
+                                return;
+
+                        /* Turn the connector off and back on immediately, which
+                         * will trigger link training
+                         */
+                        drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
+                        drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
                 }
         }
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index af1b879a9ee9..66cb10cdc7c3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2063,9 +2063,12 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
 
         DRM_INFO("amdgpu: finishing device.\n");
         adev->shutdown = true;
-        if (adev->mode_info.mode_config_initialized)
-                drm_crtc_force_disable_all(adev->ddev);
-
+        if (adev->mode_info.mode_config_initialized){
+                if (!amdgpu_device_has_dc_support(adev))
+                        drm_crtc_force_disable_all(adev->ddev);
+                else
+                        drm_atomic_helper_shutdown(adev->ddev);
+        }
         amdgpu_ib_pool_fini(adev);
         amdgpu_fence_driver_fini(adev);
         amdgpu_fbdev_fini(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index e48b4ec88c8c..ca6c931dabfa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -36,8 +36,6 @@ void amdgpu_gem_object_free(struct drm_gem_object *gobj)
         struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);
 
         if (robj) {
-                if (robj->gem_base.import_attach)
-                        drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg);
                 amdgpu_mn_unregister(robj);
                 amdgpu_bo_unref(&robj);
         }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
index 54f06c959340..2264c5c97009 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
@@ -352,6 +352,7 @@ struct amdgpu_mode_info {
         u16 firmware_flags;
         /* pointer to backlight encoder */
         struct amdgpu_encoder *bl_encoder;
+        u8 bl_level; /* saved backlight level */
         struct amdgpu_audio     audio; /* audio stuff */
         int                     num_crtc; /* number of crtcs */
         int                     num_hpd; /* number of hpd pins */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 5c4c3e0d527b..1220322c1680 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -56,6 +56,8 @@ static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo)
 
         amdgpu_bo_kunmap(bo);
 
+        if (bo->gem_base.import_attach)
+                drm_prime_gem_destroy(&bo->gem_base, bo->tbo.sg);
         drm_gem_object_release(&bo->gem_base);
         amdgpu_bo_unref(&bo->parent);
         if (!list_empty(&bo->shadow_list)) {
diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
index 2af26d2da127..d702fb8e3427 100644
--- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
+++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
@@ -34,7 +34,7 @@
 #include <linux/backlight.h>
 #include "bif/bif_4_1_d.h"
 
-static u8
+u8
 amdgpu_atombios_encoder_get_backlight_level_from_reg(struct amdgpu_device *adev)
 {
         u8 backlight_level;
@@ -48,7 +48,7 @@ amdgpu_atombios_encoder_get_backlight_level_from_reg(struct amdgpu_device *adev)
         return backlight_level;
 }
 
-static void
+void
 amdgpu_atombios_encoder_set_backlight_level_to_reg(struct amdgpu_device *adev,
                                             u8 backlight_level)
 {
diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.h b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.h
index 2bdec40515ce..f77cbdef679e 100644
--- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.h
+++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.h
@@ -25,6 +25,11 @@
 #define __ATOMBIOS_ENCODER_H__
 
 u8
+amdgpu_atombios_encoder_get_backlight_level_from_reg(struct amdgpu_device *adev);
+void
+amdgpu_atombios_encoder_set_backlight_level_to_reg(struct amdgpu_device *adev,
+                                                   u8 backlight_level);
+u8
 amdgpu_atombios_encoder_get_backlight_level(struct amdgpu_encoder *amdgpu_encoder);
 void
 amdgpu_atombios_encoder_set_backlight_level(struct amdgpu_encoder *amdgpu_encoder,
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index f34bc68aadfb..022f303463fc 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -2921,6 +2921,11 @@ static int dce_v10_0_hw_fini(void *handle)
 
 static int dce_v10_0_suspend(void *handle)
 {
+        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+        adev->mode_info.bl_level =
+                amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
+
         return dce_v10_0_hw_fini(handle);
 }
 
@@ -2929,6 +2934,9 @@ static int dce_v10_0_resume(void *handle)
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
         int ret;
 
+        amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
+                                                           adev->mode_info.bl_level);
+
         ret = dce_v10_0_hw_init(handle);
 
         /* turn on the BL */
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 26378bd6aba4..800a9f36ab4f 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -3047,6 +3047,11 @@ static int dce_v11_0_hw_fini(void *handle)
 
 static int dce_v11_0_suspend(void *handle)
 {
+        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+        adev->mode_info.bl_level =
+                amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
+
         return dce_v11_0_hw_fini(handle);
 }
 
@@ -3055,6 +3060,9 @@ static int dce_v11_0_resume(void *handle)
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
         int ret;
 
+        amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
+                                                           adev->mode_info.bl_level);
+
         ret = dce_v11_0_hw_init(handle);
 
         /* turn on the BL */
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index a712f4b285f6..b8368f69ce1f 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -2787,6 +2787,11 @@ static int dce_v6_0_hw_fini(void *handle)
 
 static int dce_v6_0_suspend(void *handle)
 {
+        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+        adev->mode_info.bl_level =
+                amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
+
         return dce_v6_0_hw_fini(handle);
 }
 
@@ -2795,6 +2800,9 @@ static int dce_v6_0_resume(void *handle)
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
         int ret;
 
+        amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
+                                                           adev->mode_info.bl_level);
+
         ret = dce_v6_0_hw_init(handle);
 
         /* turn on the BL */
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index c008dc030687..012e0a9ae0ff 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -2819,6 +2819,11 @@ static int dce_v8_0_hw_fini(void *handle)
 
 static int dce_v8_0_suspend(void *handle)
 {
+        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+        adev->mode_info.bl_level =
+                amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
+
         return dce_v8_0_hw_fini(handle);
 }
 
@@ -2827,6 +2832,9 @@ static int dce_v8_0_resume(void *handle)
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
         int ret;
 
+        amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
+                                                           adev->mode_info.bl_level);
+
         ret = dce_v8_0_hw_init(handle);
 
         /* turn on the BL */
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index c345e645f1d7..63c67346d316 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -3134,8 +3134,6 @@ static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
 
         switch (aplane->base.type) {
         case DRM_PLANE_TYPE_PRIMARY:
-                aplane->base.format_default = true;
-
                 res = drm_universal_plane_init(
                                 dm->adev->ddev,
                                 &aplane->base,
@@ -4794,6 +4792,9 @@ static int dm_atomic_check_plane_state_fb(struct drm_atomic_state *state,
                         return -EDEADLK;
 
                 crtc_state = drm_atomic_get_crtc_state(plane_state->state, crtc);
+                if (IS_ERR(crtc_state))
+                        return PTR_ERR(crtc_state);
+
                 if (crtc->primary == plane && crtc_state->active) {
                         if (!plane_state->fb)
                                 return -EINVAL;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index 9bd142f65f9b..e1acc10e35a2 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -109,7 +109,7 @@ enum dc_edid_status dm_helpers_parse_edid_caps(
                 struct cea_sad *sad = &sads[i];
 
                 edid_caps->audio_modes[i].format_code = sad->format;
-                edid_caps->audio_modes[i].channel_count = sad->channels;
+                edid_caps->audio_modes[i].channel_count = sad->channels + 1;
                 edid_caps->audio_modes[i].sample_rate = sad->freq;
                 edid_caps->audio_modes[i].sample_size = sad->byte2;
         }
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index a993279a8f2d..f11f17fe08f9 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -496,6 +496,9 @@ struct dce_hwseq_registers {
         HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
         HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
         HWS_SF(, D1VGA_CONTROL, D1VGA_MODE_ENABLE, mask_sh),\
+        HWS_SF(, D2VGA_CONTROL, D2VGA_MODE_ENABLE, mask_sh),\
+        HWS_SF(, D3VGA_CONTROL, D3VGA_MODE_ENABLE, mask_sh),\
+        HWS_SF(, D4VGA_CONTROL, D4VGA_MODE_ENABLE, mask_sh),\
         HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\
         HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh),\
         HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
@@ -591,7 +594,10 @@ struct dce_hwseq_registers {
         type DENTIST_DISPCLK_WDIVIDER; \
         type VGA_TEST_ENABLE; \
         type VGA_TEST_RENDER_START; \
-        type D1VGA_MODE_ENABLE;
+        type D1VGA_MODE_ENABLE; \
+        type D2VGA_MODE_ENABLE; \
+        type D3VGA_MODE_ENABLE; \
+        type D4VGA_MODE_ENABLE;
 
 struct dce_hwseq_shift {
         HWSEQ_REG_FIELD_LIST(uint8_t)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
index 3931412ab6d3..87093894ea9e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
@@ -128,23 +128,22 @@ static void set_truncation(
                 return;
         }
         /* on other format-to do */
-        if (params->flags.TRUNCATE_ENABLED == 0 ||
-                        params->flags.TRUNCATE_DEPTH == 2)
+        if (params->flags.TRUNCATE_ENABLED == 0)
                 return;
         /*Set truncation depth and Enable truncation*/
         REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
                                 FMT_TRUNCATE_EN, 1,
                                 FMT_TRUNCATE_DEPTH,
-                                params->flags.TRUNCATE_MODE,
+                                params->flags.TRUNCATE_DEPTH,
                                 FMT_TRUNCATE_MODE,
-                                params->flags.TRUNCATE_DEPTH);
+                                params->flags.TRUNCATE_MODE);
 }
 
 
 /**
  *      set_spatial_dither
  *      1) set spatial dithering mode: pattern of seed
- *      2) set spatical dithering depth: 0 for 18bpp or 1 for 24bpp
+ *      2) set spatial dithering depth: 0 for 18bpp or 1 for 24bpp
  *      3) set random seed
  *      4) set random mode
  *              lfsr is reset every frame or not reset
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 072e4485e85e..dc1e010725c1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -238,14 +238,24 @@ static void enable_power_gating_plane(
 static void disable_vga(
         struct dce_hwseq *hws)
 {
-        unsigned int in_vga_mode = 0;
-
-        REG_GET(D1VGA_CONTROL, D1VGA_MODE_ENABLE, &in_vga_mode);
-
-        if (in_vga_mode == 0)
+        unsigned int in_vga1_mode = 0;
+        unsigned int in_vga2_mode = 0;
+        unsigned int in_vga3_mode = 0;
+        unsigned int in_vga4_mode = 0;
+
+        REG_GET(D1VGA_CONTROL, D1VGA_MODE_ENABLE, &in_vga1_mode);
+        REG_GET(D2VGA_CONTROL, D2VGA_MODE_ENABLE, &in_vga2_mode);
+        REG_GET(D3VGA_CONTROL, D3VGA_MODE_ENABLE, &in_vga3_mode);
+        REG_GET(D4VGA_CONTROL, D4VGA_MODE_ENABLE, &in_vga4_mode);
+
+        if (in_vga1_mode == 0 && in_vga2_mode == 0 &&
+                        in_vga3_mode == 0 && in_vga4_mode == 0)
                 return;
 
         REG_WRITE(D1VGA_CONTROL, 0);
+        REG_WRITE(D2VGA_CONTROL, 0);
+        REG_WRITE(D3VGA_CONTROL, 0);
+        REG_WRITE(D4VGA_CONTROL, 0);
 
         /* HW Engineer's Notes:
          *  During switch from vga->extended, if we set the VGA_TEST_ENABLE and
diff --git a/drivers/gpu/drm/ast/ast_tables.h b/drivers/gpu/drm/ast/ast_tables.h
index 5f4c2e833a65..d665dd5af5dd 100644
--- a/drivers/gpu/drm/ast/ast_tables.h
+++ b/drivers/gpu/drm/ast/ast_tables.h
@@ -97,7 +97,7 @@ static const struct ast_vbios_dclk_info dclk_table[] = {
         {0x67, 0x22, 0x00},                     /* 0E: VCLK157_5        */
         {0x6A, 0x22, 0x00},                     /* 0F: VCLK162          */
         {0x4d, 0x4c, 0x80},                     /* 10: VCLK154          */
-        {0xa7, 0x78, 0x80},                     /* 11: VCLK83.5         */
+        {0x68, 0x6f, 0x80},                     /* 11: VCLK83.5         */
         {0x28, 0x49, 0x80},                     /* 12: VCLK106.5        */
         {0x37, 0x49, 0x80},                     /* 13: VCLK146.25       */
         {0x1f, 0x45, 0x80},                     /* 14: VCLK148.5        */
@@ -127,7 +127,7 @@ static const struct ast_vbios_dclk_info dclk_table_ast2500[] = {
         {0x67, 0x22, 0x00},                     /* 0E: VCLK157_5        */
         {0x6A, 0x22, 0x00},                     /* 0F: VCLK162          */
         {0x4d, 0x4c, 0x80},                     /* 10: VCLK154          */
-        {0xa7, 0x78, 0x80},                     /* 11: VCLK83.5         */
+        {0x68, 0x6f, 0x80},                     /* 11: VCLK83.5         */
         {0x28, 0x49, 0x80},                     /* 12: VCLK106.5        */
         {0x37, 0x49, 0x80},                     /* 13: VCLK146.25       */
         {0x1f, 0x45, 0x80},                     /* 14: VCLK148.5        */
diff --git a/drivers/gpu/drm/drm_framebuffer.c b/drivers/gpu/drm/drm_framebuffer.c
index c0530a1af5e3..2dc5e8bed172 100644
--- a/drivers/gpu/drm/drm_framebuffer.c
+++ b/drivers/gpu/drm/drm_framebuffer.c
@@ -461,6 +461,12 @@ int drm_mode_getfb(struct drm_device *dev,
         if (!fb)
                 return -ENOENT;
 
+        /* Multi-planar framebuffers need getfb2. */
+        if (fb->format->num_planes > 1) {
+                ret = -EINVAL;
+                goto out;
+        }
+
         r->height = fb->height;
         r->width = fb->width;
         r->depth = fb->format->depth;
@@ -484,6 +490,7 @@ int drm_mode_getfb(struct drm_device *dev,
                 ret = -ENODEV;
         }
 
+out:
         drm_framebuffer_put(fb);
 
         return ret;
diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index c8454ac43fae..db6b94dda5df 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -471,6 +471,7 @@ struct parser_exec_state {
          * used when ret from 2nd level batch buffer
          */
         int saved_buf_addr_type;
+        bool is_ctx_wa;
 
         struct cmd_info *info;
 
@@ -1715,6 +1716,11 @@ static int perform_bb_shadow(struct parser_exec_state *s)
         bb->accessing = true;
         bb->bb_start_cmd_va = s->ip_va;
 
+        if ((s->buf_type == BATCH_BUFFER_INSTRUCTION) && (!s->is_ctx_wa))
+                bb->bb_offset = s->ip_va - s->rb_va;
+        else
+                bb->bb_offset = 0;
+
         /*
          * ip_va saves the virtual address of the shadow batch buffer, while
          * ip_gma saves the graphics address of the original batch buffer.
@@ -2571,6 +2577,7 @@ static int scan_workload(struct intel_vgpu_workload *workload)
         s.ring_tail = gma_tail;
         s.rb_va = workload->shadow_ring_buffer_va;
         s.workload = workload;
+        s.is_ctx_wa = false;
 
         if ((bypass_scan_mask & (1 << workload->ring_id)) ||
                 gma_head == gma_tail)
@@ -2624,6 +2631,7 @@ static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
         s.ring_tail = gma_tail;
         s.rb_va = wa_ctx->indirect_ctx.shadow_va;
         s.workload = workload;
+        s.is_ctx_wa = true;
 
         if (!intel_gvt_ggtt_validate_range(s.vgpu, s.ring_start, s.ring_size)) {
                 ret = -EINVAL;
diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
index 256f1bb522b7..152df3d0291e 100644
--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
@@ -394,9 +394,11 @@ void intel_gvt_switch_mmio(struct intel_vgpu *pre,
          * performace for batch mmio read/write, so we need
          * handle forcewake mannually.
          */
+        intel_runtime_pm_get(dev_priv);
         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
         switch_mmio(pre, next, ring_id);
         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+        intel_runtime_pm_put(dev_priv);
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
index b55b3580ca1d..d74d6f05c62c 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -52,6 +52,54 @@ static void set_context_pdp_root_pointer(
                 pdp_pair[i].val = pdp[7 - i];
 }
 
+/*
+ * when populating shadow ctx from guest, we should not overrride oa related
+ * registers, so that they will not be overlapped by guest oa configs. Thus
+ * made it possible to capture oa data from host for both host and guests.
+ */
+static void sr_oa_regs(struct intel_vgpu_workload *workload,
+                u32 *reg_state, bool save)
+{
+        struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv;
+        u32 ctx_oactxctrl = dev_priv->perf.oa.ctx_oactxctrl_offset;
+        u32 ctx_flexeu0 = dev_priv->perf.oa.ctx_flexeu0_offset;
+        int i = 0;
+        u32 flex_mmio[] = {
+                i915_mmio_reg_offset(EU_PERF_CNTL0),
+                i915_mmio_reg_offset(EU_PERF_CNTL1),
+                i915_mmio_reg_offset(EU_PERF_CNTL2),
+                i915_mmio_reg_offset(EU_PERF_CNTL3),
+                i915_mmio_reg_offset(EU_PERF_CNTL4),
+                i915_mmio_reg_offset(EU_PERF_CNTL5),
+                i915_mmio_reg_offset(EU_PERF_CNTL6),
+        };
+
+        if (!workload || !reg_state || workload->ring_id != RCS)
+                return;
+
+        if (save) {
+                workload->oactxctrl = reg_state[ctx_oactxctrl + 1];
+
+                for (i = 0; i < ARRAY_SIZE(workload->flex_mmio); i++) {
+                        u32 state_offset = ctx_flexeu0 + i * 2;
+
+                        workload->flex_mmio[i] = reg_state[state_offset + 1];
+                }
+        } else {
+                reg_state[ctx_oactxctrl] =
+                        i915_mmio_reg_offset(GEN8_OACTXCONTROL);
+                reg_state[ctx_oactxctrl + 1] = workload->oactxctrl;
+
+                for (i = 0; i < ARRAY_SIZE(workload->flex_mmio); i++) {
+                        u32 state_offset = ctx_flexeu0 + i * 2;
+                        u32 mmio = flex_mmio[i];
+
+                        reg_state[state_offset] = mmio;
+                        reg_state[state_offset + 1] = workload->flex_mmio[i];
+                }
+        }
+}
+
 static int populate_shadow_context(struct intel_vgpu_workload *workload)
 {
         struct intel_vgpu *vgpu = workload->vgpu;
@@ -98,6 +146,7 @@ static int populate_shadow_context(struct intel_vgpu_workload *workload)
         page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
         shadow_ring_context = kmap(page);
 
+        sr_oa_regs(workload, (u32 *)shadow_ring_context, true);
 #define COPY_REG(name) \
         intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \
                 + RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
@@ -122,6 +171,7 @@ static int populate_shadow_context(struct intel_vgpu_workload *workload)
                         sizeof(*shadow_ring_context),
                         I915_GTT_PAGE_SIZE - sizeof(*shadow_ring_context));
 
+        sr_oa_regs(workload, (u32 *)shadow_ring_context, false);
         kunmap(page);
         return 0;
 }
@@ -376,6 +426,17 @@ static int prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload)
                         goto err;
                 }
 
+                /* For privilge batch buffer and not wa_ctx, the bb_start_cmd_va
+                 * is only updated into ring_scan_buffer, not real ring address
+                 * allocated in later copy_workload_to_ring_buffer. pls be noted
+                 * shadow_ring_buffer_va is now pointed to real ring buffer va
+                 * in copy_workload_to_ring_buffer.
+                 */
+
+                if (bb->bb_offset)
+                        bb->bb_start_cmd_va = workload->shadow_ring_buffer_va
+                                + bb->bb_offset;
+
                 /* relocate shadow batch buffer */
                 bb->bb_start_cmd_va[1] = i915_ggtt_offset(bb->vma);
                 if (gmadr_bytes == 8)
@@ -1044,10 +1105,12 @@ int intel_vgpu_setup_submission(struct intel_vgpu *vgpu)
 
         bitmap_zero(s->shadow_ctx_desc_updated, I915_NUM_ENGINES);
 
-        s->workloads = kmem_cache_create("gvt-g_vgpu_workload",
-                        sizeof(struct intel_vgpu_workload), 0,
-                        SLAB_HWCACHE_ALIGN,
-                        NULL);
+        s->workloads = kmem_cache_create_usercopy("gvt-g_vgpu_workload",
+                                                  sizeof(struct intel_vgpu_workload), 0,
+                                                  SLAB_HWCACHE_ALIGN,
+                                                  offsetof(struct intel_vgpu_workload, rb_tail),
+                                                  sizeof_field(struct intel_vgpu_workload, rb_tail),
+                                                  NULL);
 
         if (!s->workloads) {
                 ret = -ENOMEM;
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.h b/drivers/gpu/drm/i915/gvt/scheduler.h
index ff175a98b19e..a79a4f60637e 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.h
+++ b/drivers/gpu/drm/i915/gvt/scheduler.h
@@ -110,6 +110,10 @@ struct intel_vgpu_workload {
         /* shadow batch buffer */
         struct list_head shadow_bb;
         struct intel_shadow_wa_ctx wa_ctx;
+
+        /* oa registers */
+        u32 oactxctrl;
+        u32 flex_mmio[7];
 };
 
 struct intel_vgpu_shadow_bb {
@@ -120,6 +124,7 @@ struct intel_vgpu_shadow_bb {
         u32 *bb_start_cmd_va;
         unsigned int clflush;
         bool accessing;
+        unsigned long bb_offset;
 };
 
 #define workload_q_head(vgpu, ring_id) \
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 66ee9d888d16..6ff5d655c202 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -434,20 +434,28 @@ i915_gem_object_wait_reservation(struct reservation_object *resv,
                         dma_fence_put(shared[i]);
                 kfree(shared);
 
+                /*
+                 * If both shared fences and an exclusive fence exist,
+                 * then by construction the shared fences must be later
+                 * than the exclusive fence. If we successfully wait for
+                 * all the shared fences, we know that the exclusive fence
+                 * must all be signaled. If all the shared fences are
+                 * signaled, we can prune the array and recover the
+                 * floating references on the fences/requests.
+                 */
                 prune_fences = count && timeout >= 0;
         } else {
                 excl = reservation_object_get_excl_rcu(resv);
         }
 
-        if (excl && timeout >= 0) {
+        if (excl && timeout >= 0)
                 timeout = i915_gem_object_wait_fence(excl, flags, timeout,
                                                      rps_client);
-                prune_fences = timeout >= 0;
-        }
 
         dma_fence_put(excl);
 
-        /* Oportunistically prune the fences iff we know they have *all* been
+        /*
+         * Opportunistically prune the fences iff we know they have *all* been
          * signaled and that the reservation object has not been changed (i.e.
          * no new fences have been added).
          */
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index b33d2158c234..e5e6f6bb2b05 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -304,8 +304,9 @@ static ssize_t gt_boost_freq_mhz_store(struct device *kdev,
 {
         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
         struct intel_rps *rps = &dev_priv->gt_pm.rps;
-        u32 val;
+        bool boost = false;
         ssize_t ret;
+        u32 val;
 
         ret = kstrtou32(buf, 0, &val);
         if (ret)
@@ -317,8 +318,13 @@ static ssize_t gt_boost_freq_mhz_store(struct device *kdev,
                 return -EINVAL;
 
         mutex_lock(&dev_priv->pcu_lock);
-        rps->boost_freq = val;
+        if (val != rps->boost_freq) {
+                rps->boost_freq = val;
+                boost = atomic_read(&rps->num_waiters);
+        }
         mutex_unlock(&dev_priv->pcu_lock);
+        if (boost)
+                schedule_work(&rps->work);
 
         return count;
 }
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index f51645a08dca..6aff9d096e13 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2175,8 +2175,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
 
         intel_ddi_init_dp_buf_reg(encoder);
-        if (!is_mst)
-                intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+        intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
         intel_dp_start_link_train(intel_dp);
         if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
                 intel_dp_stop_link_train(intel_dp);
@@ -2274,14 +2273,12 @@ static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
         struct intel_dp *intel_dp = &dig_port->dp;
-        bool is_mst = intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST);
 
         /*
          * Power down sink before disabling the port, otherwise we end
          * up getting interrupts from the sink on detecting link loss.
          */
-        if (!is_mst)
-                intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
+        intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
 
         intel_disable_ddi_buf(encoder);
 
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 35c5299feab6..a29868cd30c7 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -620,19 +620,15 @@ static int
 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 {
         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
+        int backlight_controller = dev_priv->vbt.backlight.controller;
 
         lockdep_assert_held(&dev_priv->pps_mutex);
 
         /* We should never land here with regular DP ports */
         WARN_ON(!intel_dp_is_edp(intel_dp));
 
-        /*
-         * TODO: BXT has 2 PPS instances. The correct port->PPS instance
-         * mapping needs to be retrieved from VBT, for now just hard-code to
-         * use instance #0 always.
-         */
         if (!intel_dp->pps_reset)
-                return 0;
+                return backlight_controller;
 
         intel_dp->pps_reset = false;
 
@@ -642,7 +638,7 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp)
          */
         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 
-        return 0;
+        return backlight_controller;
 }
 
 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c b/drivers/gpu/drm/i915/intel_hangcheck.c
index 348a4f7ffb67..53747318f4a7 100644
--- a/drivers/gpu/drm/i915/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/intel_hangcheck.c
@@ -246,7 +246,7 @@ engine_stuck(struct intel_engine_cs *engine, u64 acthd)
          */
         tmp = I915_READ_CTL(engine);
         if (tmp & RING_WAIT) {
-                i915_handle_error(dev_priv, 0,
+                i915_handle_error(dev_priv, BIT(engine->id),
                                   "Kicking stuck wait on %s",
                                   engine->name);
                 I915_WRITE_CTL(engine, tmp);
@@ -258,7 +258,7 @@ engine_stuck(struct intel_engine_cs *engine, u64 acthd)
                 default:
                         return ENGINE_DEAD;
                 case 1:
-                        i915_handle_error(dev_priv, 0,
+                        i915_handle_error(dev_priv, ALL_ENGINES,
                                           "Kicking stuck semaphore on %s",
                                           engine->name);
                         I915_WRITE_CTL(engine, tmp);
diff --git a/drivers/gpu/drm/imx/ipuv3-crtc.c b/drivers/gpu/drm/imx/ipuv3-crtc.c
index 9a9961802f5c..e83af0f2be86 100644
--- a/drivers/gpu/drm/imx/ipuv3-crtc.c
+++ b/drivers/gpu/drm/imx/ipuv3-crtc.c
@@ -225,7 +225,11 @@ static void ipu_crtc_atomic_begin(struct drm_crtc *crtc,
                                   struct drm_crtc_state *old_crtc_state)
 {
         drm_crtc_vblank_on(crtc);
+}
 
+static void ipu_crtc_atomic_flush(struct drm_crtc *crtc,
+                                  struct drm_crtc_state *old_crtc_state)
+{
         spin_lock_irq(&crtc->dev->event_lock);
         if (crtc->state->event) {
                 WARN_ON(drm_crtc_vblank_get(crtc));
@@ -293,6 +297,7 @@ static const struct drm_crtc_helper_funcs ipu_helper_funcs = {
         .mode_set_nofb = ipu_crtc_mode_set_nofb,
         .atomic_check = ipu_crtc_atomic_check,
         .atomic_begin = ipu_crtc_atomic_begin,
+        .atomic_flush = ipu_crtc_atomic_flush,
         .atomic_disable = ipu_crtc_atomic_disable,
         .atomic_enable = ipu_crtc_atomic_enable,
 };
diff --git a/drivers/gpu/drm/imx/ipuv3-plane.c b/drivers/gpu/drm/imx/ipuv3-plane.c
index 57ed56d8623f..d9113faaa62f 100644
--- a/drivers/gpu/drm/imx/ipuv3-plane.c
+++ b/drivers/gpu/drm/imx/ipuv3-plane.c
@@ -22,6 +22,7 @@
 #include <drm/drm_plane_helper.h>
 
 #include "video/imx-ipu-v3.h"
+#include "imx-drm.h"
 #include "ipuv3-plane.h"
 
 struct ipu_plane_state {
@@ -272,7 +273,7 @@ static void ipu_plane_destroy(struct drm_plane *plane)
         kfree(ipu_plane);
 }
 
-void ipu_plane_state_reset(struct drm_plane *plane)
+static void ipu_plane_state_reset(struct drm_plane *plane)
 {
         struct ipu_plane_state *ipu_state;
 
@@ -292,7 +293,8 @@ void ipu_plane_state_reset(struct drm_plane *plane)
         plane->state = &ipu_state->base;
 }
 
-struct drm_plane_state *ipu_plane_duplicate_state(struct drm_plane *plane)
+static struct drm_plane_state *
+ipu_plane_duplicate_state(struct drm_plane *plane)
 {
         struct ipu_plane_state *state;
 
@@ -306,8 +308,8 @@ struct drm_plane_state *ipu_plane_duplicate_state(struct drm_plane *plane)
         return &state->base;
 }
 
-void ipu_plane_destroy_state(struct drm_plane *plane,
-                             struct drm_plane_state *state)
+static void ipu_plane_destroy_state(struct drm_plane *plane,
+                                    struct drm_plane_state *state)
 {
         struct ipu_plane_state *ipu_state = to_ipu_plane_state(state);
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_backlight.c b/drivers/gpu/drm/nouveau/nouveau_backlight.c
index 380f340204e8..debbbf0fd4bd 100644
--- a/drivers/gpu/drm/nouveau/nouveau_backlight.c
+++ b/drivers/gpu/drm/nouveau/nouveau_backlight.c
@@ -134,7 +134,7 @@ nv50_get_intensity(struct backlight_device *bd)
         struct nouveau_encoder *nv_encoder = bl_get_data(bd);
         struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
         struct nvif_object *device = &drm->client.device.object;
-        int or = nv_encoder->or;
+        int or = ffs(nv_encoder->dcb->or) - 1;
         u32 div = 1025;
         u32 val;
 
@@ -149,7 +149,7 @@ nv50_set_intensity(struct backlight_device *bd)
         struct nouveau_encoder *nv_encoder = bl_get_data(bd);
         struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
         struct nvif_object *device = &drm->client.device.object;
-        int or = nv_encoder->or;
+        int or = ffs(nv_encoder->dcb->or) - 1;
         u32 div = 1025;
         u32 val = (bd->props.brightness * div) / 100;
 
@@ -170,7 +170,7 @@ nva3_get_intensity(struct backlight_device *bd)
         struct nouveau_encoder *nv_encoder = bl_get_data(bd);
         struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
         struct nvif_object *device = &drm->client.device.object;
-        int or = nv_encoder->or;
+        int or = ffs(nv_encoder->dcb->or) - 1;
         u32 div, val;
 
         div  = nvif_rd32(device, NV50_PDISP_SOR_PWM_DIV(or));
@@ -188,7 +188,7 @@ nva3_set_intensity(struct backlight_device *bd)
         struct nouveau_encoder *nv_encoder = bl_get_data(bd);
         struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
         struct nvif_object *device = &drm->client.device.object;
-        int or = nv_encoder->or;
+        int or = ffs(nv_encoder->dcb->or) - 1;
         u32 div, val;
 
         div = nvif_rd32(device, NV50_PDISP_SOR_PWM_DIV(or));
@@ -228,7 +228,7 @@ nv50_backlight_init(struct drm_connector *connector)
                         return -ENODEV;
         }
 
-        if (!nvif_rd32(device, NV50_PDISP_SOR_PWM_CTL(nv_encoder->or)))
+        if (!nvif_rd32(device, NV50_PDISP_SOR_PWM_CTL(ffs(nv_encoder->dcb->or) - 1)))
                 return 0;
 
         if (drm->client.device.info.chipset <= 0xa0 ||
@@ -268,13 +268,13 @@ nouveau_backlight_init(struct drm_device *dev)
         struct nvif_device *device = &drm->client.device;
         struct drm_connector *connector;
 
+        INIT_LIST_HEAD(&drm->bl_connectors);
+
         if (apple_gmux_present()) {
                 NV_INFO(drm, "Apple GMUX detected: not registering Nouveau backlight interface\n");
                 return 0;
         }
 
-        INIT_LIST_HEAD(&drm->bl_connectors);
-
         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
                 if (connector->connector_type != DRM_MODE_CONNECTOR_LVDS &&
                     connector->connector_type != DRM_MODE_CONNECTOR_eDP)
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c
index 93946dcee319..1c12e58f44c2 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c
@@ -1354,7 +1354,7 @@ nvkm_vmm_get_locked(struct nvkm_vmm *vmm, bool getref, bool mapref, bool sparse,
 
                 tail = this->addr + this->size;
                 if (vmm->func->page_block && next && next->page != p)
-                        tail = ALIGN_DOWN(addr, vmm->func->page_block);
+                        tail = ALIGN_DOWN(tail, vmm->func->page_block);
 
                 if (addr <= tail && tail - addr >= size) {
                         rb_erase(&this->tree, &vmm->free);
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index 2e2ca3c6b47d..df9469a8fdb1 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -90,25 +90,18 @@ void radeon_connector_hotplug(struct drm_connector *connector)
                 /* don't do anything if sink is not display port, i.e.,
                  * passive dp->(dvi|hdmi) adaptor
                  */
-                if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
-                        int saved_dpms = connector->dpms;
-                        /* Only turn off the display if it's physically disconnected */
-                        if (!radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) {
-                                drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
-                        } else if (radeon_dp_needs_link_train(radeon_connector)) {
-                                /* Don't try to start link training before we
-                                 * have the dpcd */
-                                if (!radeon_dp_getdpcd(radeon_connector))
-                                        return;
-
-                                /* set it to OFF so that drm_helper_connector_dpms()
-                                 * won't return immediately since the current state
-                                 * is ON at this point.
-                                 */
-                                connector->dpms = DRM_MODE_DPMS_OFF;
-                                drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
-                        }
-                        connector->dpms = saved_dpms;
+                if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT &&
+                    radeon_hpd_sense(rdev, radeon_connector->hpd.hpd) &&
+                    radeon_dp_needs_link_train(radeon_connector)) {
+                        /* Don't start link training before we have the DPCD */
+                        if (!radeon_dp_getdpcd(radeon_connector))
+                                return;
+
+                        /* Turn the connector off and back on immediately, which
+                         * will trigger link training
+                         */
+                        drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
+                        drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
                 }
         }
 }
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
index a9962ffba720..27d8e7dd2d06 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -34,8 +34,6 @@ void radeon_gem_object_free(struct drm_gem_object *gobj)
         struct radeon_bo *robj = gem_to_radeon_bo(gobj);
 
         if (robj) {
-                if (robj->gem_base.import_attach)
-                        drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg);
                 radeon_mn_unregister(robj);
                 radeon_bo_unref(&robj);
         }
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index 15404af9d740..31f5ad605e59 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -82,6 +82,8 @@ static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
         mutex_unlock(&bo->rdev->gem.mutex);
         radeon_bo_clear_surface_reg(bo);
         WARN_ON_ONCE(!list_empty(&bo->va));
+        if (bo->gem_base.import_attach)
+                drm_prime_gem_destroy(&bo->gem_base, bo->tbo.sg);
         drm_gem_object_release(&bo->gem_base);
         kfree(bo);
 }
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c
index 4570da0227b4..d9a71f361b14 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -111,7 +111,7 @@ static int sun4i_drv_bind(struct device *dev)
         /* drm_vblank_init calls kcalloc, which can fail */
         ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
         if (ret)
-                goto free_mem_region;
+                goto cleanup_mode_config;
 
         drm->irq_enabled = true;
 
@@ -139,7 +139,6 @@ finish_poll:
         sun4i_framebuffer_free(drm);
 cleanup_mode_config:
         drm_mode_config_cleanup(drm);
-free_mem_region:
         of_reserved_mem_device_release(dev);
 free_drm:
         drm_dev_unref(drm);
diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
index 500b6fb3e028..fa4bcd092eaf 100644
--- a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
+++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
@@ -538,7 +538,8 @@ static int sun4i_hdmi_bind(struct device *dev, struct device *master,
                                              &sun4i_hdmi_regmap_config);
         if (IS_ERR(hdmi->regmap)) {
                 dev_err(dev, "Couldn't create HDMI encoder regmap\n");
-                return PTR_ERR(hdmi->regmap);
+                ret = PTR_ERR(hdmi->regmap);
+                goto err_disable_mod_clk;
         }
 
         ret = sun4i_tmds_create(hdmi);
@@ -551,7 +552,8 @@ static int sun4i_hdmi_bind(struct device *dev, struct device *master,
                 hdmi->ddc_parent_clk = devm_clk_get(dev, "ddc");
                 if (IS_ERR(hdmi->ddc_parent_clk)) {
                         dev_err(dev, "Couldn't get the HDMI DDC clock\n");
-                        return PTR_ERR(hdmi->ddc_parent_clk);
+                        ret = PTR_ERR(hdmi->ddc_parent_clk);
+                        goto err_disable_mod_clk;
                 }
         } else {
                 hdmi->ddc_parent_clk = hdmi->tmds_clk;
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index 2de586b7c98b..a818ca491605 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -103,6 +103,7 @@ static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel,
 
         if (enabled) {
                 clk_prepare_enable(clk);
+                clk_rate_exclusive_get(clk);
         } else {
                 clk_rate_exclusive_put(clk);
                 clk_disable_unprepare(clk);
@@ -262,7 +263,7 @@ static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon,
                                         const struct drm_display_mode *mode)
 {
         /* Configure the dot clock */
-        clk_set_rate_exclusive(tcon->dclk, mode->crtc_clock * 1000);
+        clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
 
         /* Set the resolution */
         regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
@@ -423,7 +424,7 @@ static void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
         WARN_ON(!tcon->quirks->has_channel_1);
 
         /* Configure the dot clock */
-        clk_set_rate_exclusive(tcon->sclk1, mode->crtc_clock * 1000);
+        clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000);
 
         /* Adjust clock delay */
         clk_delay = sun4i_tcon_get_clk_delay(mode, 1);
diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
index b8403ed48285..fbffe1948b3b 100644
--- a/drivers/gpu/drm/tegra/dc.c
+++ b/drivers/gpu/drm/tegra/dc.c
@@ -1903,8 +1903,12 @@ cleanup:
         if (!IS_ERR(primary))
                 drm_plane_cleanup(primary);
 
-        if (group && tegra->domain) {
-                iommu_detach_group(tegra->domain, group);
+        if (group && dc->domain) {
+                if (group == tegra->group) {
+                        iommu_detach_group(dc->domain, group);
+                        tegra->group = NULL;
+                }
+
                 dc->domain = NULL;
         }
 
@@ -1913,8 +1917,10 @@ cleanup:
 
 static int tegra_dc_exit(struct host1x_client *client)
 {
+        struct drm_device *drm = dev_get_drvdata(client->parent);
         struct iommu_group *group = iommu_group_get(client->dev);
         struct tegra_dc *dc = host1x_client_to_dc(client);
+        struct tegra_drm *tegra = drm->dev_private;
         int err;
 
         devm_free_irq(dc->dev, dc->irq, dc);
@@ -1926,7 +1932,11 @@ static int tegra_dc_exit(struct host1x_client *client)
         }
 
         if (group && dc->domain) {
-                iommu_detach_group(dc->domain, group);
+                if (group == tegra->group) {
+                        iommu_detach_group(dc->domain, group);
+                        tegra->group = NULL;
+                }
+
                 dc->domain = NULL;
         }
 
diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
index d50bddb2e447..7fcf4a242840 100644
--- a/drivers/gpu/drm/tegra/drm.c
+++ b/drivers/gpu/drm/tegra/drm.c
@@ -250,6 +250,7 @@ static void tegra_drm_unload(struct drm_device *drm)
 
         drm_kms_helper_poll_fini(drm);
         tegra_drm_fb_exit(drm);
+        drm_atomic_helper_shutdown(drm);
         drm_mode_config_cleanup(drm);
 
         err = host1x_device_exit(device);
diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c
index 4d2ed966f9e3..87c5d89bc9ba 100644
--- a/drivers/gpu/drm/tegra/dsi.c
+++ b/drivers/gpu/drm/tegra/dsi.c
@@ -1072,7 +1072,6 @@ static int tegra_dsi_exit(struct host1x_client *client)
         struct tegra_dsi *dsi = host1x_client_to_dsi(client);
 
         tegra_output_exit(&dsi->output);
-        regulator_disable(dsi->vdd);
 
         return 0;
 }
diff --git a/drivers/gpu/drm/tegra/plane.c b/drivers/gpu/drm/tegra/plane.c
index 36a06a993698..94dac79ac3c9 100644
--- a/drivers/gpu/drm/tegra/plane.c
+++ b/drivers/gpu/drm/tegra/plane.c
@@ -297,6 +297,10 @@ int tegra_plane_format_get_alpha(unsigned int opaque, unsigned int *alpha)
         case WIN_COLOR_DEPTH_B8G8R8X8:
                 *alpha = WIN_COLOR_DEPTH_B8G8R8A8;
                 return 0;
+
+        case WIN_COLOR_DEPTH_B5G6R5:
+                *alpha = opaque;
+                return 0;
         }
 
         return -EINVAL;
@@ -330,9 +334,6 @@ void tegra_plane_check_dependent(struct tegra_plane *tegra,
         unsigned int zpos[2];
         unsigned int i;
 
-        for (i = 0; i < 3; i++)
-                state->dependent[i] = false;
-
         for (i = 0; i < 2; i++)
                 zpos[i] = 0;
 
@@ -346,6 +347,8 @@ void tegra_plane_check_dependent(struct tegra_plane *tegra,
 
                 index = tegra_plane_get_overlap_index(tegra, p);
 
+                state->dependent[index] = false;
+
                 /*
                  * If any of the other planes is on top of this plane and uses
                  * a format with an alpha component, mark this plane as being
diff --git a/drivers/gpu/drm/udl/udl_fb.c b/drivers/gpu/drm/udl/udl_fb.c
index b5b335c9b2bb..2ebdc6d5a76e 100644
--- a/drivers/gpu/drm/udl/udl_fb.c
+++ b/drivers/gpu/drm/udl/udl_fb.c
@@ -159,10 +159,15 @@ static int udl_fb_mmap(struct fb_info *info, struct vm_area_struct *vma)
 {
         unsigned long start = vma->vm_start;
         unsigned long size = vma->vm_end - vma->vm_start;
-        unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
+        unsigned long offset;
         unsigned long page, pos;
 
-        if (offset + size > info->fix.smem_len)
+        if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
+                return -EINVAL;
+
+        offset = vma->vm_pgoff << PAGE_SHIFT;
+
+        if (offset > info->fix.smem_len || size > info->fix.smem_len - offset)
                 return -EINVAL;
 
         pos = (unsigned long)info->fix.smem_start + offset;
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
index 184340d486c3..86d25f18aa99 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
@@ -1337,6 +1337,19 @@ static void __vmw_svga_disable(struct vmw_private *dev_priv)
  */
 void vmw_svga_disable(struct vmw_private *dev_priv)
 {
+        /*
+         * Disabling SVGA will turn off device modesetting capabilities, so
+         * notify KMS about that so that it doesn't cache atomic state that
+         * isn't valid anymore, for example crtcs turned on.
+         * Strictly we'd want to do this under the SVGA lock (or an SVGA mutex),
+         * but vmw_kms_lost_device() takes the reservation sem and thus we'll
+         * end up with lock order reversal. Thus, a master may actually perform
+         * a new modeset just after we call vmw_kms_lost_device() and race with
+         * vmw_svga_disable(), but that should at worst cause atomic KMS state
+         * to be inconsistent with the device, causing modesetting problems.
+         *
+         */
+        vmw_kms_lost_device(dev_priv->dev);
         ttm_write_lock(&dev_priv->reservation_sem, false);
         spin_lock(&dev_priv->svga_lock);
         if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
index d08753e8fd94..9116fe8baebc 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
@@ -938,6 +938,7 @@ int vmw_kms_present(struct vmw_private *dev_priv,
 int vmw_kms_update_layout_ioctl(struct drm_device *dev, void *data,
                                 struct drm_file *file_priv);
 void vmw_kms_legacy_hotspot_clear(struct vmw_private *dev_priv);
+void vmw_kms_lost_device(struct drm_device *dev);
 
 int vmw_dumb_create(struct drm_file *file_priv,
                     struct drm_device *dev,
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
index ead61015cd79..3c824fd7cbf3 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
@@ -31,7 +31,6 @@
 #include <drm/drm_atomic_helper.h>
 #include <drm/drm_rect.h>
 
-
 /* Might need a hrtimer here? */
 #define VMWGFX_PRESENT_RATE ((HZ / 60 > 0) ? HZ / 60 : 1)
 
@@ -2517,9 +2516,12 @@ void vmw_kms_helper_buffer_finish(struct vmw_private *dev_priv,
  * Helper to be used if an error forces the caller to undo the actions of
  * vmw_kms_helper_resource_prepare.
  */
-void vmw_kms_helper_resource_revert(struct vmw_resource *res)
+void vmw_kms_helper_resource_revert(struct vmw_validation_ctx *ctx)
 {
-        vmw_kms_helper_buffer_revert(res->backup);
+        struct vmw_resource *res = ctx->res;
+
+        vmw_kms_helper_buffer_revert(ctx->buf);
+        vmw_dmabuf_unreference(&ctx->buf);
         vmw_resource_unreserve(res, false, NULL, 0);
         mutex_unlock(&res->dev_priv->cmdbuf_mutex);
 }
@@ -2536,10 +2538,14 @@ void vmw_kms_helper_resource_revert(struct vmw_resource *res)
  * interrupted by a signal.
  */
 int vmw_kms_helper_resource_prepare(struct vmw_resource *res,
-                                    bool interruptible)
+                                    bool interruptible,
+                                    struct vmw_validation_ctx *ctx)
 {
         int ret = 0;
 
+        ctx->buf = NULL;
+        ctx->res = res;
+
         if (interruptible)
                 ret = mutex_lock_interruptible(&res->dev_priv->cmdbuf_mutex);
         else
@@ -2558,6 +2564,8 @@ int vmw_kms_helper_resource_prepare(struct vmw_resource *res,
                                                     res->dev_priv->has_mob);
                 if (ret)
                         goto out_unreserve;
+
+                ctx->buf = vmw_dmabuf_reference(res->backup);
         }
         ret = vmw_resource_validate(res);
         if (ret)
@@ -2565,7 +2573,7 @@ int vmw_kms_helper_resource_prepare(struct vmw_resource *res,
         return 0;
 
 out_revert:
-        vmw_kms_helper_buffer_revert(res->backup);
+        vmw_kms_helper_buffer_revert(ctx->buf);
 out_unreserve:
         vmw_resource_unreserve(res, false, NULL, 0);
 out_unlock:
@@ -2581,11 +2589,13 @@ out_unlock:
  * @out_fence: Optional pointer to a fence pointer. If non-NULL, a
  * ref-counted fence pointer is returned here.
  */
-void vmw_kms_helper_resource_finish(struct vmw_resource *res,
-                             struct vmw_fence_obj **out_fence)
+void vmw_kms_helper_resource_finish(struct vmw_validation_ctx *ctx,
+                                    struct vmw_fence_obj **out_fence)
 {
-        if (res->backup || out_fence)
-                vmw_kms_helper_buffer_finish(res->dev_priv, NULL, res->backup,
+        struct vmw_resource *res = ctx->res;
+
+        if (ctx->buf || out_fence)
+                vmw_kms_helper_buffer_finish(res->dev_priv, NULL, ctx->buf,
                                              out_fence, NULL);
 
         vmw_resource_unreserve(res, false, NULL, 0);
@@ -2851,3 +2861,14 @@ int vmw_kms_set_config(struct drm_mode_set *set,
 
         return drm_atomic_helper_set_config(set, ctx);
 }
+
+
+/**
+ * vmw_kms_lost_device - Notify kms that modesetting capabilities will be lost
+ *
+ * @dev: Pointer to the drm device
+ */
+void vmw_kms_lost_device(struct drm_device *dev)
+{
+        drm_atomic_helper_shutdown(dev);
+}
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.h b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.h
index cd9da2dd79af..3d2ca280eaa7 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.h
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.h
@@ -240,6 +240,11 @@ struct vmw_display_unit {
         int set_gui_y;
 };
 
+struct vmw_validation_ctx {
+        struct vmw_resource *res;
+        struct vmw_dma_buffer *buf;
+};
+
 #define vmw_crtc_to_du(x) \
         container_of(x, struct vmw_display_unit, crtc)
 #define vmw_connector_to_du(x) \
@@ -296,9 +301,10 @@ void vmw_kms_helper_buffer_finish(struct vmw_private *dev_priv,
                                   struct drm_vmw_fence_rep __user *
                                   user_fence_rep);
 int vmw_kms_helper_resource_prepare(struct vmw_resource *res,
-                                    bool interruptible);
-void vmw_kms_helper_resource_revert(struct vmw_resource *res);
-void vmw_kms_helper_resource_finish(struct vmw_resource *res,
+                                    bool interruptible,
+                                    struct vmw_validation_ctx *ctx);
+void vmw_kms_helper_resource_revert(struct vmw_validation_ctx *ctx);
+void vmw_kms_helper_resource_finish(struct vmw_validation_ctx *ctx,
                                     struct vmw_fence_obj **out_fence);
 int vmw_kms_readback(struct vmw_private *dev_priv,
                      struct drm_file *file_priv,
@@ -439,5 +445,4 @@ int vmw_kms_stdu_dma(struct vmw_private *dev_priv,
 
 int vmw_kms_set_config(struct drm_mode_set *set,
                        struct drm_modeset_acquire_ctx *ctx);
-
 #endif
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c b/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c
index 63a4cd794b73..3ec9eae831b8 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c
@@ -909,12 +909,13 @@ int vmw_kms_sou_do_surface_dirty(struct vmw_private *dev_priv,
         struct vmw_framebuffer_surface *vfbs =
                 container_of(framebuffer, typeof(*vfbs), base);
         struct vmw_kms_sou_surface_dirty sdirty;
+        struct vmw_validation_ctx ctx;
         int ret;
 
         if (!srf)
                 srf = &vfbs->surface->res;
 
-        ret = vmw_kms_helper_resource_prepare(srf, true);
+        ret = vmw_kms_helper_resource_prepare(srf, true, &ctx);
         if (ret)
                 return ret;
 
@@ -933,7 +934,7 @@ int vmw_kms_sou_do_surface_dirty(struct vmw_private *dev_priv,
         ret = vmw_kms_helper_dirty(dev_priv, framebuffer, clips, vclips,
                                    dest_x, dest_y, num_clips, inc,
                                    &sdirty.base);
-        vmw_kms_helper_resource_finish(srf, out_fence);
+        vmw_kms_helper_resource_finish(&ctx, out_fence);
 
         return ret;
 }
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c b/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
index b68d74888ab1..6b969e5dea2a 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
@@ -980,12 +980,13 @@ int vmw_kms_stdu_surface_dirty(struct vmw_private *dev_priv,
         struct vmw_framebuffer_surface *vfbs =
                 container_of(framebuffer, typeof(*vfbs), base);
         struct vmw_stdu_dirty sdirty;
+        struct vmw_validation_ctx ctx;
         int ret;
 
         if (!srf)
                 srf = &vfbs->surface->res;
 
-        ret = vmw_kms_helper_resource_prepare(srf, true);
+        ret = vmw_kms_helper_resource_prepare(srf, true, &ctx);
         if (ret)
                 return ret;
 
@@ -1008,7 +1009,7 @@ int vmw_kms_stdu_surface_dirty(struct vmw_private *dev_priv,
                                    dest_x, dest_y, num_clips, inc,
                                    &sdirty.base);
 out_finish:
-        vmw_kms_helper_resource_finish(srf, out_fence);
+        vmw_kms_helper_resource_finish(&ctx, out_fence);
 
         return ret;
 }
diff --git a/drivers/gpu/ipu-v3/ipu-prg.c b/drivers/gpu/ipu-v3/ipu-prg.c
index 97b99500153d..83f9dd934a5d 100644
--- a/drivers/gpu/ipu-v3/ipu-prg.c
+++ b/drivers/gpu/ipu-v3/ipu-prg.c
@@ -250,10 +250,14 @@ void ipu_prg_channel_disable(struct ipuv3_channel *ipu_chan)
 {
         int prg_chan = ipu_prg_ipu_to_prg_chan(ipu_chan->num);
         struct ipu_prg *prg = ipu_chan->ipu->prg_priv;
-        struct ipu_prg_channel *chan = &prg->chan[prg_chan];
+        struct ipu_prg_channel *chan;
         u32 val;
 
-        if (!chan->enabled || prg_chan < 0)
+        if (prg_chan < 0)
+                return;
+
+        chan = &prg->chan[prg_chan];
+        if (!chan->enabled)
                 return;
 
         pm_runtime_get_sync(prg->dev);
@@ -280,13 +284,15 @@ int ipu_prg_channel_configure(struct ipuv3_channel *ipu_chan,
 {
         int prg_chan = ipu_prg_ipu_to_prg_chan(ipu_chan->num);
         struct ipu_prg *prg = ipu_chan->ipu->prg_priv;
-        struct ipu_prg_channel *chan = &prg->chan[prg_chan];
+        struct ipu_prg_channel *chan;
         u32 val;
         int ret;
 
         if (prg_chan < 0)
                 return prg_chan;
 
+        chan = &prg->chan[prg_chan];
+
         if (chan->enabled) {
                 ipu_pre_update(prg->pres[chan->used_pre], *eba);
                 return 0;