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authorDave Airlie <airlied@redhat.com>2016-07-15 21:23:50 -0400
committerDave Airlie <airlied@redhat.com>2016-07-15 21:23:50 -0400
commit877fa9a42ddc087dc46a3a3aac18db8adde2bdf1 (patch)
treec5189830c8d3fed08e92deda8681f0676aaea8a5 /drivers/gpu/host1x/hw/channel_hw.c
parente2b80bac213cdfd443df9b6e1c769f98d0553c0c (diff)
parent64ea25c3bc86c05c7da6c683b86663f4c90158d6 (diff)
Merge tag 'drm/tegra/for-4.8-rc1' of git://anongit.freedesktop.org/tegra/linux into drm-next
drm/tegra: Changes for v4.8-rc1 This set of changes contains a bunch of cleanups to the host1x driver as well as the addition of a pin controller for DPAUX, which is required by boards to configure the DPAUX pads in AUX mode (for DisplayPort) or I2C mode (for HDMI and DDC). Included is also a bit of rework of the SOR driver in preparation to add DisplayPort support as well as some refactoring and cleanup. Finally, all output drivers are converted to runtime PM, which greatly simplifies the handling of clocks and resets. * tag 'drm/tegra/for-4.8-rc1' of git://anongit.freedesktop.org/tegra/linux: (35 commits) drm/tegra: sor: Reject HDMI 2.0 modes drm/tegra: sor: Prepare for generic PM domain support drm/tegra: dsi: Prepare for generic PM domain support drm/tegra: sor: Make XBAR configurable per SoC drm/tegra: sor: Use sor1_src clock to set parent for HDMI dt-bindings: display: tegra: Add source clock for SOR drm/tegra: sor: Implement sor1_brick clock drm/tegra: sor: Implement runtime PM drm/tegra: hdmi: Implement runtime PM drm/tegra: dsi: Implement runtime PM drm/tegra: dc: Implement runtime PM drm/tegra: hdmi: Enable audio over HDMI drm/tegra: sor: Do not support deep color modes drm/tegra: sor: Extract tegra_sor_mode_set() drm/tegra: sor: Split out tegra_sor_apply_config() drm/tegra: sor: Rename tegra_sor_calc_config() drm/tegra: sor: Factor out tegra_sor_set_parent_clock() drm/tegra: dpaux: Add pinctrl support dt-bindings: Add bindings for Tegra DPAUX pinctrl driver drm/tegra: Prepare DPAUX for supporting generic PM domains ...
Diffstat (limited to 'drivers/gpu/host1x/hw/channel_hw.c')
-rw-r--r--drivers/gpu/host1x/hw/channel_hw.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/gpu/host1x/hw/channel_hw.c b/drivers/gpu/host1x/hw/channel_hw.c
index 946c332c3906..5e8df78b7acd 100644
--- a/drivers/gpu/host1x/hw/channel_hw.c
+++ b/drivers/gpu/host1x/hw/channel_hw.c
@@ -46,6 +46,7 @@ static void trace_write_gather(struct host1x_cdma *cdma, struct host1x_bo *bo,
46 */ 46 */
47 for (i = 0; i < words; i += TRACE_MAX_LENGTH) { 47 for (i = 0; i < words; i += TRACE_MAX_LENGTH) {
48 u32 num_words = min(words - i, TRACE_MAX_LENGTH); 48 u32 num_words = min(words - i, TRACE_MAX_LENGTH);
49
49 offset += i * sizeof(u32); 50 offset += i * sizeof(u32);
50 51
51 trace_host1x_cdma_push_gather(dev_name(dev), bo, 52 trace_host1x_cdma_push_gather(dev_name(dev), bo,
@@ -66,6 +67,7 @@ static void submit_gathers(struct host1x_job *job)
66 struct host1x_job_gather *g = &job->gathers[i]; 67 struct host1x_job_gather *g = &job->gathers[i];
67 u32 op1 = host1x_opcode_gather(g->words); 68 u32 op1 = host1x_opcode_gather(g->words);
68 u32 op2 = g->base + g->offset; 69 u32 op2 = g->base + g->offset;
70
69 trace_write_gather(cdma, g->bo, g->offset, op1 & 0xffff); 71 trace_write_gather(cdma, g->bo, g->offset, op1 & 0xffff);
70 host1x_cdma_push(cdma, op1, op2); 72 host1x_cdma_push(cdma, op1, op2);
71 } 73 }
@@ -75,7 +77,8 @@ static inline void synchronize_syncpt_base(struct host1x_job *job)
75{ 77{
76 struct host1x *host = dev_get_drvdata(job->channel->dev->parent); 78 struct host1x *host = dev_get_drvdata(job->channel->dev->parent);
77 struct host1x_syncpt *sp = host->syncpt + job->syncpt_id; 79 struct host1x_syncpt *sp = host->syncpt + job->syncpt_id;
78 u32 id, value; 80 unsigned int id;
81 u32 value;
79 82
80 value = host1x_syncpt_read_max(sp); 83 value = host1x_syncpt_read_max(sp);
81 id = sp->base->id; 84 id = sp->base->id;