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authorDave Airlie <airlied@redhat.com>2016-07-15 21:23:50 -0400
committerDave Airlie <airlied@redhat.com>2016-07-15 21:23:50 -0400
commit877fa9a42ddc087dc46a3a3aac18db8adde2bdf1 (patch)
treec5189830c8d3fed08e92deda8681f0676aaea8a5 /drivers/gpu/host1x/dev.h
parente2b80bac213cdfd443df9b6e1c769f98d0553c0c (diff)
parent64ea25c3bc86c05c7da6c683b86663f4c90158d6 (diff)
Merge tag 'drm/tegra/for-4.8-rc1' of git://anongit.freedesktop.org/tegra/linux into drm-next
drm/tegra: Changes for v4.8-rc1 This set of changes contains a bunch of cleanups to the host1x driver as well as the addition of a pin controller for DPAUX, which is required by boards to configure the DPAUX pads in AUX mode (for DisplayPort) or I2C mode (for HDMI and DDC). Included is also a bit of rework of the SOR driver in preparation to add DisplayPort support as well as some refactoring and cleanup. Finally, all output drivers are converted to runtime PM, which greatly simplifies the handling of clocks and resets. * tag 'drm/tegra/for-4.8-rc1' of git://anongit.freedesktop.org/tegra/linux: (35 commits) drm/tegra: sor: Reject HDMI 2.0 modes drm/tegra: sor: Prepare for generic PM domain support drm/tegra: dsi: Prepare for generic PM domain support drm/tegra: sor: Make XBAR configurable per SoC drm/tegra: sor: Use sor1_src clock to set parent for HDMI dt-bindings: display: tegra: Add source clock for SOR drm/tegra: sor: Implement sor1_brick clock drm/tegra: sor: Implement runtime PM drm/tegra: hdmi: Implement runtime PM drm/tegra: dsi: Implement runtime PM drm/tegra: dc: Implement runtime PM drm/tegra: hdmi: Enable audio over HDMI drm/tegra: sor: Do not support deep color modes drm/tegra: sor: Extract tegra_sor_mode_set() drm/tegra: sor: Split out tegra_sor_apply_config() drm/tegra: sor: Rename tegra_sor_calc_config() drm/tegra: sor: Factor out tegra_sor_set_parent_clock() drm/tegra: dpaux: Add pinctrl support dt-bindings: Add bindings for Tegra DPAUX pinctrl driver drm/tegra: Prepare DPAUX for supporting generic PM domains ...
Diffstat (limited to 'drivers/gpu/host1x/dev.h')
-rw-r--r--drivers/gpu/host1x/dev.h38
1 files changed, 19 insertions, 19 deletions
diff --git a/drivers/gpu/host1x/dev.h b/drivers/gpu/host1x/dev.h
index dace124994bb..5220510f39da 100644
--- a/drivers/gpu/host1x/dev.h
+++ b/drivers/gpu/host1x/dev.h
@@ -45,7 +45,7 @@ struct host1x_cdma_ops {
45 void (*start)(struct host1x_cdma *cdma); 45 void (*start)(struct host1x_cdma *cdma);
46 void (*stop)(struct host1x_cdma *cdma); 46 void (*stop)(struct host1x_cdma *cdma);
47 void (*flush)(struct host1x_cdma *cdma); 47 void (*flush)(struct host1x_cdma *cdma);
48 int (*timeout_init)(struct host1x_cdma *cdma, u32 syncpt_id); 48 int (*timeout_init)(struct host1x_cdma *cdma, unsigned int syncpt);
49 void (*timeout_destroy)(struct host1x_cdma *cdma); 49 void (*timeout_destroy)(struct host1x_cdma *cdma);
50 void (*freeze)(struct host1x_cdma *cdma); 50 void (*freeze)(struct host1x_cdma *cdma);
51 void (*resume)(struct host1x_cdma *cdma, u32 getptr); 51 void (*resume)(struct host1x_cdma *cdma, u32 getptr);
@@ -82,21 +82,21 @@ struct host1x_intr_ops {
82 int (*init_host_sync)(struct host1x *host, u32 cpm, 82 int (*init_host_sync)(struct host1x *host, u32 cpm,
83 void (*syncpt_thresh_work)(struct work_struct *work)); 83 void (*syncpt_thresh_work)(struct work_struct *work));
84 void (*set_syncpt_threshold)( 84 void (*set_syncpt_threshold)(
85 struct host1x *host, u32 id, u32 thresh); 85 struct host1x *host, unsigned int id, u32 thresh);
86 void (*enable_syncpt_intr)(struct host1x *host, u32 id); 86 void (*enable_syncpt_intr)(struct host1x *host, unsigned int id);
87 void (*disable_syncpt_intr)(struct host1x *host, u32 id); 87 void (*disable_syncpt_intr)(struct host1x *host, unsigned int id);
88 void (*disable_all_syncpt_intrs)(struct host1x *host); 88 void (*disable_all_syncpt_intrs)(struct host1x *host);
89 int (*free_syncpt_irq)(struct host1x *host); 89 int (*free_syncpt_irq)(struct host1x *host);
90}; 90};
91 91
92struct host1x_info { 92struct host1x_info {
93 int nb_channels; /* host1x: num channels supported */ 93 unsigned int nb_channels; /* host1x: number of channels supported */
94 int nb_pts; /* host1x: num syncpoints supported */ 94 unsigned int nb_pts; /* host1x: number of syncpoints supported */
95 int nb_bases; /* host1x: num syncpoints supported */ 95 unsigned int nb_bases; /* host1x: number of syncpoint bases supported */
96 int nb_mlocks; /* host1x: number of mlocks */ 96 unsigned int nb_mlocks; /* host1x: number of mlocks supported */
97 int (*init)(struct host1x *); /* initialize per SoC ops */ 97 int (*init)(struct host1x *host1x); /* initialize per SoC ops */
98 int sync_offset; 98 unsigned int sync_offset; /* offset of syncpoint registers */
99 u64 dma_mask; /* mask of addressable memory */ 99 u64 dma_mask; /* mask of addressable memory */
100}; 100};
101 101
102struct host1x { 102struct host1x {
@@ -109,7 +109,6 @@ struct host1x {
109 struct clk *clk; 109 struct clk *clk;
110 110
111 struct mutex intr_mutex; 111 struct mutex intr_mutex;
112 struct workqueue_struct *intr_wq;
113 int intr_syncpt_irq; 112 int intr_syncpt_irq;
114 113
115 const struct host1x_syncpt_ops *syncpt_op; 114 const struct host1x_syncpt_ops *syncpt_op;
@@ -183,19 +182,20 @@ static inline int host1x_hw_intr_init_host_sync(struct host1x *host, u32 cpm,
183} 182}
184 183
185static inline void host1x_hw_intr_set_syncpt_threshold(struct host1x *host, 184static inline void host1x_hw_intr_set_syncpt_threshold(struct host1x *host,
186 u32 id, u32 thresh) 185 unsigned int id,
186 u32 thresh)
187{ 187{
188 host->intr_op->set_syncpt_threshold(host, id, thresh); 188 host->intr_op->set_syncpt_threshold(host, id, thresh);
189} 189}
190 190
191static inline void host1x_hw_intr_enable_syncpt_intr(struct host1x *host, 191static inline void host1x_hw_intr_enable_syncpt_intr(struct host1x *host,
192 u32 id) 192 unsigned int id)
193{ 193{
194 host->intr_op->enable_syncpt_intr(host, id); 194 host->intr_op->enable_syncpt_intr(host, id);
195} 195}
196 196
197static inline void host1x_hw_intr_disable_syncpt_intr(struct host1x *host, 197static inline void host1x_hw_intr_disable_syncpt_intr(struct host1x *host,
198 u32 id) 198 unsigned int id)
199{ 199{
200 host->intr_op->disable_syncpt_intr(host, id); 200 host->intr_op->disable_syncpt_intr(host, id);
201} 201}
@@ -212,9 +212,9 @@ static inline int host1x_hw_intr_free_syncpt_irq(struct host1x *host)
212 212
213static inline int host1x_hw_channel_init(struct host1x *host, 213static inline int host1x_hw_channel_init(struct host1x *host,
214 struct host1x_channel *channel, 214 struct host1x_channel *channel,
215 int chid) 215 unsigned int id)
216{ 216{
217 return host->channel_op->init(channel, host, chid); 217 return host->channel_op->init(channel, host, id);
218} 218}
219 219
220static inline int host1x_hw_channel_submit(struct host1x *host, 220static inline int host1x_hw_channel_submit(struct host1x *host,
@@ -243,9 +243,9 @@ static inline void host1x_hw_cdma_flush(struct host1x *host,
243 243
244static inline int host1x_hw_cdma_timeout_init(struct host1x *host, 244static inline int host1x_hw_cdma_timeout_init(struct host1x *host,
245 struct host1x_cdma *cdma, 245 struct host1x_cdma *cdma,
246 u32 syncpt_id) 246 unsigned int syncpt)
247{ 247{
248 return host->cdma_op->timeout_init(cdma, syncpt_id); 248 return host->cdma_op->timeout_init(cdma, syncpt);
249} 249}
250 250
251static inline void host1x_hw_cdma_timeout_destroy(struct host1x *host, 251static inline void host1x_hw_cdma_timeout_destroy(struct host1x *host,