aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm
diff options
context:
space:
mode:
authorDeepak Rawat <drawat@vmware.com>2018-06-13 16:53:28 -0400
committerThomas Hellstrom <thellstrom@vmware.com>2018-07-04 03:42:49 -0400
commitdc75e733308c3673d88664fe5e6b9478fa6bec4d (patch)
tree81ffc2be2073917502d94589a2f3780a3fb95c76 /drivers/gpu/drm
parent812a954b787ab5a91d62e597a36351628b08d079 (diff)
drm/vmwgfx: Update the device headers
This change updates the device headers to the latest device version. Where renaming affects the existing code, it's updated accordingly. Signed-off-by: Deepak Rawat <drawat@vmware.com> Reviewed-by: Sinclair Yeh <syeh@vmware.com> Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com> Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/vmwgfx/device_include/svga3d_cmd.h230
-rw-r--r--drivers/gpu/drm/vmwgfx/device_include/svga3d_devcaps.h83
-rw-r--r--drivers/gpu/drm/vmwgfx/device_include/svga3d_dx.h297
-rw-r--r--drivers/gpu/drm/vmwgfx/device_include/svga3d_limits.h4
-rw-r--r--drivers/gpu/drm/vmwgfx/device_include/svga3d_surfacedefs.h1070
-rw-r--r--drivers/gpu/drm/vmwgfx/device_include/svga3d_types.h331
-rw-r--r--drivers/gpu/drm/vmwgfx/device_include/svga_reg.h177
-rw-r--r--drivers/gpu/drm/vmwgfx/device_include/svga_types.h3
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_drv.c2
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c4
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c15
11 files changed, 1438 insertions, 778 deletions
diff --git a/drivers/gpu/drm/vmwgfx/device_include/svga3d_cmd.h b/drivers/gpu/drm/vmwgfx/device_include/svga3d_cmd.h
index 2dfd57c5f463..168bbf8373a5 100644
--- a/drivers/gpu/drm/vmwgfx/device_include/svga3d_cmd.h
+++ b/drivers/gpu/drm/vmwgfx/device_include/svga3d_cmd.h
@@ -46,10 +46,10 @@
46 * the SVGA3D protocol and remain reserved; they should not be used in the 46 * the SVGA3D protocol and remain reserved; they should not be used in the
47 * future. 47 * future.
48 * 48 *
49 * IDs between 1040 and 1999 (inclusive) are available for use by the 49 * IDs between 1040 and 2999 (inclusive) are available for use by the
50 * current SVGA3D protocol. 50 * current SVGA3D protocol.
51 * 51 *
52 * FIFO clients other than SVGA3D should stay below 1000, or at 2000 52 * FIFO clients other than SVGA3D should stay below 1000, or at 3000
53 * and up. 53 * and up.
54 */ 54 */
55 55
@@ -89,19 +89,19 @@ typedef enum {
89 SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN = 1069, 89 SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN = 1069,
90 SVGA_3D_CMD_SURFACE_DEFINE_V2 = 1070, 90 SVGA_3D_CMD_SURFACE_DEFINE_V2 = 1070,
91 SVGA_3D_CMD_GENERATE_MIPMAPS = 1071, 91 SVGA_3D_CMD_GENERATE_MIPMAPS = 1071,
92 SVGA_3D_CMD_VIDEO_CREATE_DECODER = 1072, 92 SVGA_3D_CMD_DEAD4 = 1072,
93 SVGA_3D_CMD_VIDEO_DESTROY_DECODER = 1073, 93 SVGA_3D_CMD_DEAD5 = 1073,
94 SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR = 1074, 94 SVGA_3D_CMD_DEAD6 = 1074,
95 SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR = 1075, 95 SVGA_3D_CMD_DEAD7 = 1075,
96 SVGA_3D_CMD_VIDEO_DECODE_START_FRAME = 1076, 96 SVGA_3D_CMD_DEAD8 = 1076,
97 SVGA_3D_CMD_VIDEO_DECODE_RENDER = 1077, 97 SVGA_3D_CMD_DEAD9 = 1077,
98 SVGA_3D_CMD_VIDEO_DECODE_END_FRAME = 1078, 98 SVGA_3D_CMD_DEAD10 = 1078,
99 SVGA_3D_CMD_VIDEO_PROCESS_FRAME = 1079, 99 SVGA_3D_CMD_DEAD11 = 1079,
100 SVGA_3D_CMD_ACTIVATE_SURFACE = 1080, 100 SVGA_3D_CMD_ACTIVATE_SURFACE = 1080,
101 SVGA_3D_CMD_DEACTIVATE_SURFACE = 1081, 101 SVGA_3D_CMD_DEACTIVATE_SURFACE = 1081,
102 SVGA_3D_CMD_SCREEN_DMA = 1082, 102 SVGA_3D_CMD_SCREEN_DMA = 1082,
103 SVGA_3D_CMD_SET_UNITY_SURFACE_COOKIE = 1083, 103 SVGA_3D_CMD_DEAD1 = 1083,
104 SVGA_3D_CMD_OPEN_CONTEXT_SURFACE = 1084, 104 SVGA_3D_CMD_DEAD2 = 1084,
105 105
106 SVGA_3D_CMD_LOGICOPS_BITBLT = 1085, 106 SVGA_3D_CMD_LOGICOPS_BITBLT = 1085,
107 SVGA_3D_CMD_LOGICOPS_TRANSBLT = 1086, 107 SVGA_3D_CMD_LOGICOPS_TRANSBLT = 1086,
@@ -217,7 +217,7 @@ typedef enum {
217 SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW = 1177, 217 SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW = 1177,
218 SVGA_3D_CMD_DX_PRED_COPY_REGION = 1178, 218 SVGA_3D_CMD_DX_PRED_COPY_REGION = 1178,
219 SVGA_3D_CMD_DX_PRED_COPY = 1179, 219 SVGA_3D_CMD_DX_PRED_COPY = 1179,
220 SVGA_3D_CMD_DX_STRETCHBLT = 1180, 220 SVGA_3D_CMD_DX_PRESENTBLT = 1180,
221 SVGA_3D_CMD_DX_GENMIPS = 1181, 221 SVGA_3D_CMD_DX_GENMIPS = 1181,
222 SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE = 1182, 222 SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE = 1182,
223 SVGA_3D_CMD_DX_READBACK_SUBRESOURCE = 1183, 223 SVGA_3D_CMD_DX_READBACK_SUBRESOURCE = 1183,
@@ -254,7 +254,7 @@ typedef enum {
254 SVGA_3D_CMD_DX_READBACK_ALL_QUERY = 1214, 254 SVGA_3D_CMD_DX_READBACK_ALL_QUERY = 1214,
255 SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER = 1215, 255 SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER = 1215,
256 SVGA_3D_CMD_DX_MOB_FENCE_64 = 1216, 256 SVGA_3D_CMD_DX_MOB_FENCE_64 = 1216,
257 SVGA_3D_CMD_DX_BIND_SHADER_ON_CONTEXT = 1217, 257 SVGA_3D_CMD_DX_BIND_ALL_SHADER = 1217,
258 SVGA_3D_CMD_DX_HINT = 1218, 258 SVGA_3D_CMD_DX_HINT = 1218,
259 SVGA_3D_CMD_DX_BUFFER_UPDATE = 1219, 259 SVGA_3D_CMD_DX_BUFFER_UPDATE = 1219,
260 SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET = 1220, 260 SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET = 1220,
@@ -262,17 +262,47 @@ typedef enum {
262 SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET = 1222, 262 SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET = 1222,
263 263
264 /* 264 /*
265 * Reserve some IDs to be used for the DX11 shader types. 265 * Reserve some IDs to be used for the SM5 shader types.
266 */ 266 */
267 SVGA_3D_CMD_DX_RESERVED1 = 1223, 267 SVGA_3D_CMD_DX_RESERVED1 = 1223,
268 SVGA_3D_CMD_DX_RESERVED2 = 1224, 268 SVGA_3D_CMD_DX_RESERVED2 = 1224,
269 SVGA_3D_CMD_DX_RESERVED3 = 1225, 269 SVGA_3D_CMD_DX_RESERVED3 = 1225,
270 270
271 SVGA_3D_CMD_DX_MAX = 1226, 271 SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER = 1226,
272 SVGA_3D_CMD_MAX = 1226, 272 SVGA_3D_CMD_DX_MAX = 1227,
273
274 SVGA_3D_CMD_SCREEN_COPY = 1227,
275
276 /*
277 * Reserve some IDs to be used for video.
278 */
279 SVGA_3D_CMD_VIDEO_RESERVED1 = 1228,
280 SVGA_3D_CMD_VIDEO_RESERVED2 = 1229,
281 SVGA_3D_CMD_VIDEO_RESERVED3 = 1230,
282 SVGA_3D_CMD_VIDEO_RESERVED4 = 1231,
283 SVGA_3D_CMD_VIDEO_RESERVED5 = 1232,
284 SVGA_3D_CMD_VIDEO_RESERVED6 = 1233,
285 SVGA_3D_CMD_VIDEO_RESERVED7 = 1234,
286 SVGA_3D_CMD_VIDEO_RESERVED8 = 1235,
287
288 SVGA_3D_CMD_GROW_OTABLE = 1236,
289 SVGA_3D_CMD_DX_GROW_COTABLE = 1237,
290 SVGA_3D_CMD_INTRA_SURFACE_COPY = 1238,
291
292 SVGA_3D_CMD_DEFINE_GB_SURFACE_V3 = 1239,
293
294 SVGA_3D_CMD_DX_RESOLVE_COPY = 1240,
295 SVGA_3D_CMD_DX_PRED_RESOLVE_COPY = 1241,
296 SVGA_3D_CMD_DX_PRED_CONVERT_REGION = 1242,
297 SVGA_3D_CMD_DX_PRED_CONVERT = 1243,
298 SVGA_3D_CMD_WHOLE_SURFACE_COPY = 1244,
299
300 SVGA_3D_CMD_MAX = 1245,
273 SVGA_3D_CMD_FUTURE_MAX = 3000 301 SVGA_3D_CMD_FUTURE_MAX = 3000
274} SVGAFifo3dCmdId; 302} SVGAFifo3dCmdId;
275 303
304#define SVGA_NUM_3D_CMD (SVGA_3D_CMD_MAX - SVGA_3D_CMD_BASE)
305
276/* 306/*
277 * FIFO command format definitions: 307 * FIFO command format definitions:
278 */ 308 */
@@ -301,7 +331,7 @@ typedef
301#include "vmware_pack_begin.h" 331#include "vmware_pack_begin.h"
302struct { 332struct {
303 uint32 sid; 333 uint32 sid;
304 SVGA3dSurfaceFlags surfaceFlags; 334 SVGA3dSurface1Flags surfaceFlags;
305 SVGA3dSurfaceFormat format; 335 SVGA3dSurfaceFormat format;
306 /* 336 /*
307 * If surfaceFlags has SVGA3D_SURFACE_CUBEMAP bit set, all SVGA3dSurfaceFace 337 * If surfaceFlags has SVGA3D_SURFACE_CUBEMAP bit set, all SVGA3dSurfaceFace
@@ -327,7 +357,7 @@ typedef
327#include "vmware_pack_begin.h" 357#include "vmware_pack_begin.h"
328struct { 358struct {
329 uint32 sid; 359 uint32 sid;
330 SVGA3dSurfaceFlags surfaceFlags; 360 SVGA3dSurface1Flags surfaceFlags;
331 SVGA3dSurfaceFormat format; 361 SVGA3dSurfaceFormat format;
332 /* 362 /*
333 * If surfaceFlags has SVGA3D_SURFACE_CUBEMAP bit set, all SVGA3dSurfaceFace 363 * If surfaceFlags has SVGA3D_SURFACE_CUBEMAP bit set, all SVGA3dSurfaceFace
@@ -459,6 +489,28 @@ struct {
459#include "vmware_pack_end.h" 489#include "vmware_pack_end.h"
460SVGA3dCmdSurfaceCopy; /* SVGA_3D_CMD_SURFACE_COPY */ 490SVGA3dCmdSurfaceCopy; /* SVGA_3D_CMD_SURFACE_COPY */
461 491
492/*
493 * Perform a surface copy within the same image.
494 * The src/dest boxes are allowed to overlap.
495 */
496typedef
497#include "vmware_pack_begin.h"
498struct {
499 SVGA3dSurfaceImageId surface;
500 SVGA3dCopyBox box;
501}
502#include "vmware_pack_end.h"
503SVGA3dCmdIntraSurfaceCopy; /* SVGA_3D_CMD_INTRA_SURFACE_COPY */
504
505typedef
506#include "vmware_pack_begin.h"
507struct {
508 uint32 srcSid;
509 uint32 destSid;
510}
511#include "vmware_pack_end.h"
512SVGA3dCmdWholeSurfaceCopy; /* SVGA_3D_CMD_WHOLE_SURFACE_COPY */
513
462typedef 514typedef
463#include "vmware_pack_begin.h" 515#include "vmware_pack_begin.h"
464struct { 516struct {
@@ -772,6 +824,17 @@ struct {
772#include "vmware_pack_end.h" 824#include "vmware_pack_end.h"
773SVGA3dVertexElement; 825SVGA3dVertexElement;
774 826
827/*
828 * Should the vertex element respect the stream value? The high bit of the
829 * stream should be set to indicate that the stream should be respected. If
830 * the high bit is not set, the stream will be ignored and replaced by the index
831 * of the position of the currently considered vertex element.
832 *
833 * All guests should set this bit and correctly specify the stream going
834 * forward.
835 */
836#define SVGA3D_VERTEX_ELEMENT_RESPECT_STREAM (1 << 7)
837
775typedef 838typedef
776#include "vmware_pack_begin.h" 839#include "vmware_pack_begin.h"
777struct { 840struct {
@@ -1102,8 +1165,6 @@ struct {
1102#include "vmware_pack_end.h" 1165#include "vmware_pack_end.h"
1103SVGA3dCmdGenerateMipmaps; /* SVGA_3D_CMD_GENERATE_MIPMAPS */ 1166SVGA3dCmdGenerateMipmaps; /* SVGA_3D_CMD_GENERATE_MIPMAPS */
1104 1167
1105
1106
1107typedef 1168typedef
1108#include "vmware_pack_begin.h" 1169#include "vmware_pack_begin.h"
1109struct { 1170struct {
@@ -1147,38 +1208,6 @@ struct SVGA3dCmdScreenDMA {
1147SVGA3dCmdScreenDMA; /* SVGA_3D_CMD_SCREEN_DMA */ 1208SVGA3dCmdScreenDMA; /* SVGA_3D_CMD_SCREEN_DMA */
1148 1209
1149/* 1210/*
1150 * Set Unity Surface Cookie
1151 *
1152 * Associates the supplied cookie with the surface id for use with
1153 * Unity. This cookie is a hint from guest to host, there is no way
1154 * for the guest to readback the cookie and the host is free to drop
1155 * the cookie association at will. The default value for the cookie
1156 * on all surfaces is 0.
1157 */
1158
1159typedef
1160#include "vmware_pack_begin.h"
1161struct SVGA3dCmdSetUnitySurfaceCookie {
1162 uint32 sid;
1163 uint64 cookie;
1164}
1165#include "vmware_pack_end.h"
1166SVGA3dCmdSetUnitySurfaceCookie; /* SVGA_3D_CMD_SET_UNITY_SURFACE_COOKIE */
1167
1168/*
1169 * Open a context-specific surface in a non-context-specific manner.
1170 */
1171
1172typedef
1173#include "vmware_pack_begin.h"
1174struct SVGA3dCmdOpenContextSurface {
1175 uint32 sid;
1176}
1177#include "vmware_pack_end.h"
1178SVGA3dCmdOpenContextSurface; /* SVGA_3D_CMD_OPEN_CONTEXT_SURFACE */
1179
1180
1181/*
1182 * Logic ops 1211 * Logic ops
1183 */ 1212 */
1184 1213
@@ -1324,7 +1353,7 @@ typedef
1324#include "vmware_pack_begin.h" 1353#include "vmware_pack_begin.h"
1325struct { 1354struct {
1326 SVGA3dSurfaceFormat format; 1355 SVGA3dSurfaceFormat format;
1327 SVGA3dSurfaceFlags surfaceFlags; 1356 SVGA3dSurface1Flags surface1Flags;
1328 uint32 numMipLevels; 1357 uint32 numMipLevels;
1329 uint32 multisampleCount; 1358 uint32 multisampleCount;
1330 SVGA3dTextureFilter autogenFilter; 1359 SVGA3dTextureFilter autogenFilter;
@@ -1332,7 +1361,11 @@ struct {
1332 SVGAMobId mobid; 1361 SVGAMobId mobid;
1333 uint32 arraySize; 1362 uint32 arraySize;
1334 uint32 mobPitch; 1363 uint32 mobPitch;
1335 uint32 pad[5]; 1364 SVGA3dSurface2Flags surface2Flags;
1365 uint8 multisamplePattern;
1366 uint8 qualityLevel;
1367 uint8 pad0[2];
1368 uint32 pad1[3];
1336} 1369}
1337#include "vmware_pack_end.h" 1370#include "vmware_pack_end.h"
1338SVGAOTableSurfaceEntry; 1371SVGAOTableSurfaceEntry;
@@ -1360,7 +1393,8 @@ struct {
1360SVGAOTableShaderEntry; 1393SVGAOTableShaderEntry;
1361#define SVGA3D_OTABLE_SHADER_ENTRY_SIZE (sizeof(SVGAOTableShaderEntry)) 1394#define SVGA3D_OTABLE_SHADER_ENTRY_SIZE (sizeof(SVGAOTableShaderEntry))
1362 1395
1363#define SVGA_STFLAG_PRIMARY (1 << 0) 1396#define SVGA_STFLAG_PRIMARY (1 << 0)
1397#define SVGA_STFLAG_RESERVED (1 << 1) /* Added with cap SVGA_CAP_HP_CMD_QUEUE */
1364typedef uint32 SVGAScreenTargetFlags; 1398typedef uint32 SVGAScreenTargetFlags;
1365 1399
1366typedef 1400typedef
@@ -1528,6 +1562,25 @@ struct {
1528#include "vmware_pack_end.h" 1562#include "vmware_pack_end.h"
1529SVGA3dCmdSetOTableBase64; /* SVGA_3D_CMD_SET_OTABLE_BASE64 */ 1563SVGA3dCmdSetOTableBase64; /* SVGA_3D_CMD_SET_OTABLE_BASE64 */
1530 1564
1565/*
1566 * Guests using SVGA_3D_CMD_GROW_OTABLE are promising that
1567 * the new OTable contains the same contents as the old one, except possibly
1568 * for some new invalid entries at the end.
1569 *
1570 * (Otherwise, guests should use one of the SetOTableBase commands.)
1571 */
1572typedef
1573#include "vmware_pack_begin.h"
1574struct {
1575 SVGAOTableType type;
1576 PPN64 baseAddress;
1577 uint32 sizeInBytes;
1578 uint32 validSizeInBytes;
1579 SVGAMobFormat ptDepth;
1580}
1581#include "vmware_pack_end.h"
1582SVGA3dCmdGrowOTable; /* SVGA_3D_CMD_GROW_OTABLE */
1583
1531typedef 1584typedef
1532#include "vmware_pack_begin.h" 1585#include "vmware_pack_begin.h"
1533struct { 1586struct {
@@ -1615,7 +1668,7 @@ typedef
1615#include "vmware_pack_begin.h" 1668#include "vmware_pack_begin.h"
1616struct SVGA3dCmdDefineGBSurface { 1669struct SVGA3dCmdDefineGBSurface {
1617 uint32 sid; 1670 uint32 sid;
1618 SVGA3dSurfaceFlags surfaceFlags; 1671 SVGA3dSurface1Flags surfaceFlags;
1619 SVGA3dSurfaceFormat format; 1672 SVGA3dSurfaceFormat format;
1620 uint32 numMipLevels; 1673 uint32 numMipLevels;
1621 uint32 multisampleCount; 1674 uint32 multisampleCount;
@@ -1626,6 +1679,45 @@ struct SVGA3dCmdDefineGBSurface {
1626SVGA3dCmdDefineGBSurface; /* SVGA_3D_CMD_DEFINE_GB_SURFACE */ 1679SVGA3dCmdDefineGBSurface; /* SVGA_3D_CMD_DEFINE_GB_SURFACE */
1627 1680
1628/* 1681/*
1682 * Defines a guest-backed surface, adding the arraySize field.
1683 */
1684typedef
1685#include "vmware_pack_begin.h"
1686struct SVGA3dCmdDefineGBSurface_v2 {
1687 uint32 sid;
1688 SVGA3dSurface1Flags surfaceFlags;
1689 SVGA3dSurfaceFormat format;
1690 uint32 numMipLevels;
1691 uint32 multisampleCount;
1692 SVGA3dTextureFilter autogenFilter;
1693 SVGA3dSize size;
1694 uint32 arraySize;
1695 uint32 pad;
1696}
1697#include "vmware_pack_end.h"
1698SVGA3dCmdDefineGBSurface_v2; /* SVGA_3D_CMD_DEFINE_GB_SURFACE_V2 */
1699
1700/*
1701 * Defines a guest-backed surface, adding the larger flags.
1702 */
1703typedef
1704#include "vmware_pack_begin.h"
1705struct SVGA3dCmdDefineGBSurface_v3 {
1706 uint32 sid;
1707 SVGA3dSurfaceAllFlags surfaceFlags;
1708 SVGA3dSurfaceFormat format;
1709 uint32 numMipLevels;
1710 uint32 multisampleCount;
1711 SVGA3dMSPattern multisamplePattern;
1712 SVGA3dMSQualityLevel qualityLevel;
1713 SVGA3dTextureFilter autogenFilter;
1714 SVGA3dSize size;
1715 uint32 arraySize;
1716}
1717#include "vmware_pack_end.h"
1718SVGA3dCmdDefineGBSurface_v3; /* SVGA_3D_CMD_DEFINE_GB_SURFACE_V3 */
1719
1720/*
1629 * Destroy a guest-backed surface. 1721 * Destroy a guest-backed surface.
1630 */ 1722 */
1631 1723
@@ -1672,7 +1764,7 @@ SVGA3dCmdBindGBSurfaceWithPitch; /* SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH */
1672 1764
1673typedef 1765typedef
1674#include "vmware_pack_begin.h" 1766#include "vmware_pack_begin.h"
1675struct{ 1767struct SVGA3dCmdCondBindGBSurface {
1676 uint32 sid; 1768 uint32 sid;
1677 SVGAMobId testMobid; 1769 SVGAMobId testMobid;
1678 SVGAMobId mobid; 1770 SVGAMobId mobid;
@@ -2066,6 +2158,26 @@ struct {
2066 uint32 mobOffset; 2158 uint32 mobOffset;
2067} 2159}
2068#include "vmware_pack_end.h" 2160#include "vmware_pack_end.h"
2069SVGA3dCmdGBMobFence; /* SVGA_3D_CMD_GB_MOB_FENCE*/ 2161SVGA3dCmdGBMobFence; /* SVGA_3D_CMD_GB_MOB_FENCE */
2162
2163typedef
2164#include "vmware_pack_begin.h"
2165struct {
2166 uint32 stid;
2167 SVGA3dSurfaceImageId dest;
2168
2169 uint32 statusMobId;
2170 uint32 statusMobOffset;
2171
2172 /* Reserved fields */
2173 uint32 mustBeInvalidId;
2174 uint32 mustBeZero;
2175}
2176#include "vmware_pack_end.h"
2177SVGA3dCmdScreenCopy; /* SVGA_3D_CMD_SCREEN_COPY */
2178
2179#define SVGA_SCREEN_COPY_STATUS_FAILURE 0x00
2180#define SVGA_SCREEN_COPY_STATUS_SUCCESS 0x01
2181#define SVGA_SCREEN_COPY_STATUS_INVALID 0xFFFFFFFF
2070 2182
2071#endif /* _SVGA3D_CMD_H_ */ 2183#endif /* _SVGA3D_CMD_H_ */
diff --git a/drivers/gpu/drm/vmwgfx/device_include/svga3d_devcaps.h b/drivers/gpu/drm/vmwgfx/device_include/svga3d_devcaps.h
index c18b663f360f..e545013e65d6 100644
--- a/drivers/gpu/drm/vmwgfx/device_include/svga3d_devcaps.h
+++ b/drivers/gpu/drm/vmwgfx/device_include/svga3d_devcaps.h
@@ -229,9 +229,9 @@ typedef enum {
229 SVGA3D_DEVCAP_DEAD2 = 94, 229 SVGA3D_DEVCAP_DEAD2 = 94,
230 230
231 /* 231 /*
232 * Does the device support the DX commands? 232 * Does the device support DXContexts?
233 */ 233 */
234 SVGA3D_DEVCAP_DX = 95, 234 SVGA3D_DEVCAP_DXCONTEXT = 95,
235 235
236 /* 236 /*
237 * What is the maximum size of a texture array? 237 * What is the maximum size of a texture array?
@@ -241,21 +241,47 @@ typedef enum {
241 SVGA3D_DEVCAP_MAX_TEXTURE_ARRAY_SIZE = 96, 241 SVGA3D_DEVCAP_MAX_TEXTURE_ARRAY_SIZE = 96,
242 242
243 /* 243 /*
244 * What is the maximum number of vertex buffers that can 244 * What is the maximum number of vertex buffers or vertex input registers
245 * be used in the DXContext inputAssembly? 245 * that can be expected to work correctly with a DXContext?
246 *
247 * The guest is allowed to set up to SVGA3D_DX_MAX_VERTEXBUFFERS, but
248 * anything in excess of this cap is not guaranteed to render correctly.
249 *
250 * Similarly, the guest can set up to SVGA3D_DX_MAX_VERTEXINPUTREGISTERS
251 * input registers without the SVGA3D_DEVCAP_SM4_1 cap, or
252 * SVGA3D_DX_SM41_MAX_VERTEXINPUTREGISTERS with the SVGA3D_DEVCAP_SM4_1,
253 * but only the registers up to this cap value are guaranteed to render
254 * correctly.
255 *
256 * If guest-drivers are able to expose a lower-limit, it's recommended
257 * that they clamp to this value. Otherwise, the host will make a
258 * best-effort on case-by-case basis if guests exceed this.
246 */ 259 */
247 SVGA3D_DEVCAP_DX_MAX_VERTEXBUFFERS = 97, 260 SVGA3D_DEVCAP_DX_MAX_VERTEXBUFFERS = 97,
248 261
249 /* 262 /*
250 * What is the maximum number of constant buffers 263 * What is the maximum number of constant buffers that can be expected to
251 * that can be expected to work correctly with a 264 * work correctly with a DX context?
252 * DX context? 265 *
266 * The guest is allowed to set up to SVGA3D_DX_MAX_CONSTBUFFERS, but
267 * anything in excess of this cap is not guaranteed to render correctly.
268 *
269 * If guest-drivers are able to expose a lower-limit, it's recommended
270 * that they clamp to this value. Otherwise, the host will make a
271 * best-effort on case-by-case basis if guests exceed this.
253 */ 272 */
254 SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS = 98, 273 SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS = 98,
255 274
256 /* 275 /*
257 * Does the device support provoking vertex control? 276 * Does the device support provoking vertex control?
258 * If zero, the first vertex will always be the provoking vertex. 277 *
278 * If this cap is present, the provokingVertexLast field in the
279 * rasterizer state is enabled. (Guests can then set it to FALSE,
280 * meaning that the first vertex is the provoking vertex, or TRUE,
281 * meaning that the last verteix is the provoking vertex.)
282 *
283 * If this cap is FALSE, then guests should set the provokingVertexLast
284 * to FALSE, otherwise rendering behavior is undefined.
259 */ 285 */
260 SVGA3D_DEVCAP_DX_PROVOKING_VERTEX = 99, 286 SVGA3D_DEVCAP_DX_PROVOKING_VERTEX = 99,
261 287
@@ -281,7 +307,7 @@ typedef enum {
281 SVGA3D_DEVCAP_DXFMT_BUMPU8V8 = 119, 307 SVGA3D_DEVCAP_DXFMT_BUMPU8V8 = 119,
282 SVGA3D_DEVCAP_DXFMT_BUMPL6V5U5 = 120, 308 SVGA3D_DEVCAP_DXFMT_BUMPL6V5U5 = 120,
283 SVGA3D_DEVCAP_DXFMT_BUMPX8L8V8U8 = 121, 309 SVGA3D_DEVCAP_DXFMT_BUMPX8L8V8U8 = 121,
284 SVGA3D_DEVCAP_DXFMT_BUMPL8V8U8 = 122, 310 SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD1 = 122,
285 SVGA3D_DEVCAP_DXFMT_ARGB_S10E5 = 123, 311 SVGA3D_DEVCAP_DXFMT_ARGB_S10E5 = 123,
286 SVGA3D_DEVCAP_DXFMT_ARGB_S23E8 = 124, 312 SVGA3D_DEVCAP_DXFMT_ARGB_S23E8 = 124,
287 SVGA3D_DEVCAP_DXFMT_A2R10G10B10 = 125, 313 SVGA3D_DEVCAP_DXFMT_A2R10G10B10 = 125,
@@ -320,8 +346,8 @@ typedef enum {
320 SVGA3D_DEVCAP_DXFMT_R32G32_SINT = 158, 346 SVGA3D_DEVCAP_DXFMT_R32G32_SINT = 158,
321 SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS = 159, 347 SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS = 159,
322 SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT = 160, 348 SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT = 160,
323 SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24_TYPELESS = 161, 349 SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24 = 161,
324 SVGA3D_DEVCAP_DXFMT_X32_TYPELESS_G8X24_UINT = 162, 350 SVGA3D_DEVCAP_DXFMT_X32_G8X24_UINT = 162,
325 SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS = 163, 351 SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS = 163,
326 SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT = 164, 352 SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT = 164,
327 SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT = 165, 353 SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT = 165,
@@ -339,8 +365,8 @@ typedef enum {
339 SVGA3D_DEVCAP_DXFMT_R32_SINT = 177, 365 SVGA3D_DEVCAP_DXFMT_R32_SINT = 177,
340 SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS = 178, 366 SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS = 178,
341 SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT = 179, 367 SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT = 179,
342 SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8_TYPELESS = 180, 368 SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8 = 180,
343 SVGA3D_DEVCAP_DXFMT_X24_TYPELESS_G8_UINT = 181, 369 SVGA3D_DEVCAP_DXFMT_X24_G8_UINT = 181,
344 SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS = 182, 370 SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS = 182,
345 SVGA3D_DEVCAP_DXFMT_R8G8_UNORM = 183, 371 SVGA3D_DEVCAP_DXFMT_R8G8_UNORM = 183,
346 SVGA3D_DEVCAP_DXFMT_R8G8_UINT = 184, 372 SVGA3D_DEVCAP_DXFMT_R8G8_UINT = 184,
@@ -404,6 +430,17 @@ typedef enum {
404 SVGA3D_DEVCAP_DXFMT_BC4_UNORM = 242, 430 SVGA3D_DEVCAP_DXFMT_BC4_UNORM = 242,
405 SVGA3D_DEVCAP_DXFMT_BC5_UNORM = 243, 431 SVGA3D_DEVCAP_DXFMT_BC5_UNORM = 243,
406 432
433 /*
434 * Advertises shaderModel 4.1 support, independent blend-states,
435 * cube-map arrays, and a higher vertex input registers limit.
436 *
437 * (See documentation on SVGA3D_DEVCAP_DX_MAX_VERTEXBUFFERS.)
438 */
439 SVGA3D_DEVCAP_SM41 = 244,
440
441 SVGA3D_DEVCAP_MULTISAMPLE_2X = 245,
442 SVGA3D_DEVCAP_MULTISAMPLE_4X = 246,
443
407 SVGA3D_DEVCAP_MAX /* This must be the last index. */ 444 SVGA3D_DEVCAP_MAX /* This must be the last index. */
408} SVGA3dDevCapIndex; 445} SVGA3dDevCapIndex;
409 446
@@ -419,9 +456,7 @@ typedef enum {
419 * MIPS: Does the format support mip levels? 456 * MIPS: Does the format support mip levels?
420 * ARRAY: Does the format support texture arrays? 457 * ARRAY: Does the format support texture arrays?
421 * VOLUME: Does the format support having volume? 458 * VOLUME: Does the format support having volume?
422 * MULTISAMPLE_2: Does the format support 2x multisample? 459 * MULTISAMPLE: Does the format support multisample?
423 * MULTISAMPLE_4: Does the format support 4x multisample?
424 * MULTISAMPLE_8: Does the format support 8x multisample?
425 */ 460 */
426#define SVGA3D_DXFMT_SUPPORTED (1 << 0) 461#define SVGA3D_DXFMT_SUPPORTED (1 << 0)
427#define SVGA3D_DXFMT_SHADER_SAMPLE (1 << 1) 462#define SVGA3D_DXFMT_SHADER_SAMPLE (1 << 1)
@@ -432,20 +467,8 @@ typedef enum {
432#define SVGA3D_DXFMT_ARRAY (1 << 6) 467#define SVGA3D_DXFMT_ARRAY (1 << 6)
433#define SVGA3D_DXFMT_VOLUME (1 << 7) 468#define SVGA3D_DXFMT_VOLUME (1 << 7)
434#define SVGA3D_DXFMT_DX_VERTEX_BUFFER (1 << 8) 469#define SVGA3D_DXFMT_DX_VERTEX_BUFFER (1 << 8)
435#define SVGADX_DXFMT_MULTISAMPLE_2 (1 << 9) 470#define SVGA3D_DXFMT_MULTISAMPLE (1 << 9)
436#define SVGADX_DXFMT_MULTISAMPLE_4 (1 << 10) 471#define SVGA3D_DXFMT_MAX (1 << 10)
437#define SVGADX_DXFMT_MULTISAMPLE_8 (1 << 11)
438#define SVGADX_DXFMT_MAX (1 << 12)
439
440/*
441 * Convenience mask for any multisample capability.
442 *
443 * The multisample bits imply both load and render capability.
444 */
445#define SVGA3D_DXFMT_MULTISAMPLE ( \
446 SVGADX_DXFMT_MULTISAMPLE_2 | \
447 SVGADX_DXFMT_MULTISAMPLE_4 | \
448 SVGADX_DXFMT_MULTISAMPLE_8 )
449 472
450typedef union { 473typedef union {
451 Bool b; 474 Bool b;
diff --git a/drivers/gpu/drm/vmwgfx/device_include/svga3d_dx.h b/drivers/gpu/drm/vmwgfx/device_include/svga3d_dx.h
index 8c5ae608cfb4..a5d3b6a686af 100644
--- a/drivers/gpu/drm/vmwgfx/device_include/svga3d_dx.h
+++ b/drivers/gpu/drm/vmwgfx/device_include/svga3d_dx.h
@@ -56,6 +56,16 @@ typedef uint32 SVGA3dInputClassification;
56#define SVGA3D_RESOURCE_TYPE_MAX 7 56#define SVGA3D_RESOURCE_TYPE_MAX 7
57typedef uint32 SVGA3dResourceType; 57typedef uint32 SVGA3dResourceType;
58 58
59#define SVGA3D_COLOR_WRITE_ENABLE_RED (1 << 0)
60#define SVGA3D_COLOR_WRITE_ENABLE_GREEN (1 << 1)
61#define SVGA3D_COLOR_WRITE_ENABLE_BLUE (1 << 2)
62#define SVGA3D_COLOR_WRITE_ENABLE_ALPHA (1 << 3)
63#define SVGA3D_COLOR_WRITE_ENABLE_ALL (SVGA3D_COLOR_WRITE_ENABLE_RED | \
64 SVGA3D_COLOR_WRITE_ENABLE_GREEN | \
65 SVGA3D_COLOR_WRITE_ENABLE_BLUE | \
66 SVGA3D_COLOR_WRITE_ENABLE_ALPHA)
67typedef uint8 SVGA3dColorWriteEnable;
68
59#define SVGA3D_DEPTH_WRITE_MASK_ZERO 0 69#define SVGA3D_DEPTH_WRITE_MASK_ZERO 0
60#define SVGA3D_DEPTH_WRITE_MASK_ALL 1 70#define SVGA3D_DEPTH_WRITE_MASK_ALL 1
61typedef uint8 SVGA3dDepthWriteMask; 71typedef uint8 SVGA3dDepthWriteMask;
@@ -88,17 +98,28 @@ typedef uint8 SVGA3dCullMode;
88#define SVGA3D_COMPARISON_MAX 9 98#define SVGA3D_COMPARISON_MAX 9
89typedef uint8 SVGA3dComparisonFunc; 99typedef uint8 SVGA3dComparisonFunc;
90 100
101/*
102 * SVGA3D_MULTISAMPLE_RAST_DISABLE disables MSAA for all primitives.
103 * SVGA3D_MULTISAMPLE_RAST_DISABLE_LINE, which is supported in SM41,
104 * disables MSAA for lines only.
105 */
106#define SVGA3D_MULTISAMPLE_RAST_DISABLE 0
107#define SVGA3D_MULTISAMPLE_RAST_ENABLE 1
108#define SVGA3D_MULTISAMPLE_RAST_DX_MAX 1
109#define SVGA3D_MULTISAMPLE_RAST_DISABLE_LINE 2
110#define SVGA3D_MULTISAMPLE_RAST_MAX 2
111typedef uint8 SVGA3dMultisampleRastEnable;
112
91#define SVGA3D_DX_MAX_VERTEXBUFFERS 32 113#define SVGA3D_DX_MAX_VERTEXBUFFERS 32
114#define SVGA3D_DX_MAX_VERTEXINPUTREGISTERS 16
115#define SVGA3D_DX_SM41_MAX_VERTEXINPUTREGISTERS 32
92#define SVGA3D_DX_MAX_SOTARGETS 4 116#define SVGA3D_DX_MAX_SOTARGETS 4
93#define SVGA3D_DX_MAX_SRVIEWS 128 117#define SVGA3D_DX_MAX_SRVIEWS 128
94#define SVGA3D_DX_MAX_CONSTBUFFERS 16 118#define SVGA3D_DX_MAX_CONSTBUFFERS 16
95#define SVGA3D_DX_MAX_SAMPLERS 16 119#define SVGA3D_DX_MAX_SAMPLERS 16
96 120
97/* Id limits */ 121#define SVGA3D_DX_MAX_CONSTBUF_BINDING_SIZE (4096 * 4 * (uint32)sizeof(uint32))
98static const uint32 SVGA3dBlendObjectCountPerContext = 4096;
99static const uint32 SVGA3dDepthStencilObjectCountPerContext = 4096;
100 122
101typedef uint32 SVGA3dSurfaceId;
102typedef uint32 SVGA3dShaderResourceViewId; 123typedef uint32 SVGA3dShaderResourceViewId;
103typedef uint32 SVGA3dRenderTargetViewId; 124typedef uint32 SVGA3dRenderTargetViewId;
104typedef uint32 SVGA3dDepthStencilViewId; 125typedef uint32 SVGA3dDepthStencilViewId;
@@ -194,20 +215,6 @@ SVGA3dCmdDXInvalidateContext; /* SVGA_3D_CMD_DX_INVALIDATE_CONTEXT */
194 215
195typedef 216typedef
196#include "vmware_pack_begin.h" 217#include "vmware_pack_begin.h"
197struct SVGA3dReplyFormatData {
198 uint32 formatSupport;
199 uint32 msaa2xQualityLevels:5;
200 uint32 msaa4xQualityLevels:5;
201 uint32 msaa8xQualityLevels:5;
202 uint32 msaa16xQualityLevels:5;
203 uint32 msaa32xQualityLevels:5;
204 uint32 pad:7;
205}
206#include "vmware_pack_end.h"
207SVGA3dReplyFormatData;
208
209typedef
210#include "vmware_pack_begin.h"
211struct SVGA3dCmdDXSetSingleConstantBuffer { 218struct SVGA3dCmdDXSetSingleConstantBuffer {
212 uint32 slot; 219 uint32 slot;
213 SVGA3dShaderType type; 220 SVGA3dShaderType type;
@@ -624,6 +631,28 @@ SVGA3dCmdDXPredCopy; /* SVGA_3D_CMD_DX_PRED_COPY */
624 631
625typedef 632typedef
626#include "vmware_pack_begin.h" 633#include "vmware_pack_begin.h"
634struct SVGA3dCmdDXPredConvertRegion {
635 SVGA3dSurfaceId dstSid;
636 uint32 dstSubResource;
637 SVGA3dBox destBox;
638 SVGA3dSurfaceId srcSid;
639 uint32 srcSubResource;
640 SVGA3dBox srcBox;
641}
642#include "vmware_pack_end.h"
643SVGA3dCmdDXPredConvertRegion; /* SVGA_3D_CMD_DX_PRED_CONVERT_REGION */
644
645typedef
646#include "vmware_pack_begin.h"
647struct SVGA3dCmdDXPredConvert {
648 SVGA3dSurfaceId dstSid;
649 SVGA3dSurfaceId srcSid;
650}
651#include "vmware_pack_end.h"
652SVGA3dCmdDXPredConvert; /* SVGA_3D_CMD_DX_PRED_CONVERT */
653
654typedef
655#include "vmware_pack_begin.h"
627struct SVGA3dCmdDXBufferCopy { 656struct SVGA3dCmdDXBufferCopy {
628 SVGA3dSurfaceId dest; 657 SVGA3dSurfaceId dest;
629 SVGA3dSurfaceId src; 658 SVGA3dSurfaceId src;
@@ -635,23 +664,57 @@ struct SVGA3dCmdDXBufferCopy {
635SVGA3dCmdDXBufferCopy; 664SVGA3dCmdDXBufferCopy;
636/* SVGA_3D_CMD_DX_BUFFER_COPY */ 665/* SVGA_3D_CMD_DX_BUFFER_COPY */
637 666
638typedef uint32 SVGA3dDXStretchBltMode; 667/*
639#define SVGADX_STRETCHBLT_LINEAR (1 << 0) 668 * Perform a surface copy between a multisample, and a non-multisampled
640#define SVGADX_STRETCHBLT_FORCE_SRC_SRGB (1 << 1) 669 * surface.
670 */
671typedef
672#include "vmware_pack_begin.h"
673struct {
674 SVGA3dSurfaceId dstSid;
675 uint32 dstSubResource;
676 SVGA3dSurfaceId srcSid;
677 uint32 srcSubResource;
678 SVGA3dSurfaceFormat copyFormat;
679}
680#include "vmware_pack_end.h"
681SVGA3dCmdDXResolveCopy; /* SVGA_3D_CMD_DX_RESOLVE_COPY */
682
683/*
684 * Perform a predicated surface copy between a multisample, and a
685 * non-multisampled surface.
686 */
687typedef
688#include "vmware_pack_begin.h"
689struct {
690 SVGA3dSurfaceId dstSid;
691 uint32 dstSubResource;
692 SVGA3dSurfaceId srcSid;
693 uint32 srcSubResource;
694 SVGA3dSurfaceFormat copyFormat;
695}
696#include "vmware_pack_end.h"
697SVGA3dCmdDXPredResolveCopy; /* SVGA_3D_CMD_DX_PRED_RESOLVE_COPY */
698
699typedef uint32 SVGA3dDXPresentBltMode;
700#define SVGADX_PRESENTBLT_LINEAR (1 << 0)
701#define SVGADX_PRESENTBLT_FORCE_SRC_SRGB (1 << 1)
702#define SVGADX_PRESENTBLT_FORCE_SRC_XRBIAS (1 << 2)
703#define SVGADX_PRESENTBLT_MODE_MAX (1 << 3)
641 704
642typedef 705typedef
643#include "vmware_pack_begin.h" 706#include "vmware_pack_begin.h"
644struct SVGA3dCmdDXStretchBlt { 707struct SVGA3dCmdDXPresentBlt {
645 SVGA3dSurfaceId srcSid; 708 SVGA3dSurfaceId srcSid;
646 uint32 srcSubResource; 709 uint32 srcSubResource;
647 SVGA3dSurfaceId dstSid; 710 SVGA3dSurfaceId dstSid;
648 uint32 destSubResource; 711 uint32 destSubResource;
649 SVGA3dBox boxSrc; 712 SVGA3dBox boxSrc;
650 SVGA3dBox boxDest; 713 SVGA3dBox boxDest;
651 SVGA3dDXStretchBltMode mode; 714 SVGA3dDXPresentBltMode mode;
652} 715}
653#include "vmware_pack_end.h" 716#include "vmware_pack_end.h"
654SVGA3dCmdDXStretchBlt; /* SVGA_3D_CMD_DX_STRETCHBLT */ 717SVGA3dCmdDXPresentBlt; /* SVGA_3D_CMD_DX_PRESENTBLT*/
655 718
656typedef 719typedef
657#include "vmware_pack_begin.h" 720#include "vmware_pack_begin.h"
@@ -662,26 +725,6 @@ struct SVGA3dCmdDXGenMips {
662SVGA3dCmdDXGenMips; /* SVGA_3D_CMD_DX_GENMIPS */ 725SVGA3dCmdDXGenMips; /* SVGA_3D_CMD_DX_GENMIPS */
663 726
664/* 727/*
665 * Defines a resource/DX surface. Resources share the surfaceId namespace.
666 *
667 */
668typedef
669#include "vmware_pack_begin.h"
670struct SVGA3dCmdDefineGBSurface_v2 {
671 uint32 sid;
672 SVGA3dSurfaceFlags surfaceFlags;
673 SVGA3dSurfaceFormat format;
674 uint32 numMipLevels;
675 uint32 multisampleCount;
676 SVGA3dTextureFilter autogenFilter;
677 SVGA3dSize size;
678 uint32 arraySize;
679 uint32 pad;
680}
681#include "vmware_pack_end.h"
682SVGA3dCmdDefineGBSurface_v2; /* SVGA_3D_CMD_DEFINE_GB_SURFACE_V2 */
683
684/*
685 * Update a sub-resource in a guest-backed resource. 728 * Update a sub-resource in a guest-backed resource.
686 * (Inform the device that the guest-contents have been updated.) 729 * (Inform the device that the guest-contents have been updated.)
687 */ 730 */
@@ -724,7 +767,8 @@ SVGA3dCmdDXInvalidateSubResource; /* SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE */
724 767
725/* 768/*
726 * Raw byte wise transfer from a buffer surface into another surface 769 * Raw byte wise transfer from a buffer surface into another surface
727 * of the requested box. 770 * of the requested box. Supported if 3d is enabled and SVGA_CAP_DX
771 * is set. This command does not take a context.
728 */ 772 */
729typedef 773typedef
730#include "vmware_pack_begin.h" 774#include "vmware_pack_begin.h"
@@ -773,6 +817,93 @@ struct SVGA3dCmdDXSurfaceCopyAndReadback {
773SVGA3dCmdDXSurfaceCopyAndReadback; 817SVGA3dCmdDXSurfaceCopyAndReadback;
774/* SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK */ 818/* SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK */
775 819
820/*
821 * SVGA_DX_HINT_NONE: Does nothing.
822 *
823 * SVGA_DX_HINT_PREFETCH_OBJECT:
824 * SVGA_DX_HINT_PREEVICT_OBJECT:
825 * Consumes a SVGAObjectRef, and hints that the host should consider
826 * fetching/evicting the specified object.
827 *
828 * An id of SVGA3D_INVALID_ID can be used if the guest isn't sure
829 * what object was affected. (For instance, if the guest knows that
830 * it is about to evict a DXShader, but doesn't know precisely which one,
831 * the device can still use this to help limit it's search, or track
832 * how many page-outs have happened.)
833 *
834 * SVGA_DX_HINT_PREFETCH_COBJECT:
835 * SVGA_DX_HINT_PREEVICT_COBJECT:
836 * Same as the above, except they consume an SVGACObjectRef.
837 */
838typedef uint32 SVGADXHintId;
839#define SVGA_DX_HINT_NONE 0
840#define SVGA_DX_HINT_PREFETCH_OBJECT 1
841#define SVGA_DX_HINT_PREEVICT_OBJECT 2
842#define SVGA_DX_HINT_PREFETCH_COBJECT 3
843#define SVGA_DX_HINT_PREEVICT_COBJECT 4
844#define SVGA_DX_HINT_MAX 5
845
846typedef
847#include "vmware_pack_begin.h"
848struct SVGAObjectRef {
849 SVGAOTableType type;
850 uint32 id;
851}
852#include "vmware_pack_end.h"
853SVGAObjectRef;
854
855typedef
856#include "vmware_pack_begin.h"
857struct SVGACObjectRef {
858 SVGACOTableType type;
859 uint32 cid;
860 uint32 id;
861}
862#include "vmware_pack_end.h"
863SVGACObjectRef;
864
865typedef
866#include "vmware_pack_begin.h"
867struct SVGA3dCmdDXHint {
868 SVGADXHintId hintId;
869
870 /*
871 * Followed by variable sized data depending on the hintId.
872 */
873}
874#include "vmware_pack_end.h"
875SVGA3dCmdDXHint;
876/* SVGA_3D_CMD_DX_HINT */
877
878typedef
879#include "vmware_pack_begin.h"
880struct SVGA3dCmdDXBufferUpdate {
881 SVGA3dSurfaceId sid;
882 uint32 x;
883 uint32 width;
884}
885#include "vmware_pack_end.h"
886SVGA3dCmdDXBufferUpdate;
887/* SVGA_3D_CMD_DX_BUFFER_UPDATE */
888
889typedef
890#include "vmware_pack_begin.h"
891struct SVGA3dCmdDXSetConstantBufferOffset {
892 uint32 slot;
893 uint32 offsetInBytes;
894}
895#include "vmware_pack_end.h"
896SVGA3dCmdDXSetConstantBufferOffset;
897
898typedef SVGA3dCmdDXSetConstantBufferOffset SVGA3dCmdDXSetVSConstantBufferOffset;
899/* SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET */
900
901typedef SVGA3dCmdDXSetConstantBufferOffset SVGA3dCmdDXSetPSConstantBufferOffset;
902/* SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET */
903
904typedef SVGA3dCmdDXSetConstantBufferOffset SVGA3dCmdDXSetGSConstantBufferOffset;
905/* SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET */
906
776 907
777typedef 908typedef
778#include "vmware_pack_begin.h" 909#include "vmware_pack_begin.h"
@@ -789,7 +920,7 @@ struct {
789 uint32 firstArraySlice; 920 uint32 firstArraySlice;
790 uint32 mipLevels; 921 uint32 mipLevels;
791 uint32 arraySize; 922 uint32 arraySize;
792 } tex; 923 } tex; /* 1d, 2d, 3d, cube */
793 struct { 924 struct {
794 uint32 firstElement; 925 uint32 firstElement;
795 uint32 numElements; 926 uint32 numElements;
@@ -844,6 +975,7 @@ struct SVGA3dRenderTargetViewDesc {
844 struct { 975 struct {
845 uint32 firstElement; 976 uint32 firstElement;
846 uint32 numElements; 977 uint32 numElements;
978 uint32 padding0;
847 } buffer; 979 } buffer;
848 struct { 980 struct {
849 uint32 mipSlice; 981 uint32 mipSlice;
@@ -964,9 +1096,6 @@ SVGA3dInputElementDesc;
964typedef 1096typedef
965#include "vmware_pack_begin.h" 1097#include "vmware_pack_begin.h"
966struct { 1098struct {
967 /*
968 * XXX: How many of these can there be?
969 */
970 uint32 elid; 1099 uint32 elid;
971 uint32 numDescs; 1100 uint32 numDescs;
972 SVGA3dInputElementDesc desc[32]; 1101 SVGA3dInputElementDesc desc[32];
@@ -1007,7 +1136,7 @@ struct SVGA3dDXBlendStatePerRT {
1007 uint8 srcBlendAlpha; 1136 uint8 srcBlendAlpha;
1008 uint8 destBlendAlpha; 1137 uint8 destBlendAlpha;
1009 uint8 blendOpAlpha; 1138 uint8 blendOpAlpha;
1010 uint8 renderTargetWriteMask; 1139 SVGA3dColorWriteEnable renderTargetWriteMask;
1011 uint8 logicOpEnable; 1140 uint8 logicOpEnable;
1012 uint8 logicOp; 1141 uint8 logicOp;
1013 uint16 pad0; 1142 uint16 pad0;
@@ -1125,7 +1254,7 @@ struct {
1125 float slopeScaledDepthBias; 1254 float slopeScaledDepthBias;
1126 uint8 depthClipEnable; 1255 uint8 depthClipEnable;
1127 uint8 scissorEnable; 1256 uint8 scissorEnable;
1128 uint8 multisampleEnable; 1257 SVGA3dMultisampleRastEnable multisampleEnable;
1129 uint8 antialiasedLineEnable; 1258 uint8 antialiasedLineEnable;
1130 float lineWidth; 1259 float lineWidth;
1131 uint8 lineStippleEnable; 1260 uint8 lineStippleEnable;
@@ -1152,7 +1281,7 @@ struct SVGA3dCmdDXDefineRasterizerState {
1152 float slopeScaledDepthBias; 1281 float slopeScaledDepthBias;
1153 uint8 depthClipEnable; 1282 uint8 depthClipEnable;
1154 uint8 scissorEnable; 1283 uint8 scissorEnable;
1155 uint8 multisampleEnable; 1284 SVGA3dMultisampleRastEnable multisampleEnable;
1156 uint8 antialiasedLineEnable; 1285 uint8 antialiasedLineEnable;
1157 float lineWidth; 1286 float lineWidth;
1158 uint8 lineStippleEnable; 1287 uint8 lineStippleEnable;
@@ -1222,21 +1351,6 @@ struct SVGA3dCmdDXDestroySamplerState {
1222#include "vmware_pack_end.h" 1351#include "vmware_pack_end.h"
1223SVGA3dCmdDXDestroySamplerState; /* SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE */ 1352SVGA3dCmdDXDestroySamplerState; /* SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE */
1224 1353
1225/*
1226 */
1227typedef
1228#include "vmware_pack_begin.h"
1229struct SVGA3dSignatureEntry {
1230 uint8 systemValue;
1231 uint8 reg; /* register is a reserved word */
1232 uint16 mask;
1233 uint8 registerComponentType;
1234 uint8 minPrecision;
1235 uint16 pad0;
1236}
1237#include "vmware_pack_end.h"
1238SVGA3dSignatureEntry;
1239
1240typedef 1354typedef
1241#include "vmware_pack_begin.h" 1355#include "vmware_pack_begin.h"
1242struct SVGA3dCmdDXDefineShader { 1356struct SVGA3dCmdDXDefineShader {
@@ -1254,12 +1368,7 @@ struct SVGACOTableDXShaderEntry {
1254 uint32 sizeInBytes; 1368 uint32 sizeInBytes;
1255 uint32 offsetInBytes; 1369 uint32 offsetInBytes;
1256 SVGAMobId mobid; 1370 SVGAMobId mobid;
1257 uint32 numInputSignatureEntries; 1371 uint32 pad[4];
1258 uint32 numOutputSignatureEntries;
1259
1260 uint32 numPatchConstantSignatureEntries;
1261
1262 uint32 pad;
1263} 1372}
1264#include "vmware_pack_end.h" 1373#include "vmware_pack_end.h"
1265SVGACOTableDXShaderEntry; 1374SVGACOTableDXShaderEntry;
@@ -1283,6 +1392,25 @@ struct SVGA3dCmdDXBindShader {
1283#include "vmware_pack_end.h" 1392#include "vmware_pack_end.h"
1284SVGA3dCmdDXBindShader; /* SVGA_3D_CMD_DX_BIND_SHADER */ 1393SVGA3dCmdDXBindShader; /* SVGA_3D_CMD_DX_BIND_SHADER */
1285 1394
1395typedef
1396#include "vmware_pack_begin.h"
1397struct SVGA3dCmdDXBindAllShader {
1398 uint32 cid;
1399 SVGAMobId mobid;
1400}
1401#include "vmware_pack_end.h"
1402SVGA3dCmdDXBindAllShader; /* SVGA_3D_CMD_DX_BIND_ALL_SHADER */
1403
1404typedef
1405#include "vmware_pack_begin.h"
1406struct SVGA3dCmdDXCondBindAllShader {
1407 uint32 cid;
1408 SVGAMobId testMobid;
1409 SVGAMobId mobid;
1410}
1411#include "vmware_pack_end.h"
1412SVGA3dCmdDXCondBindAllShader; /* SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER */
1413
1286/* 1414/*
1287 * The maximum number of streamout decl's in each streamout entry. 1415 * The maximum number of streamout decl's in each streamout entry.
1288 */ 1416 */
@@ -1356,7 +1484,6 @@ SVGA3dCmdDXMobFence64; /* SVGA_3D_CMD_DX_MOB_FENCE_64 */
1356 * 1484 *
1357 * This command allows the guest to bind a mob to a context-object table. 1485 * This command allows the guest to bind a mob to a context-object table.
1358 */ 1486 */
1359
1360typedef 1487typedef
1361#include "vmware_pack_begin.h" 1488#include "vmware_pack_begin.h"
1362struct SVGA3dCmdDXSetCOTable { 1489struct SVGA3dCmdDXSetCOTable {
@@ -1368,6 +1495,26 @@ struct SVGA3dCmdDXSetCOTable {
1368#include "vmware_pack_end.h" 1495#include "vmware_pack_end.h"
1369SVGA3dCmdDXSetCOTable; /* SVGA_3D_CMD_DX_SET_COTABLE */ 1496SVGA3dCmdDXSetCOTable; /* SVGA_3D_CMD_DX_SET_COTABLE */
1370 1497
1498/*
1499 * Guests using SVGA_3D_CMD_DX_GROW_COTABLE are promising that
1500 * the new COTable contains the same contents as the old one, except possibly
1501 * for some new invalid entries at the end.
1502 *
1503 * If there is an old cotable mob bound, it also has to still be valid.
1504 *
1505 * (Otherwise, guests should use the DXSetCOTableBase command.)
1506 */
1507typedef
1508#include "vmware_pack_begin.h"
1509struct SVGA3dCmdDXGrowCOTable {
1510 uint32 cid;
1511 uint32 mobid;
1512 SVGACOTableType type;
1513 uint32 validSizeInBytes;
1514}
1515#include "vmware_pack_end.h"
1516SVGA3dCmdDXGrowCOTable; /* SVGA_3D_CMD_DX_GROW_COTABLE */
1517
1371typedef 1518typedef
1372#include "vmware_pack_begin.h" 1519#include "vmware_pack_begin.h"
1373struct SVGA3dCmdDXReadbackCOTable { 1520struct SVGA3dCmdDXReadbackCOTable {
@@ -1471,7 +1618,7 @@ struct SVGADXContextMobFormat {
1471 SVGA3dQueryId queryID[SVGA3D_MAX_QUERY]; 1618 SVGA3dQueryId queryID[SVGA3D_MAX_QUERY];
1472 1619
1473 SVGA3dCOTableData cotables[SVGA_COTABLE_MAX]; 1620 SVGA3dCOTableData cotables[SVGA_COTABLE_MAX];
1474 uint32 pad7[381]; 1621 uint32 pad7[380];
1475} 1622}
1476#include "vmware_pack_end.h" 1623#include "vmware_pack_end.h"
1477SVGADXContextMobFormat; 1624SVGADXContextMobFormat;
diff --git a/drivers/gpu/drm/vmwgfx/device_include/svga3d_limits.h b/drivers/gpu/drm/vmwgfx/device_include/svga3d_limits.h
index a1c36877ad55..2d462ab7cccf 100644
--- a/drivers/gpu/drm/vmwgfx/device_include/svga3d_limits.h
+++ b/drivers/gpu/drm/vmwgfx/device_include/svga3d_limits.h
@@ -62,7 +62,9 @@
62 * Maximum size in dwords of shader text the SVGA device will allow. 62 * Maximum size in dwords of shader text the SVGA device will allow.
63 * Currently 8 MB. 63 * Currently 8 MB.
64 */ 64 */
65#define SVGA3D_MAX_SHADER_MEMORY (8 * 1024 * 1024 / sizeof(uint32)) 65#define SVGA3D_MAX_SHADER_MEMORY_BYTES (8 * 1024 * 1024)
66#define SVGA3D_MAX_SHADER_MEMORY (SVGA3D_MAX_SHADER_MEMORY_BYTES / \
67 sizeof(uint32))
66 68
67#define SVGA3D_MAX_CLIP_PLANES 6 69#define SVGA3D_MAX_CLIP_PLANES 6
68 70
diff --git a/drivers/gpu/drm/vmwgfx/device_include/svga3d_surfacedefs.h b/drivers/gpu/drm/vmwgfx/device_include/svga3d_surfacedefs.h
index babe7cb84fc2..6422e3899cdf 100644
--- a/drivers/gpu/drm/vmwgfx/device_include/svga3d_surfacedefs.h
+++ b/drivers/gpu/drm/vmwgfx/device_include/svga3d_surfacedefs.h
@@ -25,189 +25,355 @@
25 * 25 *
26 **************************************************************************/ 26 **************************************************************************/
27 27
28#include <linux/kernel.h> 28/*
29 29 * svga3d_surfacedefs.h --
30#ifdef __KERNEL__ 30 *
31 31 * Surface definitions and inlineable utilities for SVGA3d.
32#include <drm/vmwgfx_drm.h> 32 */
33#define surf_size_struct struct drm_vmw_size
34
35#else /* __KERNEL__ */
36 33
37#ifndef ARRAY_SIZE 34#ifndef _SVGA3D_SURFACEDEFS_H_
38#define ARRAY_SIZE(_A) (sizeof(_A) / sizeof((_A)[0])) 35#define _SVGA3D_SURFACEDEFS_H_
39#endif /* ARRAY_SIZE */
40 36
41#define max_t(type, x, y) ((x) > (y) ? (x) : (y)) 37#define INCLUDE_ALLOW_USERLEVEL
42#define surf_size_struct SVGA3dSize 38#define INCLUDE_ALLOW_MODULE
43#define u32 uint32 39#include "includeCheck.h"
44 40
45#endif /* __KERNEL__ */ 41#include <linux/kernel.h>
42#include <drm/vmwgfx_drm.h>
46 43
47#include "svga3d_reg.h" 44#include "svga3d_reg.h"
48 45
46#define surf_size_struct struct drm_vmw_size
47
49/* 48/*
50 * enum svga3d_block_desc describes the active data channels in a block. 49 * enum svga3d_block_desc - describes generic properties about formats.
51 *
52 * There can be at-most four active channels in a block:
53 * 1. Red, bump W, luminance and depth are stored in the first channel.
54 * 2. Green, bump V and stencil are stored in the second channel.
55 * 3. Blue and bump U are stored in the third channel.
56 * 4. Alpha and bump Q are stored in the fourth channel.
57 *
58 * Block channels can be used to store compressed and buffer data:
59 * 1. For compressed formats, only the data channel is used and its size
60 * is equal to that of a singular block in the compression scheme.
61 * 2. For buffer formats, only the data channel is used and its size is
62 * exactly one byte in length.
63 * 3. In each case the bit depth represent the size of a singular block.
64 *
65 * Note: Compressed and IEEE formats do not use the bitMask structure.
66 */ 50 */
67
68enum svga3d_block_desc { 51enum svga3d_block_desc {
69 SVGA3DBLOCKDESC_NONE = 0, /* No channels are active */ 52 /* Nothing special can be said about this format. */
70 SVGA3DBLOCKDESC_BLUE = 1 << 0, /* Block with red channel 53 SVGA3DBLOCKDESC_NONE = 0,
71 data */ 54
72 SVGA3DBLOCKDESC_U = 1 << 0, /* Block with bump U channel 55 /* Format contains Blue/U data */
73 data */ 56 SVGA3DBLOCKDESC_BLUE = 1 << 0,
74 SVGA3DBLOCKDESC_UV_VIDEO = 1 << 7, /* Block with alternating video 57 SVGA3DBLOCKDESC_W = 1 << 0,
75 U and V */ 58 SVGA3DBLOCKDESC_BUMP_L = 1 << 0,
76 SVGA3DBLOCKDESC_GREEN = 1 << 1, /* Block with green channel 59
77 data */ 60 /* Format contains Green/V data */
78 SVGA3DBLOCKDESC_V = 1 << 1, /* Block with bump V channel 61 SVGA3DBLOCKDESC_GREEN = 1 << 1,
79 data */ 62 SVGA3DBLOCKDESC_V = 1 << 1,
80 SVGA3DBLOCKDESC_STENCIL = 1 << 1, /* Block with a stencil 63
81 channel */ 64 /* Format contains Red/W/Luminance data */
82 SVGA3DBLOCKDESC_RED = 1 << 2, /* Block with blue channel 65 SVGA3DBLOCKDESC_RED = 1 << 2,
83 data */ 66 SVGA3DBLOCKDESC_U = 1 << 2,
84 SVGA3DBLOCKDESC_W = 1 << 2, /* Block with bump W channel 67 SVGA3DBLOCKDESC_LUMINANCE = 1 << 2,
85 data */ 68
86 SVGA3DBLOCKDESC_LUMINANCE = 1 << 2, /* Block with luminance channel 69 /* Format contains Alpha/Q data */
87 data */ 70 SVGA3DBLOCKDESC_ALPHA = 1 << 3,
88 SVGA3DBLOCKDESC_Y = 1 << 2, /* Block with video luminance 71 SVGA3DBLOCKDESC_Q = 1 << 3,
89 data */ 72
90 SVGA3DBLOCKDESC_DEPTH = 1 << 2, /* Block with depth channel */ 73 /* Format is a buffer */
91 SVGA3DBLOCKDESC_ALPHA = 1 << 3, /* Block with an alpha 74 SVGA3DBLOCKDESC_BUFFER = 1 << 4,
92 channel */ 75
93 SVGA3DBLOCKDESC_Q = 1 << 3, /* Block with bump Q channel 76 /* Format is compressed */
94 data */ 77 SVGA3DBLOCKDESC_COMPRESSED = 1 << 5,
95 SVGA3DBLOCKDESC_BUFFER = 1 << 4, /* Block stores 1 byte of 78
96 data */ 79 /* Format uses IEEE floating point */
97 SVGA3DBLOCKDESC_COMPRESSED = 1 << 5, /* Block stores n bytes of 80 SVGA3DBLOCKDESC_FP = 1 << 6,
98 data depending on the 81
99 compression method used */ 82 /* Three separate blocks store data. */
100 SVGA3DBLOCKDESC_IEEE_FP = 1 << 6, /* Block stores data in an IEEE 83 SVGA3DBLOCKDESC_PLANAR_YUV = 1 << 7,
101 floating point 84
102 representation in 85 /* 2 planes of Y, UV, e.g., NV12. */
103 all channels */ 86 SVGA3DBLOCKDESC_2PLANAR_YUV = 1 << 8,
104 SVGA3DBLOCKDESC_PLANAR_YUV = 1 << 8, /* Three separate blocks store 87
105 data. */ 88 /* 3 planes of separate Y, U, V, e.g., YV12. */
106 SVGA3DBLOCKDESC_U_VIDEO = 1 << 9, /* Block with U video data */ 89 SVGA3DBLOCKDESC_3PLANAR_YUV = 1 << 9,
107 SVGA3DBLOCKDESC_V_VIDEO = 1 << 10, /* Block with V video data */ 90
108 SVGA3DBLOCKDESC_EXP = 1 << 11, /* Shared exponent */ 91 /* Block with a stencil channel */
109 SVGA3DBLOCKDESC_SRGB = 1 << 12, /* Data is in sRGB format */ 92 SVGA3DBLOCKDESC_STENCIL = 1 << 11,
110 SVGA3DBLOCKDESC_2PLANAR_YUV = 1 << 13, /* 2 planes of Y, UV, 93
111 e.g., NV12. */ 94 /* Typeless format */
112 SVGA3DBLOCKDESC_3PLANAR_YUV = 1 << 14, /* 3 planes of separate 95 SVGA3DBLOCKDESC_TYPELESS = 1 << 12,
113 Y, U, V, e.g., YV12. */ 96
114 97 /* Channels are signed integers */
115 SVGA3DBLOCKDESC_RG = SVGA3DBLOCKDESC_RED | 98 SVGA3DBLOCKDESC_SINT = 1 << 13,
116 SVGA3DBLOCKDESC_GREEN, 99
117 SVGA3DBLOCKDESC_RGB = SVGA3DBLOCKDESC_RG | 100 /* Channels are unsigned integers */
118 SVGA3DBLOCKDESC_BLUE, 101 SVGA3DBLOCKDESC_UINT = 1 << 14,
119 SVGA3DBLOCKDESC_RGB_SRGB = SVGA3DBLOCKDESC_RGB | 102
120 SVGA3DBLOCKDESC_SRGB, 103 /* Channels are normalized (when sampling) */
121 SVGA3DBLOCKDESC_RGBA = SVGA3DBLOCKDESC_RGB | 104 SVGA3DBLOCKDESC_NORM = 1 << 15,
122 SVGA3DBLOCKDESC_ALPHA, 105
123 SVGA3DBLOCKDESC_RGBA_SRGB = SVGA3DBLOCKDESC_RGBA | 106 /* Channels are in SRGB */
124 SVGA3DBLOCKDESC_SRGB, 107 SVGA3DBLOCKDESC_SRGB = 1 << 16,
108
109 /* Shared exponent */
110 SVGA3DBLOCKDESC_EXP = 1 << 17,
111
112 /* Format contains color data. */
113 SVGA3DBLOCKDESC_COLOR = 1 << 18,
114 /* Format contains depth data. */
115 SVGA3DBLOCKDESC_DEPTH = 1 << 19,
116 /* Format contains bump data. */
117 SVGA3DBLOCKDESC_BUMP = 1 << 20,
118
119 /* Format contains YUV video data. */
120 SVGA3DBLOCKDESC_YUV_VIDEO = 1 << 21,
121
122 /* For mixed unsigned/signed formats. */
123 SVGA3DBLOCKDESC_MIXED = 1 << 22,
124
125 /* For distingushing CxV8U8. */
126 SVGA3DBLOCKDESC_CX = 1 << 23,
127
128 /* Different compressed format groups. */
129 SVGA3DBLOCKDESC_BC1 = 1 << 24,
130 SVGA3DBLOCKDESC_BC2 = 1 << 25,
131 SVGA3DBLOCKDESC_BC3 = 1 << 26,
132 SVGA3DBLOCKDESC_BC4 = 1 << 27,
133 SVGA3DBLOCKDESC_BC5 = 1 << 28,
134
135 SVGA3DBLOCKDESC_A_UINT = SVGA3DBLOCKDESC_ALPHA |
136 SVGA3DBLOCKDESC_UINT |
137 SVGA3DBLOCKDESC_COLOR,
138 SVGA3DBLOCKDESC_A_UNORM = SVGA3DBLOCKDESC_A_UINT |
139 SVGA3DBLOCKDESC_NORM,
140 SVGA3DBLOCKDESC_R_UINT = SVGA3DBLOCKDESC_RED |
141 SVGA3DBLOCKDESC_UINT |
142 SVGA3DBLOCKDESC_COLOR,
143 SVGA3DBLOCKDESC_R_UNORM = SVGA3DBLOCKDESC_R_UINT |
144 SVGA3DBLOCKDESC_NORM,
145 SVGA3DBLOCKDESC_R_SINT = SVGA3DBLOCKDESC_RED |
146 SVGA3DBLOCKDESC_SINT |
147 SVGA3DBLOCKDESC_COLOR,
148 SVGA3DBLOCKDESC_R_SNORM = SVGA3DBLOCKDESC_R_SINT |
149 SVGA3DBLOCKDESC_NORM,
150 SVGA3DBLOCKDESC_G_UINT = SVGA3DBLOCKDESC_GREEN |
151 SVGA3DBLOCKDESC_UINT |
152 SVGA3DBLOCKDESC_COLOR,
153 SVGA3DBLOCKDESC_RG_UINT = SVGA3DBLOCKDESC_RED |
154 SVGA3DBLOCKDESC_GREEN |
155 SVGA3DBLOCKDESC_UINT |
156 SVGA3DBLOCKDESC_COLOR,
157 SVGA3DBLOCKDESC_RG_UNORM = SVGA3DBLOCKDESC_RG_UINT |
158 SVGA3DBLOCKDESC_NORM,
159 SVGA3DBLOCKDESC_RG_SINT = SVGA3DBLOCKDESC_RED |
160 SVGA3DBLOCKDESC_GREEN |
161 SVGA3DBLOCKDESC_SINT |
162 SVGA3DBLOCKDESC_COLOR,
163 SVGA3DBLOCKDESC_RG_SNORM = SVGA3DBLOCKDESC_RG_SINT |
164 SVGA3DBLOCKDESC_NORM,
165 SVGA3DBLOCKDESC_RGB_UINT = SVGA3DBLOCKDESC_RED |
166 SVGA3DBLOCKDESC_GREEN |
167 SVGA3DBLOCKDESC_BLUE |
168 SVGA3DBLOCKDESC_UINT |
169 SVGA3DBLOCKDESC_COLOR,
170 SVGA3DBLOCKDESC_RGB_SINT = SVGA3DBLOCKDESC_RED |
171 SVGA3DBLOCKDESC_GREEN |
172 SVGA3DBLOCKDESC_BLUE |
173 SVGA3DBLOCKDESC_SINT |
174 SVGA3DBLOCKDESC_COLOR,
175 SVGA3DBLOCKDESC_RGB_UNORM = SVGA3DBLOCKDESC_RGB_UINT |
176 SVGA3DBLOCKDESC_NORM,
177 SVGA3DBLOCKDESC_RGB_UNORM_SRGB = SVGA3DBLOCKDESC_RGB_UNORM |
178 SVGA3DBLOCKDESC_SRGB,
179 SVGA3DBLOCKDESC_RGBA_UINT = SVGA3DBLOCKDESC_RED |
180 SVGA3DBLOCKDESC_GREEN |
181 SVGA3DBLOCKDESC_BLUE |
182 SVGA3DBLOCKDESC_ALPHA |
183 SVGA3DBLOCKDESC_UINT |
184 SVGA3DBLOCKDESC_COLOR,
185 SVGA3DBLOCKDESC_RGBA_UNORM = SVGA3DBLOCKDESC_RGBA_UINT |
186 SVGA3DBLOCKDESC_NORM,
187 SVGA3DBLOCKDESC_RGBA_UNORM_SRGB = SVGA3DBLOCKDESC_RGBA_UNORM |
188 SVGA3DBLOCKDESC_SRGB,
189 SVGA3DBLOCKDESC_RGBA_SINT = SVGA3DBLOCKDESC_RED |
190 SVGA3DBLOCKDESC_GREEN |
191 SVGA3DBLOCKDESC_BLUE |
192 SVGA3DBLOCKDESC_ALPHA |
193 SVGA3DBLOCKDESC_SINT |
194 SVGA3DBLOCKDESC_COLOR,
195 SVGA3DBLOCKDESC_RGBA_SNORM = SVGA3DBLOCKDESC_RGBA_SINT |
196 SVGA3DBLOCKDESC_NORM,
197 SVGA3DBLOCKDESC_RGBA_FP = SVGA3DBLOCKDESC_RED |
198 SVGA3DBLOCKDESC_GREEN |
199 SVGA3DBLOCKDESC_BLUE |
200 SVGA3DBLOCKDESC_ALPHA |
201 SVGA3DBLOCKDESC_FP |
202 SVGA3DBLOCKDESC_COLOR,
125 SVGA3DBLOCKDESC_UV = SVGA3DBLOCKDESC_U | 203 SVGA3DBLOCKDESC_UV = SVGA3DBLOCKDESC_U |
126 SVGA3DBLOCKDESC_V, 204 SVGA3DBLOCKDESC_V |
205 SVGA3DBLOCKDESC_BUMP,
127 SVGA3DBLOCKDESC_UVL = SVGA3DBLOCKDESC_UV | 206 SVGA3DBLOCKDESC_UVL = SVGA3DBLOCKDESC_UV |
128 SVGA3DBLOCKDESC_LUMINANCE, 207 SVGA3DBLOCKDESC_BUMP_L |
208 SVGA3DBLOCKDESC_MIXED |
209 SVGA3DBLOCKDESC_BUMP,
129 SVGA3DBLOCKDESC_UVW = SVGA3DBLOCKDESC_UV | 210 SVGA3DBLOCKDESC_UVW = SVGA3DBLOCKDESC_UV |
130 SVGA3DBLOCKDESC_W, 211 SVGA3DBLOCKDESC_W |
212 SVGA3DBLOCKDESC_BUMP,
131 SVGA3DBLOCKDESC_UVWA = SVGA3DBLOCKDESC_UVW | 213 SVGA3DBLOCKDESC_UVWA = SVGA3DBLOCKDESC_UVW |
132 SVGA3DBLOCKDESC_ALPHA, 214 SVGA3DBLOCKDESC_ALPHA |
215 SVGA3DBLOCKDESC_MIXED |
216 SVGA3DBLOCKDESC_BUMP,
133 SVGA3DBLOCKDESC_UVWQ = SVGA3DBLOCKDESC_U | 217 SVGA3DBLOCKDESC_UVWQ = SVGA3DBLOCKDESC_U |
134 SVGA3DBLOCKDESC_V | 218 SVGA3DBLOCKDESC_V |
135 SVGA3DBLOCKDESC_W | 219 SVGA3DBLOCKDESC_W |
136 SVGA3DBLOCKDESC_Q, 220 SVGA3DBLOCKDESC_Q |
137 SVGA3DBLOCKDESC_LA = SVGA3DBLOCKDESC_LUMINANCE | 221 SVGA3DBLOCKDESC_BUMP,
138 SVGA3DBLOCKDESC_ALPHA, 222 SVGA3DBLOCKDESC_L_UNORM = SVGA3DBLOCKDESC_LUMINANCE |
223 SVGA3DBLOCKDESC_UINT |
224 SVGA3DBLOCKDESC_NORM |
225 SVGA3DBLOCKDESC_COLOR,
226 SVGA3DBLOCKDESC_LA_UNORM = SVGA3DBLOCKDESC_LUMINANCE |
227 SVGA3DBLOCKDESC_ALPHA |
228 SVGA3DBLOCKDESC_UINT |
229 SVGA3DBLOCKDESC_NORM |
230 SVGA3DBLOCKDESC_COLOR,
139 SVGA3DBLOCKDESC_R_FP = SVGA3DBLOCKDESC_RED | 231 SVGA3DBLOCKDESC_R_FP = SVGA3DBLOCKDESC_RED |
140 SVGA3DBLOCKDESC_IEEE_FP, 232 SVGA3DBLOCKDESC_FP |
233 SVGA3DBLOCKDESC_COLOR,
141 SVGA3DBLOCKDESC_RG_FP = SVGA3DBLOCKDESC_R_FP | 234 SVGA3DBLOCKDESC_RG_FP = SVGA3DBLOCKDESC_R_FP |
142 SVGA3DBLOCKDESC_GREEN, 235 SVGA3DBLOCKDESC_GREEN |
236 SVGA3DBLOCKDESC_COLOR,
143 SVGA3DBLOCKDESC_RGB_FP = SVGA3DBLOCKDESC_RG_FP | 237 SVGA3DBLOCKDESC_RGB_FP = SVGA3DBLOCKDESC_RG_FP |
144 SVGA3DBLOCKDESC_BLUE, 238 SVGA3DBLOCKDESC_BLUE |
145 SVGA3DBLOCKDESC_RGBA_FP = SVGA3DBLOCKDESC_RGB_FP | 239 SVGA3DBLOCKDESC_COLOR,
146 SVGA3DBLOCKDESC_ALPHA, 240 SVGA3DBLOCKDESC_YUV = SVGA3DBLOCKDESC_YUV_VIDEO |
147 SVGA3DBLOCKDESC_DS = SVGA3DBLOCKDESC_DEPTH | 241 SVGA3DBLOCKDESC_COLOR,
148 SVGA3DBLOCKDESC_STENCIL,
149 SVGA3DBLOCKDESC_YUV = SVGA3DBLOCKDESC_UV_VIDEO |
150 SVGA3DBLOCKDESC_Y,
151 SVGA3DBLOCKDESC_AYUV = SVGA3DBLOCKDESC_ALPHA | 242 SVGA3DBLOCKDESC_AYUV = SVGA3DBLOCKDESC_ALPHA |
152 SVGA3DBLOCKDESC_Y | 243 SVGA3DBLOCKDESC_YUV_VIDEO |
153 SVGA3DBLOCKDESC_U_VIDEO | 244 SVGA3DBLOCKDESC_COLOR,
154 SVGA3DBLOCKDESC_V_VIDEO, 245 SVGA3DBLOCKDESC_RGB_EXP = SVGA3DBLOCKDESC_RED |
155 SVGA3DBLOCKDESC_RGBE = SVGA3DBLOCKDESC_RGB | 246 SVGA3DBLOCKDESC_GREEN |
156 SVGA3DBLOCKDESC_EXP, 247 SVGA3DBLOCKDESC_BLUE |
157 SVGA3DBLOCKDESC_COMPRESSED_SRGB = SVGA3DBLOCKDESC_COMPRESSED | 248 SVGA3DBLOCKDESC_EXP |
158 SVGA3DBLOCKDESC_SRGB, 249 SVGA3DBLOCKDESC_COLOR,
159 SVGA3DBLOCKDESC_NV12 = SVGA3DBLOCKDESC_PLANAR_YUV | 250
160 SVGA3DBLOCKDESC_2PLANAR_YUV, 251 SVGA3DBLOCKDESC_COMP_TYPELESS = SVGA3DBLOCKDESC_COMPRESSED |
161 SVGA3DBLOCKDESC_YV12 = SVGA3DBLOCKDESC_PLANAR_YUV | 252 SVGA3DBLOCKDESC_TYPELESS,
162 SVGA3DBLOCKDESC_3PLANAR_YUV, 253 SVGA3DBLOCKDESC_COMP_UNORM = SVGA3DBLOCKDESC_COMPRESSED |
254 SVGA3DBLOCKDESC_UINT |
255 SVGA3DBLOCKDESC_NORM |
256 SVGA3DBLOCKDESC_COLOR,
257 SVGA3DBLOCKDESC_COMP_SNORM = SVGA3DBLOCKDESC_COMPRESSED |
258 SVGA3DBLOCKDESC_SINT |
259 SVGA3DBLOCKDESC_NORM |
260 SVGA3DBLOCKDESC_COLOR,
261 SVGA3DBLOCKDESC_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_COMP_UNORM |
262 SVGA3DBLOCKDESC_SRGB,
263 SVGA3DBLOCKDESC_BC1_COMP_TYPELESS = SVGA3DBLOCKDESC_BC1 |
264 SVGA3DBLOCKDESC_COMP_TYPELESS,
265 SVGA3DBLOCKDESC_BC1_COMP_UNORM = SVGA3DBLOCKDESC_BC1 |
266 SVGA3DBLOCKDESC_COMP_UNORM,
267 SVGA3DBLOCKDESC_BC1_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_BC1_COMP_UNORM |
268 SVGA3DBLOCKDESC_SRGB,
269 SVGA3DBLOCKDESC_BC2_COMP_TYPELESS = SVGA3DBLOCKDESC_BC2 |
270 SVGA3DBLOCKDESC_COMP_TYPELESS,
271 SVGA3DBLOCKDESC_BC2_COMP_UNORM = SVGA3DBLOCKDESC_BC2 |
272 SVGA3DBLOCKDESC_COMP_UNORM,
273 SVGA3DBLOCKDESC_BC2_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_BC2_COMP_UNORM |
274 SVGA3DBLOCKDESC_SRGB,
275 SVGA3DBLOCKDESC_BC3_COMP_TYPELESS = SVGA3DBLOCKDESC_BC3 |
276 SVGA3DBLOCKDESC_COMP_TYPELESS,
277 SVGA3DBLOCKDESC_BC3_COMP_UNORM = SVGA3DBLOCKDESC_BC3 |
278 SVGA3DBLOCKDESC_COMP_UNORM,
279 SVGA3DBLOCKDESC_BC3_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_BC3_COMP_UNORM |
280 SVGA3DBLOCKDESC_SRGB,
281 SVGA3DBLOCKDESC_BC4_COMP_TYPELESS = SVGA3DBLOCKDESC_BC4 |
282 SVGA3DBLOCKDESC_COMP_TYPELESS,
283 SVGA3DBLOCKDESC_BC4_COMP_UNORM = SVGA3DBLOCKDESC_BC4 |
284 SVGA3DBLOCKDESC_COMP_UNORM,
285 SVGA3DBLOCKDESC_BC4_COMP_SNORM = SVGA3DBLOCKDESC_BC4 |
286 SVGA3DBLOCKDESC_COMP_SNORM,
287 SVGA3DBLOCKDESC_BC5_COMP_TYPELESS = SVGA3DBLOCKDESC_BC5 |
288 SVGA3DBLOCKDESC_COMP_TYPELESS,
289 SVGA3DBLOCKDESC_BC5_COMP_UNORM = SVGA3DBLOCKDESC_BC5 |
290 SVGA3DBLOCKDESC_COMP_UNORM,
291 SVGA3DBLOCKDESC_BC5_COMP_SNORM = SVGA3DBLOCKDESC_BC5 |
292 SVGA3DBLOCKDESC_COMP_SNORM,
293
294 SVGA3DBLOCKDESC_NV12 = SVGA3DBLOCKDESC_YUV_VIDEO |
295 SVGA3DBLOCKDESC_PLANAR_YUV |
296 SVGA3DBLOCKDESC_2PLANAR_YUV |
297 SVGA3DBLOCKDESC_COLOR,
298 SVGA3DBLOCKDESC_YV12 = SVGA3DBLOCKDESC_YUV_VIDEO |
299 SVGA3DBLOCKDESC_PLANAR_YUV |
300 SVGA3DBLOCKDESC_3PLANAR_YUV |
301 SVGA3DBLOCKDESC_COLOR,
302
303 SVGA3DBLOCKDESC_DEPTH_UINT = SVGA3DBLOCKDESC_DEPTH |
304 SVGA3DBLOCKDESC_UINT,
305 SVGA3DBLOCKDESC_DEPTH_UNORM = SVGA3DBLOCKDESC_DEPTH_UINT |
306 SVGA3DBLOCKDESC_NORM,
307 SVGA3DBLOCKDESC_DS = SVGA3DBLOCKDESC_DEPTH |
308 SVGA3DBLOCKDESC_STENCIL,
309 SVGA3DBLOCKDESC_DS_UINT = SVGA3DBLOCKDESC_DEPTH |
310 SVGA3DBLOCKDESC_STENCIL |
311 SVGA3DBLOCKDESC_UINT,
312 SVGA3DBLOCKDESC_DS_UNORM = SVGA3DBLOCKDESC_DS_UINT |
313 SVGA3DBLOCKDESC_NORM,
314 SVGA3DBLOCKDESC_DEPTH_FP = SVGA3DBLOCKDESC_DEPTH |
315 SVGA3DBLOCKDESC_FP,
316
317 SVGA3DBLOCKDESC_UV_UINT = SVGA3DBLOCKDESC_UV |
318 SVGA3DBLOCKDESC_UINT,
319 SVGA3DBLOCKDESC_UV_SNORM = SVGA3DBLOCKDESC_UV |
320 SVGA3DBLOCKDESC_SINT |
321 SVGA3DBLOCKDESC_NORM,
322 SVGA3DBLOCKDESC_UVCX_SNORM = SVGA3DBLOCKDESC_UV_SNORM |
323 SVGA3DBLOCKDESC_CX,
324 SVGA3DBLOCKDESC_UVWQ_SNORM = SVGA3DBLOCKDESC_UVWQ |
325 SVGA3DBLOCKDESC_SINT |
326 SVGA3DBLOCKDESC_NORM,
163}; 327};
164 328
165/*
166 * SVGA3dSurfaceDesc describes the actual pixel data.
167 *
168 * This structure provides the following information:
169 * 1. Block description.
170 * 2. Dimensions of a block in the surface.
171 * 3. Size of block in bytes.
172 * 4. Bit depth of the pixel data.
173 * 5. Channel bit depths and masks (if applicable).
174 */
175struct svga3d_channel_def { 329struct svga3d_channel_def {
176 union { 330 union {
177 u8 blue; 331 u8 blue;
178 u8 u; 332 u8 w_bump;
333 u8 l_bump;
179 u8 uv_video; 334 u8 uv_video;
180 u8 u_video; 335 u8 u_video;
181 }; 336 };
182 union { 337 union {
183 u8 green; 338 u8 green;
184 u8 v;
185 u8 stencil; 339 u8 stencil;
340 u8 v_bump;
186 u8 v_video; 341 u8 v_video;
187 }; 342 };
188 union { 343 union {
189 u8 red; 344 u8 red;
190 u8 w; 345 u8 u_bump;
191 u8 luminance; 346 u8 luminance;
192 u8 y; 347 u8 y_video;
193 u8 depth; 348 u8 depth;
194 u8 data; 349 u8 data;
195 }; 350 };
196 union { 351 union {
197 u8 alpha; 352 u8 alpha;
198 u8 q; 353 u8 q_bump;
199 u8 exp; 354 u8 exp;
200 }; 355 };
201}; 356};
202 357
358/*
359 * struct svga3d_surface_desc - describes the actual pixel data.
360 *
361 * @format: Format
362 * @block_desc: Block description
363 * @block_size: Dimensions in pixels of a block
364 * @bytes_per_block: Size of block in bytes
365 * @pitch_bytes_per_block: Size of a block in bytes for purposes of pitch
366 * @bit_depth: Channel bit depths
367 * @bit_offset: Channel bit masks (in bits offset from the start of the pointer)
368 */
203struct svga3d_surface_desc { 369struct svga3d_surface_desc {
204 SVGA3dSurfaceFormat format; 370 SVGA3dSurfaceFormat format;
205 enum svga3d_block_desc block_desc; 371 enum svga3d_block_desc block_desc;
372
206 surf_size_struct block_size; 373 surf_size_struct block_size;
207 u32 bytes_per_block; 374 u32 bytes_per_block;
208 u32 pitch_bytes_per_block; 375 u32 pitch_bytes_per_block;
209 376
210 u32 total_bit_depth;
211 struct svga3d_channel_def bit_depth; 377 struct svga3d_channel_def bit_depth;
212 struct svga3d_channel_def bit_offset; 378 struct svga3d_channel_def bit_offset;
213}; 379};
@@ -215,729 +381,728 @@ struct svga3d_surface_desc {
215static const struct svga3d_surface_desc svga3d_surface_descs[] = { 381static const struct svga3d_surface_desc svga3d_surface_descs[] = {
216 {SVGA3D_FORMAT_INVALID, SVGA3DBLOCKDESC_NONE, 382 {SVGA3D_FORMAT_INVALID, SVGA3DBLOCKDESC_NONE,
217 {1, 1, 1}, 0, 0, 383 {1, 1, 1}, 0, 0,
218 0, {{0}, {0}, {0}, {0}}, 384 {{0}, {0}, {0}, {0}},
219 {{0}, {0}, {0}, {0}}}, 385 {{0}, {0}, {0}, {0}}},
220 386
221 {SVGA3D_X8R8G8B8, SVGA3DBLOCKDESC_RGB, 387 {SVGA3D_X8R8G8B8, SVGA3DBLOCKDESC_RGB_UNORM,
222 {1, 1, 1}, 4, 4, 388 {1, 1, 1}, 4, 4,
223 24, {{8}, {8}, {8}, {0}}, 389 {{8}, {8}, {8}, {0}},
224 {{0}, {8}, {16}, {24}}}, 390 {{0}, {8}, {16}, {24}}},
225 391
226 {SVGA3D_A8R8G8B8, SVGA3DBLOCKDESC_RGBA, 392 {SVGA3D_A8R8G8B8, SVGA3DBLOCKDESC_RGBA_UNORM,
227 {1, 1, 1}, 4, 4, 393 {1, 1, 1}, 4, 4,
228 32, {{8}, {8}, {8}, {8}}, 394 {{8}, {8}, {8}, {8}},
229 {{0}, {8}, {16}, {24}}}, 395 {{0}, {8}, {16}, {24}}},
230 396
231 {SVGA3D_R5G6B5, SVGA3DBLOCKDESC_RGB, 397 {SVGA3D_R5G6B5, SVGA3DBLOCKDESC_RGB_UNORM,
232 {1, 1, 1}, 2, 2, 398 {1, 1, 1}, 2, 2,
233 16, {{5}, {6}, {5}, {0}}, 399 {{5}, {6}, {5}, {0}},
234 {{0}, {5}, {11}, {0}}}, 400 {{0}, {5}, {11}, {0}}},
235 401
236 {SVGA3D_X1R5G5B5, SVGA3DBLOCKDESC_RGB, 402 {SVGA3D_X1R5G5B5, SVGA3DBLOCKDESC_RGB_UNORM,
237 {1, 1, 1}, 2, 2, 403 {1, 1, 1}, 2, 2,
238 15, {{5}, {5}, {5}, {0}}, 404 {{5}, {5}, {5}, {0}},
239 {{0}, {5}, {10}, {0}}}, 405 {{0}, {5}, {10}, {0}}},
240 406
241 {SVGA3D_A1R5G5B5, SVGA3DBLOCKDESC_RGBA, 407 {SVGA3D_A1R5G5B5, SVGA3DBLOCKDESC_RGBA_UNORM,
242 {1, 1, 1}, 2, 2, 408 {1, 1, 1}, 2, 2,
243 16, {{5}, {5}, {5}, {1}}, 409 {{5}, {5}, {5}, {1}},
244 {{0}, {5}, {10}, {15}}}, 410 {{0}, {5}, {10}, {15}}},
245 411
246 {SVGA3D_A4R4G4B4, SVGA3DBLOCKDESC_RGBA, 412 {SVGA3D_A4R4G4B4, SVGA3DBLOCKDESC_RGBA_UNORM,
247 {1, 1, 1}, 2, 2, 413 {1, 1, 1}, 2, 2,
248 16, {{4}, {4}, {4}, {4}}, 414 {{4}, {4}, {4}, {4}},
249 {{0}, {4}, {8}, {12}}}, 415 {{0}, {4}, {8}, {12}}},
250 416
251 {SVGA3D_Z_D32, SVGA3DBLOCKDESC_DEPTH, 417 {SVGA3D_Z_D32, SVGA3DBLOCKDESC_DEPTH_UNORM,
252 {1, 1, 1}, 4, 4, 418 {1, 1, 1}, 4, 4,
253 32, {{0}, {0}, {32}, {0}}, 419 {{0}, {0}, {32}, {0}},
254 {{0}, {0}, {0}, {0}}}, 420 {{0}, {0}, {0}, {0}}},
255 421
256 {SVGA3D_Z_D16, SVGA3DBLOCKDESC_DEPTH, 422 {SVGA3D_Z_D16, SVGA3DBLOCKDESC_DEPTH_UNORM,
257 {1, 1, 1}, 2, 2, 423 {1, 1, 1}, 2, 2,
258 16, {{0}, {0}, {16}, {0}}, 424 {{0}, {0}, {16}, {0}},
259 {{0}, {0}, {0}, {0}}}, 425 {{0}, {0}, {0}, {0}}},
260 426
261 {SVGA3D_Z_D24S8, SVGA3DBLOCKDESC_DS, 427 {SVGA3D_Z_D24S8, SVGA3DBLOCKDESC_DS_UNORM,
262 {1, 1, 1}, 4, 4, 428 {1, 1, 1}, 4, 4,
263 32, {{0}, {8}, {24}, {0}}, 429 {{0}, {8}, {24}, {0}},
264 {{0}, {24}, {0}, {0}}}, 430 {{0}, {0}, {8}, {0}}},
265 431
266 {SVGA3D_Z_D15S1, SVGA3DBLOCKDESC_DS, 432 {SVGA3D_Z_D15S1, SVGA3DBLOCKDESC_DS_UNORM,
267 {1, 1, 1}, 2, 2, 433 {1, 1, 1}, 2, 2,
268 16, {{0}, {1}, {15}, {0}}, 434 {{0}, {1}, {15}, {0}},
269 {{0}, {15}, {0}, {0}}}, 435 {{0}, {0}, {1}, {0}}},
270 436
271 {SVGA3D_LUMINANCE8, SVGA3DBLOCKDESC_LUMINANCE, 437 {SVGA3D_LUMINANCE8, SVGA3DBLOCKDESC_L_UNORM,
272 {1, 1, 1}, 1, 1, 438 {1, 1, 1}, 1, 1,
273 8, {{0}, {0}, {8}, {0}}, 439 {{0}, {0}, {8}, {0}},
274 {{0}, {0}, {0}, {0}}}, 440 {{0}, {0}, {0}, {0}}},
275 441
276 {SVGA3D_LUMINANCE4_ALPHA4, SVGA3DBLOCKDESC_LA, 442 {SVGA3D_LUMINANCE4_ALPHA4, SVGA3DBLOCKDESC_LA_UNORM,
277 {1 , 1, 1}, 1, 1, 443 {1, 1, 1}, 1, 1,
278 8, {{0}, {0}, {4}, {4}}, 444 {{0}, {0}, {4}, {4}},
279 {{0}, {0}, {0}, {4}}}, 445 {{0}, {0}, {0}, {4}}},
280 446
281 {SVGA3D_LUMINANCE16, SVGA3DBLOCKDESC_LUMINANCE, 447 {SVGA3D_LUMINANCE16, SVGA3DBLOCKDESC_L_UNORM,
282 {1, 1, 1}, 2, 2, 448 {1, 1, 1}, 2, 2,
283 16, {{0}, {0}, {16}, {0}}, 449 {{0}, {0}, {16}, {0}},
284 {{0}, {0}, {0}, {0}}}, 450 {{0}, {0}, {0}, {0}}},
285 451
286 {SVGA3D_LUMINANCE8_ALPHA8, SVGA3DBLOCKDESC_LA, 452 {SVGA3D_LUMINANCE8_ALPHA8, SVGA3DBLOCKDESC_LA_UNORM,
287 {1, 1, 1}, 2, 2, 453 {1, 1, 1}, 2, 2,
288 16, {{0}, {0}, {8}, {8}}, 454 {{0}, {0}, {8}, {8}},
289 {{0}, {0}, {0}, {8}}}, 455 {{0}, {0}, {0}, {8}}},
290 456
291 {SVGA3D_DXT1, SVGA3DBLOCKDESC_COMPRESSED, 457 {SVGA3D_DXT1, SVGA3DBLOCKDESC_BC1_COMP_UNORM,
292 {4, 4, 1}, 8, 8, 458 {4, 4, 1}, 8, 8,
293 64, {{0}, {0}, {64}, {0}}, 459 {{0}, {0}, {64}, {0}},
294 {{0}, {0}, {0}, {0}}}, 460 {{0}, {0}, {0}, {0}}},
295 461
296 {SVGA3D_DXT2, SVGA3DBLOCKDESC_COMPRESSED, 462 {SVGA3D_DXT2, SVGA3DBLOCKDESC_BC2_COMP_UNORM,
297 {4, 4, 1}, 16, 16, 463 {4, 4, 1}, 16, 16,
298 128, {{0}, {0}, {128}, {0}}, 464 {{0}, {0}, {128}, {0}},
299 {{0}, {0}, {0}, {0}}}, 465 {{0}, {0}, {0}, {0}}},
300 466
301 {SVGA3D_DXT3, SVGA3DBLOCKDESC_COMPRESSED, 467 {SVGA3D_DXT3, SVGA3DBLOCKDESC_BC2_COMP_UNORM,
302 {4, 4, 1}, 16, 16, 468 {4, 4, 1}, 16, 16,
303 128, {{0}, {0}, {128}, {0}}, 469 {{0}, {0}, {128}, {0}},
304 {{0}, {0}, {0}, {0}}}, 470 {{0}, {0}, {0}, {0}}},
305 471
306 {SVGA3D_DXT4, SVGA3DBLOCKDESC_COMPRESSED, 472 {SVGA3D_DXT4, SVGA3DBLOCKDESC_BC3_COMP_UNORM,
307 {4, 4, 1}, 16, 16, 473 {4, 4, 1}, 16, 16,
308 128, {{0}, {0}, {128}, {0}}, 474 {{0}, {0}, {128}, {0}},
309 {{0}, {0}, {0}, {0}}}, 475 {{0}, {0}, {0}, {0}}},
310 476
311 {SVGA3D_DXT5, SVGA3DBLOCKDESC_COMPRESSED, 477 {SVGA3D_DXT5, SVGA3DBLOCKDESC_BC3_COMP_UNORM,
312 {4, 4, 1}, 16, 16, 478 {4, 4, 1}, 16, 16,
313 128, {{0}, {0}, {128}, {0}}, 479 {{0}, {0}, {128}, {0}},
314 {{0}, {0}, {0}, {0}}}, 480 {{0}, {0}, {0}, {0}}},
315 481
316 {SVGA3D_BUMPU8V8, SVGA3DBLOCKDESC_UV, 482 {SVGA3D_BUMPU8V8, SVGA3DBLOCKDESC_UV_SNORM,
317 {1, 1, 1}, 2, 2, 483 {1, 1, 1}, 2, 2,
318 16, {{0}, {0}, {8}, {8}}, 484 {{0}, {8}, {8}, {0}},
319 {{0}, {0}, {0}, {8}}}, 485 {{0}, {8}, {0}, {0}}},
320 486
321 {SVGA3D_BUMPL6V5U5, SVGA3DBLOCKDESC_UVL, 487 {SVGA3D_BUMPL6V5U5, SVGA3DBLOCKDESC_UVL,
322 {1, 1, 1}, 2, 2, 488 {1, 1, 1}, 2, 2,
323 16, {{5}, {5}, {6}, {0}}, 489 {{6}, {5}, {5}, {0}},
324 {{11}, {6}, {0}, {0}}}, 490 {{10}, {5}, {0}, {0}}},
325 491
326 {SVGA3D_BUMPX8L8V8U8, SVGA3DBLOCKDESC_UVL, 492 {SVGA3D_BUMPX8L8V8U8, SVGA3DBLOCKDESC_UVL,
327 {1, 1, 1}, 4, 4, 493 {1, 1, 1}, 4, 4,
328 32, {{8}, {8}, {8}, {0}}, 494 {{8}, {8}, {8}, {0}},
329 {{16}, {8}, {0}, {0}}}, 495 {{16}, {8}, {0}, {0}}},
330 496
331 {SVGA3D_BUMPL8V8U8, SVGA3DBLOCKDESC_UVL, 497 {SVGA3D_FORMAT_DEAD1, SVGA3DBLOCKDESC_UVL,
332 {1, 1, 1}, 3, 3, 498 {1, 1, 1}, 3, 3,
333 24, {{8}, {8}, {8}, {0}}, 499 {{8}, {8}, {8}, {0}},
334 {{16}, {8}, {0}, {0}}}, 500 {{16}, {8}, {0}, {0}}},
335 501
336 {SVGA3D_ARGB_S10E5, SVGA3DBLOCKDESC_RGBA_FP, 502 {SVGA3D_ARGB_S10E5, SVGA3DBLOCKDESC_RGBA_FP,
337 {1, 1, 1}, 8, 8, 503 {1, 1, 1}, 8, 8,
338 64, {{16}, {16}, {16}, {16}}, 504 {{16}, {16}, {16}, {16}},
339 {{32}, {16}, {0}, {48}}}, 505 {{32}, {16}, {0}, {48}}},
340 506
341 {SVGA3D_ARGB_S23E8, SVGA3DBLOCKDESC_RGBA_FP, 507 {SVGA3D_ARGB_S23E8, SVGA3DBLOCKDESC_RGBA_FP,
342 {1, 1, 1}, 16, 16, 508 {1, 1, 1}, 16, 16,
343 128, {{32}, {32}, {32}, {32}}, 509 {{32}, {32}, {32}, {32}},
344 {{64}, {32}, {0}, {96}}}, 510 {{64}, {32}, {0}, {96}}},
345 511
346 {SVGA3D_A2R10G10B10, SVGA3DBLOCKDESC_RGBA, 512 {SVGA3D_A2R10G10B10, SVGA3DBLOCKDESC_RGBA_UNORM,
347 {1, 1, 1}, 4, 4, 513 {1, 1, 1}, 4, 4,
348 32, {{10}, {10}, {10}, {2}}, 514 {{10}, {10}, {10}, {2}},
349 {{0}, {10}, {20}, {30}}}, 515 {{0}, {10}, {20}, {30}}},
350 516
351 {SVGA3D_V8U8, SVGA3DBLOCKDESC_UV, 517 {SVGA3D_V8U8, SVGA3DBLOCKDESC_UV_SNORM,
352 {1, 1, 1}, 2, 2, 518 {1, 1, 1}, 2, 2,
353 16, {{8}, {8}, {0}, {0}}, 519 {{0}, {8}, {8}, {0}},
354 {{8}, {0}, {0}, {0}}}, 520 {{0}, {8}, {0}, {0}}},
355 521
356 {SVGA3D_Q8W8V8U8, SVGA3DBLOCKDESC_UVWQ, 522 {SVGA3D_Q8W8V8U8, SVGA3DBLOCKDESC_UVWQ_SNORM,
357 {1, 1, 1}, 4, 4, 523 {1, 1, 1}, 4, 4,
358 32, {{8}, {8}, {8}, {8}}, 524 {{8}, {8}, {8}, {8}},
359 {{24}, {16}, {8}, {0}}}, 525 {{16}, {8}, {0}, {24}}},
360 526
361 {SVGA3D_CxV8U8, SVGA3DBLOCKDESC_UV, 527 {SVGA3D_CxV8U8, SVGA3DBLOCKDESC_UVCX_SNORM,
362 {1, 1, 1}, 2, 2, 528 {1, 1, 1}, 2, 2,
363 16, {{8}, {8}, {0}, {0}}, 529 {{0}, {8}, {8}, {0}},
364 {{8}, {0}, {0}, {0}}}, 530 {{0}, {8}, {0}, {0}}},
365 531
366 {SVGA3D_X8L8V8U8, SVGA3DBLOCKDESC_UVL, 532 {SVGA3D_X8L8V8U8, SVGA3DBLOCKDESC_UVL,
367 {1, 1, 1}, 4, 4, 533 {1, 1, 1}, 4, 4,
368 24, {{8}, {8}, {8}, {0}}, 534 {{8}, {8}, {8}, {0}},
369 {{16}, {8}, {0}, {0}}}, 535 {{16}, {8}, {0}, {0}}},
370 536
371 {SVGA3D_A2W10V10U10, SVGA3DBLOCKDESC_UVWA, 537 {SVGA3D_A2W10V10U10, SVGA3DBLOCKDESC_UVWA,
372 {1, 1, 1}, 4, 4, 538 {1, 1, 1}, 4, 4,
373 32, {{10}, {10}, {10}, {2}}, 539 {{10}, {10}, {10}, {2}},
374 {{0}, {10}, {20}, {30}}}, 540 {{20}, {10}, {0}, {30}}},
375 541
376 {SVGA3D_ALPHA8, SVGA3DBLOCKDESC_ALPHA, 542 {SVGA3D_ALPHA8, SVGA3DBLOCKDESC_A_UNORM,
377 {1, 1, 1}, 1, 1, 543 {1, 1, 1}, 1, 1,
378 8, {{0}, {0}, {0}, {8}}, 544 {{0}, {0}, {0}, {8}},
379 {{0}, {0}, {0}, {0}}}, 545 {{0}, {0}, {0}, {0}}},
380 546
381 {SVGA3D_R_S10E5, SVGA3DBLOCKDESC_R_FP, 547 {SVGA3D_R_S10E5, SVGA3DBLOCKDESC_R_FP,
382 {1, 1, 1}, 2, 2, 548 {1, 1, 1}, 2, 2,
383 16, {{0}, {0}, {16}, {0}}, 549 {{0}, {0}, {16}, {0}},
384 {{0}, {0}, {0}, {0}}}, 550 {{0}, {0}, {0}, {0}}},
385 551
386 {SVGA3D_R_S23E8, SVGA3DBLOCKDESC_R_FP, 552 {SVGA3D_R_S23E8, SVGA3DBLOCKDESC_R_FP,
387 {1, 1, 1}, 4, 4, 553 {1, 1, 1}, 4, 4,
388 32, {{0}, {0}, {32}, {0}}, 554 {{0}, {0}, {32}, {0}},
389 {{0}, {0}, {0}, {0}}}, 555 {{0}, {0}, {0}, {0}}},
390 556
391 {SVGA3D_RG_S10E5, SVGA3DBLOCKDESC_RG_FP, 557 {SVGA3D_RG_S10E5, SVGA3DBLOCKDESC_RG_FP,
392 {1, 1, 1}, 4, 4, 558 {1, 1, 1}, 4, 4,
393 32, {{0}, {16}, {16}, {0}}, 559 {{0}, {16}, {16}, {0}},
394 {{0}, {16}, {0}, {0}}}, 560 {{0}, {16}, {0}, {0}}},
395 561
396 {SVGA3D_RG_S23E8, SVGA3DBLOCKDESC_RG_FP, 562 {SVGA3D_RG_S23E8, SVGA3DBLOCKDESC_RG_FP,
397 {1, 1, 1}, 8, 8, 563 {1, 1, 1}, 8, 8,
398 64, {{0}, {32}, {32}, {0}}, 564 {{0}, {32}, {32}, {0}},
399 {{0}, {32}, {0}, {0}}}, 565 {{0}, {32}, {0}, {0}}},
400 566
401 {SVGA3D_BUFFER, SVGA3DBLOCKDESC_BUFFER, 567 {SVGA3D_BUFFER, SVGA3DBLOCKDESC_BUFFER,
402 {1, 1, 1}, 1, 1, 568 {1, 1, 1}, 1, 1,
403 8, {{0}, {0}, {8}, {0}}, 569 {{0}, {0}, {8}, {0}},
404 {{0}, {0}, {0}, {0}}}, 570 {{0}, {0}, {0}, {0}}},
405 571
406 {SVGA3D_Z_D24X8, SVGA3DBLOCKDESC_DEPTH, 572 {SVGA3D_Z_D24X8, SVGA3DBLOCKDESC_DEPTH_UNORM,
407 {1, 1, 1}, 4, 4, 573 {1, 1, 1}, 4, 4,
408 32, {{0}, {0}, {24}, {0}}, 574 {{0}, {0}, {24}, {0}},
409 {{0}, {24}, {0}, {0}}}, 575 {{0}, {0}, {8}, {0}}},
410 576
411 {SVGA3D_V16U16, SVGA3DBLOCKDESC_UV, 577 {SVGA3D_V16U16, SVGA3DBLOCKDESC_UV_SNORM,
412 {1, 1, 1}, 4, 4, 578 {1, 1, 1}, 4, 4,
413 32, {{16}, {16}, {0}, {0}}, 579 {{0}, {16}, {16}, {0}},
414 {{16}, {0}, {0}, {0}}}, 580 {{0}, {16}, {0}, {0}}},
415 581
416 {SVGA3D_G16R16, SVGA3DBLOCKDESC_RG, 582 {SVGA3D_G16R16, SVGA3DBLOCKDESC_RG_UNORM,
417 {1, 1, 1}, 4, 4, 583 {1, 1, 1}, 4, 4,
418 32, {{0}, {16}, {16}, {0}}, 584 {{0}, {16}, {16}, {0}},
419 {{0}, {0}, {16}, {0}}}, 585 {{0}, {16}, {0}, {0}}},
420 586
421 {SVGA3D_A16B16G16R16, SVGA3DBLOCKDESC_RGBA, 587 {SVGA3D_A16B16G16R16, SVGA3DBLOCKDESC_RGBA_UNORM,
422 {1, 1, 1}, 8, 8, 588 {1, 1, 1}, 8, 8,
423 64, {{16}, {16}, {16}, {16}}, 589 {{16}, {16}, {16}, {16}},
424 {{32}, {16}, {0}, {48}}}, 590 {{32}, {16}, {0}, {48}}},
425 591
426 {SVGA3D_UYVY, SVGA3DBLOCKDESC_YUV, 592 {SVGA3D_UYVY, SVGA3DBLOCKDESC_YUV,
427 {1, 1, 1}, 2, 2, 593 {2, 1, 1}, 4, 4,
428 16, {{8}, {0}, {8}, {0}}, 594 {{8}, {0}, {8}, {0}},
429 {{0}, {0}, {8}, {0}}}, 595 {{0}, {0}, {8}, {0}}},
430 596
431 {SVGA3D_YUY2, SVGA3DBLOCKDESC_YUV, 597 {SVGA3D_YUY2, SVGA3DBLOCKDESC_YUV,
432 {1, 1, 1}, 2, 2, 598 {2, 1, 1}, 4, 4,
433 16, {{8}, {0}, {8}, {0}}, 599 {{8}, {0}, {8}, {0}},
434 {{8}, {0}, {0}, {0}}}, 600 {{8}, {0}, {0}, {0}}},
435 601
436 {SVGA3D_NV12, SVGA3DBLOCKDESC_NV12, 602 {SVGA3D_NV12, SVGA3DBLOCKDESC_NV12,
437 {2, 2, 1}, 6, 2, 603 {2, 2, 1}, 6, 2,
438 48, {{0}, {0}, {48}, {0}}, 604 {{0}, {0}, {48}, {0}},
439 {{0}, {0}, {0}, {0}}}, 605 {{0}, {0}, {0}, {0}}},
440 606
441 {SVGA3D_AYUV, SVGA3DBLOCKDESC_AYUV, 607 {SVGA3D_AYUV, SVGA3DBLOCKDESC_AYUV,
442 {1, 1, 1}, 4, 4, 608 {1, 1, 1}, 4, 4,
443 32, {{8}, {8}, {8}, {8}}, 609 {{8}, {8}, {8}, {8}},
444 {{0}, {8}, {16}, {24}}}, 610 {{0}, {8}, {16}, {24}}},
445 611
446 {SVGA3D_R32G32B32A32_TYPELESS, SVGA3DBLOCKDESC_RGBA, 612 {SVGA3D_R32G32B32A32_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
447 {1, 1, 1}, 16, 16, 613 {1, 1, 1}, 16, 16,
448 128, {{32}, {32}, {32}, {32}}, 614 {{32}, {32}, {32}, {32}},
449 {{64}, {32}, {0}, {96}}}, 615 {{64}, {32}, {0}, {96}}},
450 616
451 {SVGA3D_R32G32B32A32_UINT, SVGA3DBLOCKDESC_RGBA, 617 {SVGA3D_R32G32B32A32_UINT, SVGA3DBLOCKDESC_RGBA_UINT,
452 {1, 1, 1}, 16, 16, 618 {1, 1, 1}, 16, 16,
453 128, {{32}, {32}, {32}, {32}}, 619 {{32}, {32}, {32}, {32}},
454 {{64}, {32}, {0}, {96}}}, 620 {{64}, {32}, {0}, {96}}},
455 621
456 {SVGA3D_R32G32B32A32_SINT, SVGA3DBLOCKDESC_UVWQ, 622 {SVGA3D_R32G32B32A32_SINT, SVGA3DBLOCKDESC_RGBA_SINT,
457 {1, 1, 1}, 16, 16, 623 {1, 1, 1}, 16, 16,
458 128, {{32}, {32}, {32}, {32}}, 624 {{32}, {32}, {32}, {32}},
459 {{64}, {32}, {0}, {96}}}, 625 {{64}, {32}, {0}, {96}}},
460 626
461 {SVGA3D_R32G32B32_TYPELESS, SVGA3DBLOCKDESC_RGB, 627 {SVGA3D_R32G32B32_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
462 {1, 1, 1}, 12, 12, 628 {1, 1, 1}, 12, 12,
463 96, {{32}, {32}, {32}, {0}}, 629 {{32}, {32}, {32}, {0}},
464 {{64}, {32}, {0}, {0}}}, 630 {{64}, {32}, {0}, {0}}},
465 631
466 {SVGA3D_R32G32B32_FLOAT, SVGA3DBLOCKDESC_RGB_FP, 632 {SVGA3D_R32G32B32_FLOAT, SVGA3DBLOCKDESC_RGB_FP,
467 {1, 1, 1}, 12, 12, 633 {1, 1, 1}, 12, 12,
468 96, {{32}, {32}, {32}, {0}}, 634 {{32}, {32}, {32}, {0}},
469 {{64}, {32}, {0}, {0}}}, 635 {{64}, {32}, {0}, {0}}},
470 636
471 {SVGA3D_R32G32B32_UINT, SVGA3DBLOCKDESC_RGB, 637 {SVGA3D_R32G32B32_UINT, SVGA3DBLOCKDESC_RGB_UINT,
472 {1, 1, 1}, 12, 12, 638 {1, 1, 1}, 12, 12,
473 96, {{32}, {32}, {32}, {0}}, 639 {{32}, {32}, {32}, {0}},
474 {{64}, {32}, {0}, {0}}}, 640 {{64}, {32}, {0}, {0}}},
475 641
476 {SVGA3D_R32G32B32_SINT, SVGA3DBLOCKDESC_UVW, 642 {SVGA3D_R32G32B32_SINT, SVGA3DBLOCKDESC_RGB_SINT,
477 {1, 1, 1}, 12, 12, 643 {1, 1, 1}, 12, 12,
478 96, {{32}, {32}, {32}, {0}}, 644 {{32}, {32}, {32}, {0}},
479 {{64}, {32}, {0}, {0}}}, 645 {{64}, {32}, {0}, {0}}},
480 646
481 {SVGA3D_R16G16B16A16_TYPELESS, SVGA3DBLOCKDESC_RGBA, 647 {SVGA3D_R16G16B16A16_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
482 {1, 1, 1}, 8, 8, 648 {1, 1, 1}, 8, 8,
483 64, {{16}, {16}, {16}, {16}}, 649 {{16}, {16}, {16}, {16}},
484 {{32}, {16}, {0}, {48}}}, 650 {{32}, {16}, {0}, {48}}},
485 651
486 {SVGA3D_R16G16B16A16_UINT, SVGA3DBLOCKDESC_RGBA, 652 {SVGA3D_R16G16B16A16_UINT, SVGA3DBLOCKDESC_RGBA_UINT,
487 {1, 1, 1}, 8, 8, 653 {1, 1, 1}, 8, 8,
488 64, {{16}, {16}, {16}, {16}}, 654 {{16}, {16}, {16}, {16}},
489 {{32}, {16}, {0}, {48}}}, 655 {{32}, {16}, {0}, {48}}},
490 656
491 {SVGA3D_R16G16B16A16_SNORM, SVGA3DBLOCKDESC_UVWQ, 657 {SVGA3D_R16G16B16A16_SNORM, SVGA3DBLOCKDESC_RGBA_SNORM,
492 {1, 1, 1}, 8, 8, 658 {1, 1, 1}, 8, 8,
493 64, {{16}, {16}, {16}, {16}}, 659 {{16}, {16}, {16}, {16}},
494 {{32}, {16}, {0}, {48}}}, 660 {{32}, {16}, {0}, {48}}},
495 661
496 {SVGA3D_R16G16B16A16_SINT, SVGA3DBLOCKDESC_UVWQ, 662 {SVGA3D_R16G16B16A16_SINT, SVGA3DBLOCKDESC_RGBA_SINT,
497 {1, 1, 1}, 8, 8, 663 {1, 1, 1}, 8, 8,
498 64, {{16}, {16}, {16}, {16}}, 664 {{16}, {16}, {16}, {16}},
499 {{32}, {16}, {0}, {48}}}, 665 {{32}, {16}, {0}, {48}}},
500 666
501 {SVGA3D_R32G32_TYPELESS, SVGA3DBLOCKDESC_RG, 667 {SVGA3D_R32G32_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
502 {1, 1, 1}, 8, 8, 668 {1, 1, 1}, 8, 8,
503 64, {{0}, {32}, {32}, {0}}, 669 {{0}, {32}, {32}, {0}},
504 {{0}, {32}, {0}, {0}}}, 670 {{0}, {32}, {0}, {0}}},
505 671
506 {SVGA3D_R32G32_UINT, SVGA3DBLOCKDESC_RG, 672 {SVGA3D_R32G32_UINT, SVGA3DBLOCKDESC_RG_UINT,
507 {1, 1, 1}, 8, 8, 673 {1, 1, 1}, 8, 8,
508 64, {{0}, {32}, {32}, {0}}, 674 {{0}, {32}, {32}, {0}},
509 {{0}, {32}, {0}, {0}}}, 675 {{0}, {32}, {0}, {0}}},
510 676
511 {SVGA3D_R32G32_SINT, SVGA3DBLOCKDESC_UV, 677 {SVGA3D_R32G32_SINT, SVGA3DBLOCKDESC_RG_SINT,
512 {1, 1, 1}, 8, 8, 678 {1, 1, 1}, 8, 8,
513 64, {{0}, {32}, {32}, {0}}, 679 {{0}, {32}, {32}, {0}},
514 {{0}, {32}, {0}, {0}}}, 680 {{0}, {32}, {0}, {0}}},
515 681
516 {SVGA3D_R32G8X24_TYPELESS, SVGA3DBLOCKDESC_RG, 682 {SVGA3D_R32G8X24_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
517 {1, 1, 1}, 8, 8, 683 {1, 1, 1}, 8, 8,
518 64, {{0}, {8}, {32}, {0}}, 684 {{0}, {8}, {32}, {0}},
519 {{0}, {32}, {0}, {0}}}, 685 {{0}, {32}, {0}, {0}}},
520 686
521 {SVGA3D_D32_FLOAT_S8X24_UINT, SVGA3DBLOCKDESC_DS, 687 {SVGA3D_D32_FLOAT_S8X24_UINT, SVGA3DBLOCKDESC_DS,
522 {1, 1, 1}, 8, 8, 688 {1, 1, 1}, 8, 8,
523 64, {{0}, {8}, {32}, {0}}, 689 {{0}, {8}, {32}, {0}},
524 {{0}, {32}, {0}, {0}}}, 690 {{0}, {32}, {0}, {0}}},
525 691
526 {SVGA3D_R32_FLOAT_X8X24_TYPELESS, SVGA3DBLOCKDESC_R_FP, 692 {SVGA3D_R32_FLOAT_X8X24, SVGA3DBLOCKDESC_R_FP,
527 {1, 1, 1}, 8, 8, 693 {1, 1, 1}, 8, 8,
528 64, {{0}, {0}, {32}, {0}}, 694 {{0}, {0}, {32}, {0}},
529 {{0}, {0}, {0}, {0}}}, 695 {{0}, {0}, {0}, {0}}},
530 696
531 {SVGA3D_X32_TYPELESS_G8X24_UINT, SVGA3DBLOCKDESC_GREEN, 697 {SVGA3D_X32_G8X24_UINT, SVGA3DBLOCKDESC_G_UINT,
532 {1, 1, 1}, 8, 8, 698 {1, 1, 1}, 8, 8,
533 64, {{0}, {8}, {0}, {0}}, 699 {{0}, {8}, {0}, {0}},
534 {{0}, {32}, {0}, {0}}}, 700 {{0}, {32}, {0}, {0}}},
535 701
536 {SVGA3D_R10G10B10A2_TYPELESS, SVGA3DBLOCKDESC_RGBA, 702 {SVGA3D_R10G10B10A2_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
537 {1, 1, 1}, 4, 4, 703 {1, 1, 1}, 4, 4,
538 32, {{10}, {10}, {10}, {2}}, 704 {{10}, {10}, {10}, {2}},
539 {{0}, {10}, {20}, {30}}}, 705 {{20}, {10}, {0}, {30}}},
540 706
541 {SVGA3D_R10G10B10A2_UINT, SVGA3DBLOCKDESC_RGBA, 707 {SVGA3D_R10G10B10A2_UINT, SVGA3DBLOCKDESC_RGBA_UINT,
542 {1, 1, 1}, 4, 4, 708 {1, 1, 1}, 4, 4,
543 32, {{10}, {10}, {10}, {2}}, 709 {{10}, {10}, {10}, {2}},
544 {{0}, {10}, {20}, {30}}}, 710 {{20}, {10}, {0}, {30}}},
545 711
546 {SVGA3D_R11G11B10_FLOAT, SVGA3DBLOCKDESC_RGB_FP, 712 {SVGA3D_R11G11B10_FLOAT, SVGA3DBLOCKDESC_RGB_FP,
547 {1, 1, 1}, 4, 4, 713 {1, 1, 1}, 4, 4,
548 32, {{10}, {11}, {11}, {0}}, 714 {{10}, {11}, {11}, {0}},
549 {{0}, {10}, {21}, {0}}}, 715 {{22}, {11}, {0}, {0}}},
550 716
551 {SVGA3D_R8G8B8A8_TYPELESS, SVGA3DBLOCKDESC_RGBA, 717 {SVGA3D_R8G8B8A8_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
552 {1, 1, 1}, 4, 4, 718 {1, 1, 1}, 4, 4,
553 32, {{8}, {8}, {8}, {8}}, 719 {{8}, {8}, {8}, {8}},
554 {{16}, {8}, {0}, {24}}}, 720 {{16}, {8}, {0}, {24}}},
555 721
556 {SVGA3D_R8G8B8A8_UNORM, SVGA3DBLOCKDESC_RGBA, 722 {SVGA3D_R8G8B8A8_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM,
557 {1, 1, 1}, 4, 4, 723 {1, 1, 1}, 4, 4,
558 32, {{8}, {8}, {8}, {8}}, 724 {{8}, {8}, {8}, {8}},
559 {{16}, {8}, {0}, {24}}}, 725 {{16}, {8}, {0}, {24}}},
560 726
561 {SVGA3D_R8G8B8A8_UNORM_SRGB, SVGA3DBLOCKDESC_RGBA_SRGB, 727 {SVGA3D_R8G8B8A8_UNORM_SRGB, SVGA3DBLOCKDESC_RGBA_UNORM_SRGB,
562 {1, 1, 1}, 4, 4, 728 {1, 1, 1}, 4, 4,
563 32, {{8}, {8}, {8}, {8}}, 729 {{8}, {8}, {8}, {8}},
564 {{16}, {8}, {0}, {24}}}, 730 {{16}, {8}, {0}, {24}}},
565 731
566 {SVGA3D_R8G8B8A8_UINT, SVGA3DBLOCKDESC_RGBA, 732 {SVGA3D_R8G8B8A8_UINT, SVGA3DBLOCKDESC_RGBA_UINT,
567 {1, 1, 1}, 4, 4, 733 {1, 1, 1}, 4, 4,
568 32, {{8}, {8}, {8}, {8}}, 734 {{8}, {8}, {8}, {8}},
569 {{16}, {8}, {0}, {24}}}, 735 {{16}, {8}, {0}, {24}}},
570 736
571 {SVGA3D_R8G8B8A8_SINT, SVGA3DBLOCKDESC_RGBA, 737 {SVGA3D_R8G8B8A8_SINT, SVGA3DBLOCKDESC_RGBA_SINT,
572 {1, 1, 1}, 4, 4, 738 {1, 1, 1}, 4, 4,
573 32, {{8}, {8}, {8}, {8}}, 739 {{8}, {8}, {8}, {8}},
574 {{16}, {8}, {0}, {24}}}, 740 {{16}, {8}, {0}, {24}}},
575 741
576 {SVGA3D_R16G16_TYPELESS, SVGA3DBLOCKDESC_RG, 742 {SVGA3D_R16G16_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
577 {1, 1, 1}, 4, 4, 743 {1, 1, 1}, 4, 4,
578 32, {{0}, {16}, {16}, {0}}, 744 {{0}, {16}, {16}, {0}},
579 {{0}, {16}, {0}, {0}}}, 745 {{0}, {16}, {0}, {0}}},
580 746
581 {SVGA3D_R16G16_UINT, SVGA3DBLOCKDESC_RG_FP, 747 {SVGA3D_R16G16_UINT, SVGA3DBLOCKDESC_RG_UINT,
582 {1, 1, 1}, 4, 4, 748 {1, 1, 1}, 4, 4,
583 32, {{0}, {16}, {16}, {0}}, 749 {{0}, {16}, {16}, {0}},
584 {{0}, {16}, {0}, {0}}}, 750 {{0}, {16}, {0}, {0}}},
585 751
586 {SVGA3D_R16G16_SINT, SVGA3DBLOCKDESC_UV, 752 {SVGA3D_R16G16_SINT, SVGA3DBLOCKDESC_RG_SINT,
587 {1, 1, 1}, 4, 4, 753 {1, 1, 1}, 4, 4,
588 32, {{0}, {16}, {16}, {0}}, 754 {{0}, {16}, {16}, {0}},
589 {{0}, {16}, {0}, {0}}}, 755 {{0}, {16}, {0}, {0}}},
590 756
591 {SVGA3D_R32_TYPELESS, SVGA3DBLOCKDESC_RED, 757 {SVGA3D_R32_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
592 {1, 1, 1}, 4, 4, 758 {1, 1, 1}, 4, 4,
593 32, {{0}, {0}, {32}, {0}}, 759 {{0}, {0}, {32}, {0}},
594 {{0}, {0}, {0}, {0}}}, 760 {{0}, {0}, {0}, {0}}},
595 761
596 {SVGA3D_D32_FLOAT, SVGA3DBLOCKDESC_DEPTH, 762 {SVGA3D_D32_FLOAT, SVGA3DBLOCKDESC_DEPTH_FP,
597 {1, 1, 1}, 4, 4, 763 {1, 1, 1}, 4, 4,
598 32, {{0}, {0}, {32}, {0}}, 764 {{0}, {0}, {32}, {0}},
599 {{0}, {0}, {0}, {0}}}, 765 {{0}, {0}, {0}, {0}}},
600 766
601 {SVGA3D_R32_UINT, SVGA3DBLOCKDESC_RED, 767 {SVGA3D_R32_UINT, SVGA3DBLOCKDESC_R_UINT,
602 {1, 1, 1}, 4, 4, 768 {1, 1, 1}, 4, 4,
603 32, {{0}, {0}, {32}, {0}}, 769 {{0}, {0}, {32}, {0}},
604 {{0}, {0}, {0}, {0}}}, 770 {{0}, {0}, {0}, {0}}},
605 771
606 {SVGA3D_R32_SINT, SVGA3DBLOCKDESC_RED, 772 {SVGA3D_R32_SINT, SVGA3DBLOCKDESC_R_SINT,
607 {1, 1, 1}, 4, 4, 773 {1, 1, 1}, 4, 4,
608 32, {{0}, {0}, {32}, {0}}, 774 {{0}, {0}, {32}, {0}},
609 {{0}, {0}, {0}, {0}}}, 775 {{0}, {0}, {0}, {0}}},
610 776
611 {SVGA3D_R24G8_TYPELESS, SVGA3DBLOCKDESC_RG, 777 {SVGA3D_R24G8_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
612 {1, 1, 1}, 4, 4, 778 {1, 1, 1}, 4, 4,
613 32, {{0}, {8}, {24}, {0}}, 779 {{0}, {8}, {24}, {0}},
614 {{0}, {24}, {0}, {0}}}, 780 {{0}, {24}, {0}, {0}}},
615 781
616 {SVGA3D_D24_UNORM_S8_UINT, SVGA3DBLOCKDESC_DS, 782 {SVGA3D_D24_UNORM_S8_UINT, SVGA3DBLOCKDESC_DS_UNORM,
617 {1, 1, 1}, 4, 4, 783 {1, 1, 1}, 4, 4,
618 32, {{0}, {8}, {24}, {0}}, 784 {{0}, {8}, {24}, {0}},
619 {{0}, {24}, {0}, {0}}}, 785 {{0}, {24}, {0}, {0}}},
620 786
621 {SVGA3D_R24_UNORM_X8_TYPELESS, SVGA3DBLOCKDESC_RED, 787 {SVGA3D_R24_UNORM_X8, SVGA3DBLOCKDESC_R_UNORM,
622 {1, 1, 1}, 4, 4, 788 {1, 1, 1}, 4, 4,
623 32, {{0}, {0}, {24}, {0}}, 789 {{0}, {0}, {24}, {0}},
624 {{0}, {0}, {0}, {0}}}, 790 {{0}, {0}, {0}, {0}}},
625 791
626 {SVGA3D_X24_TYPELESS_G8_UINT, SVGA3DBLOCKDESC_GREEN, 792 {SVGA3D_X24_G8_UINT, SVGA3DBLOCKDESC_G_UINT,
627 {1, 1, 1}, 4, 4, 793 {1, 1, 1}, 4, 4,
628 32, {{0}, {8}, {0}, {0}}, 794 {{0}, {8}, {0}, {0}},
629 {{0}, {24}, {0}, {0}}}, 795 {{0}, {24}, {0}, {0}}},
630 796
631 {SVGA3D_R8G8_TYPELESS, SVGA3DBLOCKDESC_RG, 797 {SVGA3D_R8G8_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
632 {1, 1, 1}, 2, 2, 798 {1, 1, 1}, 2, 2,
633 16, {{0}, {8}, {8}, {0}}, 799 {{0}, {8}, {8}, {0}},
634 {{0}, {8}, {0}, {0}}}, 800 {{0}, {8}, {0}, {0}}},
635 801
636 {SVGA3D_R8G8_UNORM, SVGA3DBLOCKDESC_RG, 802 {SVGA3D_R8G8_UNORM, SVGA3DBLOCKDESC_RG_UNORM,
637 {1, 1, 1}, 2, 2, 803 {1, 1, 1}, 2, 2,
638 16, {{0}, {8}, {8}, {0}}, 804 {{0}, {8}, {8}, {0}},
639 {{0}, {8}, {0}, {0}}}, 805 {{0}, {8}, {0}, {0}}},
640 806
641 {SVGA3D_R8G8_UINT, SVGA3DBLOCKDESC_RG, 807 {SVGA3D_R8G8_UINT, SVGA3DBLOCKDESC_RG_UINT,
642 {1, 1, 1}, 2, 2, 808 {1, 1, 1}, 2, 2,
643 16, {{0}, {8}, {8}, {0}}, 809 {{0}, {8}, {8}, {0}},
644 {{0}, {8}, {0}, {0}}}, 810 {{0}, {8}, {0}, {0}}},
645 811
646 {SVGA3D_R8G8_SINT, SVGA3DBLOCKDESC_UV, 812 {SVGA3D_R8G8_SINT, SVGA3DBLOCKDESC_RG_SINT,
647 {1, 1, 1}, 2, 2, 813 {1, 1, 1}, 2, 2,
648 16, {{0}, {8}, {8}, {0}}, 814 {{0}, {8}, {8}, {0}},
649 {{0}, {8}, {0}, {0}}}, 815 {{0}, {8}, {0}, {0}}},
650 816
651 {SVGA3D_R16_TYPELESS, SVGA3DBLOCKDESC_RED, 817 {SVGA3D_R16_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
652 {1, 1, 1}, 2, 2, 818 {1, 1, 1}, 2, 2,
653 16, {{0}, {0}, {16}, {0}}, 819 {{0}, {0}, {16}, {0}},
654 {{0}, {0}, {0}, {0}}}, 820 {{0}, {0}, {0}, {0}}},
655 821
656 {SVGA3D_R16_UNORM, SVGA3DBLOCKDESC_RED, 822 {SVGA3D_R16_UNORM, SVGA3DBLOCKDESC_R_UNORM,
657 {1, 1, 1}, 2, 2, 823 {1, 1, 1}, 2, 2,
658 16, {{0}, {0}, {16}, {0}}, 824 {{0}, {0}, {16}, {0}},
659 {{0}, {0}, {0}, {0}}}, 825 {{0}, {0}, {0}, {0}}},
660 826
661 {SVGA3D_R16_UINT, SVGA3DBLOCKDESC_RED, 827 {SVGA3D_R16_UINT, SVGA3DBLOCKDESC_R_UINT,
662 {1, 1, 1}, 2, 2, 828 {1, 1, 1}, 2, 2,
663 16, {{0}, {0}, {16}, {0}}, 829 {{0}, {0}, {16}, {0}},
664 {{0}, {0}, {0}, {0}}}, 830 {{0}, {0}, {0}, {0}}},
665 831
666 {SVGA3D_R16_SNORM, SVGA3DBLOCKDESC_U, 832 {SVGA3D_R16_SNORM, SVGA3DBLOCKDESC_R_SNORM,
667 {1, 1, 1}, 2, 2, 833 {1, 1, 1}, 2, 2,
668 16, {{0}, {0}, {16}, {0}}, 834 {{0}, {0}, {16}, {0}},
669 {{0}, {0}, {0}, {0}}}, 835 {{0}, {0}, {0}, {0}}},
670 836
671 {SVGA3D_R16_SINT, SVGA3DBLOCKDESC_U, 837 {SVGA3D_R16_SINT, SVGA3DBLOCKDESC_R_SINT,
672 {1, 1, 1}, 2, 2, 838 {1, 1, 1}, 2, 2,
673 16, {{0}, {0}, {16}, {0}}, 839 {{0}, {0}, {16}, {0}},
674 {{0}, {0}, {0}, {0}}}, 840 {{0}, {0}, {0}, {0}}},
675 841
676 {SVGA3D_R8_TYPELESS, SVGA3DBLOCKDESC_RED, 842 {SVGA3D_R8_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
677 {1, 1, 1}, 1, 1, 843 {1, 1, 1}, 1, 1,
678 8, {{0}, {0}, {8}, {0}}, 844 {{0}, {0}, {8}, {0}},
679 {{0}, {0}, {0}, {0}}}, 845 {{0}, {0}, {0}, {0}}},
680 846
681 {SVGA3D_R8_UNORM, SVGA3DBLOCKDESC_RED, 847 {SVGA3D_R8_UNORM, SVGA3DBLOCKDESC_R_UNORM,
682 {1, 1, 1}, 1, 1, 848 {1, 1, 1}, 1, 1,
683 8, {{0}, {0}, {8}, {0}}, 849 {{0}, {0}, {8}, {0}},
684 {{0}, {0}, {0}, {0}}}, 850 {{0}, {0}, {0}, {0}}},
685 851
686 {SVGA3D_R8_UINT, SVGA3DBLOCKDESC_RED, 852 {SVGA3D_R8_UINT, SVGA3DBLOCKDESC_R_UINT,
687 {1, 1, 1}, 1, 1, 853 {1, 1, 1}, 1, 1,
688 8, {{0}, {0}, {8}, {0}}, 854 {{0}, {0}, {8}, {0}},
689 {{0}, {0}, {0}, {0}}}, 855 {{0}, {0}, {0}, {0}}},
690 856
691 {SVGA3D_R8_SNORM, SVGA3DBLOCKDESC_U, 857 {SVGA3D_R8_SNORM, SVGA3DBLOCKDESC_R_SNORM,
692 {1, 1, 1}, 1, 1, 858 {1, 1, 1}, 1, 1,
693 8, {{0}, {0}, {8}, {0}}, 859 {{0}, {0}, {8}, {0}},
694 {{0}, {0}, {0}, {0}}}, 860 {{0}, {0}, {0}, {0}}},
695 861
696 {SVGA3D_R8_SINT, SVGA3DBLOCKDESC_U, 862 {SVGA3D_R8_SINT, SVGA3DBLOCKDESC_R_SINT,
697 {1, 1, 1}, 1, 1, 863 {1, 1, 1}, 1, 1,
698 8, {{0}, {0}, {8}, {0}}, 864 {{0}, {0}, {8}, {0}},
699 {{0}, {0}, {0}, {0}}}, 865 {{0}, {0}, {0}, {0}}},
700 866
701 {SVGA3D_P8, SVGA3DBLOCKDESC_RED, 867 {SVGA3D_P8, SVGA3DBLOCKDESC_NONE,
702 {1, 1, 1}, 1, 1, 868 {1, 1, 1}, 1, 1,
703 8, {{0}, {0}, {8}, {0}}, 869 {{0}, {0}, {8}, {0}},
704 {{0}, {0}, {0}, {0}}}, 870 {{0}, {0}, {0}, {0}}},
705 871
706 {SVGA3D_R9G9B9E5_SHAREDEXP, SVGA3DBLOCKDESC_RGBE, 872 {SVGA3D_R9G9B9E5_SHAREDEXP, SVGA3DBLOCKDESC_RGB_EXP,
707 {1, 1, 1}, 4, 4, 873 {1, 1, 1}, 4, 4,
708 32, {{9}, {9}, {9}, {5}}, 874 {{9}, {9}, {9}, {5}},
709 {{18}, {9}, {0}, {27}}}, 875 {{18}, {9}, {0}, {27}}},
710 876
711 {SVGA3D_R8G8_B8G8_UNORM, SVGA3DBLOCKDESC_RG, 877 {SVGA3D_R8G8_B8G8_UNORM, SVGA3DBLOCKDESC_NONE,
712 {1, 1, 1}, 2, 2, 878 {2, 1, 1}, 4, 4,
713 16, {{0}, {8}, {8}, {0}}, 879 {{0}, {8}, {8}, {0}},
714 {{0}, {8}, {0}, {0}}}, 880 {{0}, {0}, {8}, {0}}},
715 881
716 {SVGA3D_G8R8_G8B8_UNORM, SVGA3DBLOCKDESC_RG, 882 {SVGA3D_G8R8_G8B8_UNORM, SVGA3DBLOCKDESC_NONE,
717 {1, 1, 1}, 2, 2, 883 {2, 1, 1}, 4, 4,
718 16, {{0}, {8}, {8}, {0}}, 884 {{0}, {8}, {8}, {0}},
719 {{0}, {8}, {0}, {0}}}, 885 {{0}, {8}, {0}, {0}}},
720 886
721 {SVGA3D_BC1_TYPELESS, SVGA3DBLOCKDESC_COMPRESSED, 887 {SVGA3D_BC1_TYPELESS, SVGA3DBLOCKDESC_BC1_COMP_TYPELESS,
722 {4, 4, 1}, 8, 8, 888 {4, 4, 1}, 8, 8,
723 64, {{0}, {0}, {64}, {0}}, 889 {{0}, {0}, {64}, {0}},
724 {{0}, {0}, {0}, {0}}}, 890 {{0}, {0}, {0}, {0}}},
725 891
726 {SVGA3D_BC1_UNORM_SRGB, SVGA3DBLOCKDESC_COMPRESSED_SRGB, 892 {SVGA3D_BC1_UNORM_SRGB, SVGA3DBLOCKDESC_BC1_COMP_UNORM_SRGB,
727 {4, 4, 1}, 8, 8, 893 {4, 4, 1}, 8, 8,
728 64, {{0}, {0}, {64}, {0}}, 894 {{0}, {0}, {64}, {0}},
729 {{0}, {0}, {0}, {0}}}, 895 {{0}, {0}, {0}, {0}}},
730 896
731 {SVGA3D_BC2_TYPELESS, SVGA3DBLOCKDESC_COMPRESSED, 897 {SVGA3D_BC2_TYPELESS, SVGA3DBLOCKDESC_BC2_COMP_TYPELESS,
732 {4, 4, 1}, 16, 16, 898 {4, 4, 1}, 16, 16,
733 128, {{0}, {0}, {128}, {0}}, 899 {{0}, {0}, {128}, {0}},
734 {{0}, {0}, {0}, {0}}}, 900 {{0}, {0}, {0}, {0}}},
735 901
736 {SVGA3D_BC2_UNORM_SRGB, SVGA3DBLOCKDESC_COMPRESSED_SRGB, 902 {SVGA3D_BC2_UNORM_SRGB, SVGA3DBLOCKDESC_BC2_COMP_UNORM_SRGB,
737 {4, 4, 1}, 16, 16, 903 {4, 4, 1}, 16, 16,
738 128, {{0}, {0}, {128}, {0}}, 904 {{0}, {0}, {128}, {0}},
739 {{0}, {0}, {0}, {0}}}, 905 {{0}, {0}, {0}, {0}}},
740 906
741 {SVGA3D_BC3_TYPELESS, SVGA3DBLOCKDESC_COMPRESSED, 907 {SVGA3D_BC3_TYPELESS, SVGA3DBLOCKDESC_BC3_COMP_TYPELESS,
742 {4, 4, 1}, 16, 16, 908 {4, 4, 1}, 16, 16,
743 128, {{0}, {0}, {128}, {0}}, 909 {{0}, {0}, {128}, {0}},
744 {{0}, {0}, {0}, {0}}}, 910 {{0}, {0}, {0}, {0}}},
745 911
746 {SVGA3D_BC3_UNORM_SRGB, SVGA3DBLOCKDESC_COMPRESSED_SRGB, 912 {SVGA3D_BC3_UNORM_SRGB, SVGA3DBLOCKDESC_BC3_COMP_UNORM_SRGB,
747 {4, 4, 1}, 16, 16, 913 {4, 4, 1}, 16, 16,
748 128, {{0}, {0}, {128}, {0}}, 914 {{0}, {0}, {128}, {0}},
749 {{0}, {0}, {0}, {0}}}, 915 {{0}, {0}, {0}, {0}}},
750 916
751 {SVGA3D_BC4_TYPELESS, SVGA3DBLOCKDESC_COMPRESSED, 917 {SVGA3D_BC4_TYPELESS, SVGA3DBLOCKDESC_BC4_COMP_TYPELESS,
752 {4, 4, 1}, 8, 8, 918 {4, 4, 1}, 8, 8,
753 64, {{0}, {0}, {64}, {0}}, 919 {{0}, {0}, {64}, {0}},
754 {{0}, {0}, {0}, {0}}}, 920 {{0}, {0}, {0}, {0}}},
755 921
756 {SVGA3D_ATI1, SVGA3DBLOCKDESC_COMPRESSED, 922 {SVGA3D_ATI1, SVGA3DBLOCKDESC_BC4_COMP_UNORM,
757 {4, 4, 1}, 8, 8, 923 {4, 4, 1}, 8, 8,
758 64, {{0}, {0}, {64}, {0}}, 924 {{0}, {0}, {64}, {0}},
759 {{0}, {0}, {0}, {0}}}, 925 {{0}, {0}, {0}, {0}}},
760 926
761 {SVGA3D_BC4_SNORM, SVGA3DBLOCKDESC_COMPRESSED, 927 {SVGA3D_BC4_SNORM, SVGA3DBLOCKDESC_BC4_COMP_SNORM,
762 {4, 4, 1}, 8, 8, 928 {4, 4, 1}, 8, 8,
763 64, {{0}, {0}, {64}, {0}}, 929 {{0}, {0}, {64}, {0}},
764 {{0}, {0}, {0}, {0}}}, 930 {{0}, {0}, {0}, {0}}},
765 931
766 {SVGA3D_BC5_TYPELESS, SVGA3DBLOCKDESC_COMPRESSED, 932 {SVGA3D_BC5_TYPELESS, SVGA3DBLOCKDESC_BC5_COMP_TYPELESS,
767 {4, 4, 1}, 16, 16, 933 {4, 4, 1}, 16, 16,
768 128, {{0}, {0}, {128}, {0}}, 934 {{0}, {0}, {128}, {0}},
769 {{0}, {0}, {0}, {0}}}, 935 {{0}, {0}, {0}, {0}}},
770 936
771 {SVGA3D_ATI2, SVGA3DBLOCKDESC_COMPRESSED, 937 {SVGA3D_ATI2, SVGA3DBLOCKDESC_BC5_COMP_UNORM,
772 {4, 4, 1}, 16, 16, 938 {4, 4, 1}, 16, 16,
773 128, {{0}, {0}, {128}, {0}}, 939 {{0}, {0}, {128}, {0}},
774 {{0}, {0}, {0}, {0}}}, 940 {{0}, {0}, {0}, {0}}},
775 941
776 {SVGA3D_BC5_SNORM, SVGA3DBLOCKDESC_COMPRESSED, 942 {SVGA3D_BC5_SNORM, SVGA3DBLOCKDESC_BC5_COMP_SNORM,
777 {4, 4, 1}, 16, 16, 943 {4, 4, 1}, 16, 16,
778 128, {{0}, {0}, {128}, {0}}, 944 {{0}, {0}, {128}, {0}},
779 {{0}, {0}, {0}, {0}}}, 945 {{0}, {0}, {0}, {0}}},
780 946
781 {SVGA3D_R10G10B10_XR_BIAS_A2_UNORM, SVGA3DBLOCKDESC_RGBA, 947 {SVGA3D_R10G10B10_XR_BIAS_A2_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM,
782 {1, 1, 1}, 4, 4, 948 {1, 1, 1}, 4, 4,
783 32, {{10}, {10}, {10}, {2}}, 949 {{10}, {10}, {10}, {2}},
784 {{0}, {10}, {20}, {30}}}, 950 {{20}, {10}, {0}, {30}}},
785 951
786 {SVGA3D_B8G8R8A8_TYPELESS, SVGA3DBLOCKDESC_RGBA, 952 {SVGA3D_B8G8R8A8_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
787 {1, 1, 1}, 4, 4, 953 {1, 1, 1}, 4, 4,
788 32, {{8}, {8}, {8}, {8}}, 954 {{8}, {8}, {8}, {8}},
789 {{0}, {8}, {16}, {24}}}, 955 {{0}, {8}, {16}, {24}}},
790 956
791 {SVGA3D_B8G8R8A8_UNORM_SRGB, SVGA3DBLOCKDESC_RGBA_SRGB, 957 {SVGA3D_B8G8R8A8_UNORM_SRGB, SVGA3DBLOCKDESC_RGBA_UNORM_SRGB,
792 {1, 1, 1}, 4, 4, 958 {1, 1, 1}, 4, 4,
793 32, {{8}, {8}, {8}, {8}}, 959 {{8}, {8}, {8}, {8}},
794 {{0}, {8}, {16}, {24}}}, 960 {{0}, {8}, {16}, {24}}},
795 961
796 {SVGA3D_B8G8R8X8_TYPELESS, SVGA3DBLOCKDESC_RGB, 962 {SVGA3D_B8G8R8X8_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
797 {1, 1, 1}, 4, 4, 963 {1, 1, 1}, 4, 4,
798 24, {{8}, {8}, {8}, {0}}, 964 {{8}, {8}, {8}, {0}},
799 {{0}, {8}, {16}, {24}}}, 965 {{0}, {8}, {16}, {24}}},
800 966
801 {SVGA3D_B8G8R8X8_UNORM_SRGB, SVGA3DBLOCKDESC_RGB_SRGB, 967 {SVGA3D_B8G8R8X8_UNORM_SRGB, SVGA3DBLOCKDESC_RGB_UNORM_SRGB,
802 {1, 1, 1}, 4, 4, 968 {1, 1, 1}, 4, 4,
803 24, {{8}, {8}, {8}, {0}}, 969 {{8}, {8}, {8}, {0}},
804 {{0}, {8}, {16}, {24}}}, 970 {{0}, {8}, {16}, {24}}},
805 971
806 {SVGA3D_Z_DF16, SVGA3DBLOCKDESC_DEPTH, 972 {SVGA3D_Z_DF16, SVGA3DBLOCKDESC_DEPTH_UNORM,
807 {1, 1, 1}, 2, 2, 973 {1, 1, 1}, 2, 2,
808 16, {{0}, {0}, {16}, {0}}, 974 {{0}, {0}, {16}, {0}},
809 {{0}, {0}, {0}, {0}}}, 975 {{0}, {0}, {0}, {0}}},
810 976
811 {SVGA3D_Z_DF24, SVGA3DBLOCKDESC_DEPTH, 977 {SVGA3D_Z_DF24, SVGA3DBLOCKDESC_DEPTH_UNORM,
812 {1, 1, 1}, 4, 4, 978 {1, 1, 1}, 4, 4,
813 32, {{0}, {8}, {24}, {0}}, 979 {{0}, {0}, {24}, {0}},
814 {{0}, {24}, {0}, {0}}}, 980 {{0}, {0}, {8}, {0}}},
815 981
816 {SVGA3D_Z_D24S8_INT, SVGA3DBLOCKDESC_DS, 982 {SVGA3D_Z_D24S8_INT, SVGA3DBLOCKDESC_DS_UNORM,
817 {1, 1, 1}, 4, 4, 983 {1, 1, 1}, 4, 4,
818 32, {{0}, {8}, {24}, {0}}, 984 {{0}, {8}, {24}, {0}},
819 {{0}, {24}, {0}, {0}}}, 985 {{0}, {0}, {8}, {0}}},
820 986
821 {SVGA3D_YV12, SVGA3DBLOCKDESC_YV12, 987 {SVGA3D_YV12, SVGA3DBLOCKDESC_YV12,
822 {2, 2, 1}, 6, 2, 988 {2, 2, 1}, 6, 2,
823 48, {{0}, {0}, {48}, {0}}, 989 {{0}, {0}, {48}, {0}},
824 {{0}, {0}, {0}, {0}}}, 990 {{0}, {0}, {0}, {0}}},
825 991
826 {SVGA3D_R32G32B32A32_FLOAT, SVGA3DBLOCKDESC_RGBA_FP, 992 {SVGA3D_R32G32B32A32_FLOAT, SVGA3DBLOCKDESC_RGBA_FP,
827 {1, 1, 1}, 16, 16, 993 {1, 1, 1}, 16, 16,
828 128, {{32}, {32}, {32}, {32}}, 994 {{32}, {32}, {32}, {32}},
829 {{64}, {32}, {0}, {96}}}, 995 {{64}, {32}, {0}, {96}}},
830 996
831 {SVGA3D_R16G16B16A16_FLOAT, SVGA3DBLOCKDESC_RGBA_FP, 997 {SVGA3D_R16G16B16A16_FLOAT, SVGA3DBLOCKDESC_RGBA_FP,
832 {1, 1, 1}, 8, 8, 998 {1, 1, 1}, 8, 8,
833 64, {{16}, {16}, {16}, {16}}, 999 {{16}, {16}, {16}, {16}},
834 {{32}, {16}, {0}, {48}}}, 1000 {{32}, {16}, {0}, {48}}},
835 1001
836 {SVGA3D_R16G16B16A16_UNORM, SVGA3DBLOCKDESC_RGBA, 1002 {SVGA3D_R16G16B16A16_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM,
837 {1, 1, 1}, 8, 8, 1003 {1, 1, 1}, 8, 8,
838 64, {{16}, {16}, {16}, {16}}, 1004 {{16}, {16}, {16}, {16}},
839 {{32}, {16}, {0}, {48}}}, 1005 {{32}, {16}, {0}, {48}}},
840 1006
841 {SVGA3D_R32G32_FLOAT, SVGA3DBLOCKDESC_RG_FP, 1007 {SVGA3D_R32G32_FLOAT, SVGA3DBLOCKDESC_RG_FP,
842 {1, 1, 1}, 8, 8, 1008 {1, 1, 1}, 8, 8,
843 64, {{0}, {32}, {32}, {0}}, 1009 {{0}, {32}, {32}, {0}},
844 {{0}, {32}, {0}, {0}}}, 1010 {{0}, {32}, {0}, {0}}},
845 1011
846 {SVGA3D_R10G10B10A2_UNORM, SVGA3DBLOCKDESC_RGBA, 1012 {SVGA3D_R10G10B10A2_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM,
847 {1, 1, 1}, 4, 4, 1013 {1, 1, 1}, 4, 4,
848 32, {{10}, {10}, {10}, {2}}, 1014 {{10}, {10}, {10}, {2}},
849 {{0}, {10}, {20}, {30}}}, 1015 {{20}, {10}, {0}, {30}}},
850 1016
851 {SVGA3D_R8G8B8A8_SNORM, SVGA3DBLOCKDESC_RGBA, 1017 {SVGA3D_R8G8B8A8_SNORM, SVGA3DBLOCKDESC_RGBA_SNORM,
852 {1, 1, 1}, 4, 4, 1018 {1, 1, 1}, 4, 4,
853 32, {{8}, {8}, {8}, {8}}, 1019 {{8}, {8}, {8}, {8}},
854 {{24}, {16}, {8}, {0}}}, 1020 {{16}, {8}, {0}, {24}}},
855 1021
856 {SVGA3D_R16G16_FLOAT, SVGA3DBLOCKDESC_RG_FP, 1022 {SVGA3D_R16G16_FLOAT, SVGA3DBLOCKDESC_RG_FP,
857 {1, 1, 1}, 4, 4, 1023 {1, 1, 1}, 4, 4,
858 32, {{0}, {16}, {16}, {0}}, 1024 {{0}, {16}, {16}, {0}},
859 {{0}, {16}, {0}, {0}}}, 1025 {{0}, {16}, {0}, {0}}},
860 1026
861 {SVGA3D_R16G16_UNORM, SVGA3DBLOCKDESC_RG, 1027 {SVGA3D_R16G16_UNORM, SVGA3DBLOCKDESC_RG_UNORM,
862 {1, 1, 1}, 4, 4, 1028 {1, 1, 1}, 4, 4,
863 32, {{0}, {16}, {16}, {0}}, 1029 {{0}, {16}, {16}, {0}},
864 {{0}, {0}, {16}, {0}}}, 1030 {{0}, {16}, {0}, {0}}},
865 1031
866 {SVGA3D_R16G16_SNORM, SVGA3DBLOCKDESC_RG, 1032 {SVGA3D_R16G16_SNORM, SVGA3DBLOCKDESC_RG_SNORM,
867 {1, 1, 1}, 4, 4, 1033 {1, 1, 1}, 4, 4,
868 32, {{16}, {16}, {0}, {0}}, 1034 {{0}, {16}, {16}, {0}},
869 {{16}, {0}, {0}, {0}}}, 1035 {{0}, {16}, {0}, {0}}},
870 1036
871 {SVGA3D_R32_FLOAT, SVGA3DBLOCKDESC_R_FP, 1037 {SVGA3D_R32_FLOAT, SVGA3DBLOCKDESC_R_FP,
872 {1, 1, 1}, 4, 4, 1038 {1, 1, 1}, 4, 4,
873 32, {{0}, {0}, {32}, {0}}, 1039 {{0}, {0}, {32}, {0}},
874 {{0}, {0}, {0}, {0}}}, 1040 {{0}, {0}, {0}, {0}}},
875 1041
876 {SVGA3D_R8G8_SNORM, SVGA3DBLOCKDESC_RG, 1042 {SVGA3D_R8G8_SNORM, SVGA3DBLOCKDESC_RG_SNORM,
877 {1, 1, 1}, 2, 2, 1043 {1, 1, 1}, 2, 2,
878 16, {{8}, {8}, {0}, {0}}, 1044 {{0}, {8}, {8}, {0}},
879 {{8}, {0}, {0}, {0}}}, 1045 {{0}, {8}, {0}, {0}}},
880 1046
881 {SVGA3D_R16_FLOAT, SVGA3DBLOCKDESC_R_FP, 1047 {SVGA3D_R16_FLOAT, SVGA3DBLOCKDESC_R_FP,
882 {1, 1, 1}, 2, 2, 1048 {1, 1, 1}, 2, 2,
883 16, {{0}, {0}, {16}, {0}}, 1049 {{0}, {0}, {16}, {0}},
884 {{0}, {0}, {0}, {0}}}, 1050 {{0}, {0}, {0}, {0}}},
885 1051
886 {SVGA3D_D16_UNORM, SVGA3DBLOCKDESC_DEPTH, 1052 {SVGA3D_D16_UNORM, SVGA3DBLOCKDESC_DEPTH_UNORM,
887 {1, 1, 1}, 2, 2, 1053 {1, 1, 1}, 2, 2,
888 16, {{0}, {0}, {16}, {0}}, 1054 {{0}, {0}, {16}, {0}},
889 {{0}, {0}, {0}, {0}}}, 1055 {{0}, {0}, {0}, {0}}},
890 1056
891 {SVGA3D_A8_UNORM, SVGA3DBLOCKDESC_ALPHA, 1057 {SVGA3D_A8_UNORM, SVGA3DBLOCKDESC_A_UNORM,
892 {1, 1, 1}, 1, 1, 1058 {1, 1, 1}, 1, 1,
893 8, {{0}, {0}, {0}, {8}}, 1059 {{0}, {0}, {0}, {8}},
894 {{0}, {0}, {0}, {0}}}, 1060 {{0}, {0}, {0}, {0}}},
895 1061
896 {SVGA3D_BC1_UNORM, SVGA3DBLOCKDESC_COMPRESSED, 1062 {SVGA3D_BC1_UNORM, SVGA3DBLOCKDESC_BC1_COMP_UNORM,
897 {4, 4, 1}, 8, 8, 1063 {4, 4, 1}, 8, 8,
898 64, {{0}, {0}, {64}, {0}}, 1064 {{0}, {0}, {64}, {0}},
899 {{0}, {0}, {0}, {0}}}, 1065 {{0}, {0}, {0}, {0}}},
900 1066
901 {SVGA3D_BC2_UNORM, SVGA3DBLOCKDESC_COMPRESSED, 1067 {SVGA3D_BC2_UNORM, SVGA3DBLOCKDESC_BC2_COMP_UNORM,
902 {4, 4, 1}, 16, 16, 1068 {4, 4, 1}, 16, 16,
903 128, {{0}, {0}, {128}, {0}}, 1069 {{0}, {0}, {128}, {0}},
904 {{0}, {0}, {0}, {0}}}, 1070 {{0}, {0}, {0}, {0}}},
905 1071
906 {SVGA3D_BC3_UNORM, SVGA3DBLOCKDESC_COMPRESSED, 1072 {SVGA3D_BC3_UNORM, SVGA3DBLOCKDESC_BC3_COMP_UNORM,
907 {4, 4, 1}, 16, 16, 1073 {4, 4, 1}, 16, 16,
908 128, {{0}, {0}, {128}, {0}}, 1074 {{0}, {0}, {128}, {0}},
909 {{0}, {0}, {0}, {0}}}, 1075 {{0}, {0}, {0}, {0}}},
910 1076
911 {SVGA3D_B5G6R5_UNORM, SVGA3DBLOCKDESC_RGB, 1077 {SVGA3D_B5G6R5_UNORM, SVGA3DBLOCKDESC_RGB_UNORM,
912 {1, 1, 1}, 2, 2, 1078 {1, 1, 1}, 2, 2,
913 16, {{5}, {6}, {5}, {0}}, 1079 {{5}, {6}, {5}, {0}},
914 {{0}, {5}, {11}, {0}}}, 1080 {{0}, {5}, {11}, {0}}},
915 1081
916 {SVGA3D_B5G5R5A1_UNORM, SVGA3DBLOCKDESC_RGBA, 1082 {SVGA3D_B5G5R5A1_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM,
917 {1, 1, 1}, 2, 2, 1083 {1, 1, 1}, 2, 2,
918 16, {{5}, {5}, {5}, {1}}, 1084 {{5}, {5}, {5}, {1}},
919 {{0}, {5}, {10}, {15}}}, 1085 {{0}, {5}, {10}, {15}}},
920 1086
921 {SVGA3D_B8G8R8A8_UNORM, SVGA3DBLOCKDESC_RGBA, 1087 {SVGA3D_B8G8R8A8_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM,
922 {1, 1, 1}, 4, 4, 1088 {1, 1, 1}, 4, 4,
923 32, {{8}, {8}, {8}, {8}}, 1089 {{8}, {8}, {8}, {8}},
924 {{0}, {8}, {16}, {24}}}, 1090 {{0}, {8}, {16}, {24}}},
925 1091
926 {SVGA3D_B8G8R8X8_UNORM, SVGA3DBLOCKDESC_RGB, 1092 {SVGA3D_B8G8R8X8_UNORM, SVGA3DBLOCKDESC_RGB_UNORM,
927 {1, 1, 1}, 4, 4, 1093 {1, 1, 1}, 4, 4,
928 24, {{8}, {8}, {8}, {0}}, 1094 {{8}, {8}, {8}, {0}},
929 {{0}, {8}, {16}, {24}}}, 1095 {{0}, {8}, {16}, {24}}},
930 1096
931 {SVGA3D_BC4_UNORM, SVGA3DBLOCKDESC_COMPRESSED, 1097 {SVGA3D_BC4_UNORM, SVGA3DBLOCKDESC_BC4_COMP_UNORM,
932 {4, 4, 1}, 8, 8, 1098 {4, 4, 1}, 8, 8,
933 64, {{0}, {0}, {64}, {0}}, 1099 {{0}, {0}, {64}, {0}},
934 {{0}, {0}, {0}, {0}}}, 1100 {{0}, {0}, {0}, {0}}},
935 1101
936 {SVGA3D_BC5_UNORM, SVGA3DBLOCKDESC_COMPRESSED, 1102 {SVGA3D_BC5_UNORM, SVGA3DBLOCKDESC_BC5_COMP_UNORM,
937 {4, 4, 1}, 16, 16, 1103 {4, 4, 1}, 16, 16,
938 128, {{0}, {0}, {128}, {0}}, 1104 {{0}, {0}, {128}, {0}},
939 {{0}, {0}, {0}, {0}}}, 1105 {{0}, {0}, {0}, {0}}},
940
941}; 1106};
942 1107
943static inline u32 clamped_umul32(u32 a, u32 b) 1108static inline u32 clamped_umul32(u32 a, u32 b)
@@ -946,6 +1111,10 @@ static inline u32 clamped_umul32(u32 a, u32 b)
946 return (tmp > (uint64_t) ((u32) -1)) ? (u32) -1 : tmp; 1111 return (tmp > (uint64_t) ((u32) -1)) ? (u32) -1 : tmp;
947} 1112}
948 1113
1114/**
1115 * svga3dsurface_get_desc - Look up the appropriate SVGA3dSurfaceDesc for the
1116 * given format.
1117 */
949static inline const struct svga3d_surface_desc * 1118static inline const struct svga3d_surface_desc *
950svga3dsurface_get_desc(SVGA3dSurfaceFormat format) 1119svga3dsurface_get_desc(SVGA3dSurfaceFormat format)
951{ 1120{
@@ -955,23 +1124,10 @@ svga3dsurface_get_desc(SVGA3dSurfaceFormat format)
955 return &svga3d_surface_descs[SVGA3D_FORMAT_INVALID]; 1124 return &svga3d_surface_descs[SVGA3D_FORMAT_INVALID];
956} 1125}
957 1126
958/* 1127/**
959 *---------------------------------------------------------------------- 1128 * svga3dsurface_get_mip_size - Given a base level size and the mip level,
960 * 1129 * compute the size of the mip level.
961 * svga3dsurface_get_mip_size --
962 *
963 * Given a base level size and the mip level, compute the size of
964 * the mip level.
965 *
966 * Results:
967 * See above.
968 *
969 * Side effects:
970 * None.
971 *
972 *----------------------------------------------------------------------
973 */ 1130 */
974
975static inline surf_size_struct 1131static inline surf_size_struct
976svga3dsurface_get_mip_size(surf_size_struct base_level, u32 mip_level) 1132svga3dsurface_get_mip_size(surf_size_struct base_level, u32 mip_level)
977{ 1133{
@@ -1018,28 +1174,17 @@ svga3dsurface_calculate_pitch(const struct svga3d_surface_desc *desc,
1018 return pitch; 1174 return pitch;
1019} 1175}
1020 1176
1021/* 1177/**
1022 *----------------------------------------------------------------------------- 1178 * svga3dsurface_get_image_buffer_size - Calculates image buffer size.
1023 *
1024 * svga3dsurface_get_image_buffer_size --
1025 *
1026 * Return the number of bytes of buffer space required to store
1027 * one image of a surface, optionally using the specified pitch.
1028 *
1029 * If pitch is zero, it is assumed that rows are tightly packed.
1030 *
1031 * This function is overflow-safe. If the result would have
1032 * overflowed, instead we return MAX_UINT32.
1033 * 1179 *
1034 * Results: 1180 * Return the number of bytes of buffer space required to store one image of a
1035 * Byte count. 1181 * surface, optionally using the specified pitch.
1036 * 1182 *
1037 * Side effects: 1183 * If pitch is zero, it is assumed that rows are tightly packed.
1038 * None.
1039 * 1184 *
1040 *----------------------------------------------------------------------------- 1185 * This function is overflow-safe. If the result would have overflowed, instead
1186 * we return MAX_UINT32.
1041 */ 1187 */
1042
1043static inline u32 1188static inline u32
1044svga3dsurface_get_image_buffer_size(const struct svga3d_surface_desc *desc, 1189svga3dsurface_get_image_buffer_size(const struct svga3d_surface_desc *desc,
1045 const surf_size_struct *size, 1190 const surf_size_struct *size,
@@ -1067,6 +1212,9 @@ svga3dsurface_get_image_buffer_size(const struct svga3d_surface_desc *desc,
1067 return total_size; 1212 return total_size;
1068} 1213}
1069 1214
1215/**
1216 * svga3dsurface_get_serialized_size - Get the serialized size for the image.
1217 */
1070static inline u32 1218static inline u32
1071svga3dsurface_get_serialized_size(SVGA3dSurfaceFormat format, 1219svga3dsurface_get_serialized_size(SVGA3dSurfaceFormat format,
1072 surf_size_struct base_level_size, 1220 surf_size_struct base_level_size,
@@ -1206,3 +1354,5 @@ svga3dsurface_is_screen_target_format(SVGA3dSurfaceFormat format)
1206 } 1354 }
1207 return svga3dsurface_is_dx_screen_target_format(format); 1355 return svga3dsurface_is_dx_screen_target_format(format);
1208} 1356}
1357
1358#endif /* _SVGA3D_SURFACEDEFS_H_ */
diff --git a/drivers/gpu/drm/vmwgfx/device_include/svga3d_types.h b/drivers/gpu/drm/vmwgfx/device_include/svga3d_types.h
index 27b33ba88430..309904e7cfd3 100644
--- a/drivers/gpu/drm/vmwgfx/device_include/svga3d_types.h
+++ b/drivers/gpu/drm/vmwgfx/device_include/svga3d_types.h
@@ -44,9 +44,21 @@
44 44
45#define SVGA3D_INVALID_ID ((uint32)-1) 45#define SVGA3D_INVALID_ID ((uint32)-1)
46 46
47typedef uint8 SVGABool8; /* 8-bit Bool definition */
47typedef uint32 SVGA3dBool; /* 32-bit Bool definition */ 48typedef uint32 SVGA3dBool; /* 32-bit Bool definition */
48typedef uint32 SVGA3dColor; /* a, r, g, b */ 49typedef uint32 SVGA3dColor; /* a, r, g, b */
49 50
51typedef uint32 SVGA3dSurfaceId;
52
53typedef
54#include "vmware_pack_begin.h"
55struct {
56 uint32 numerator;
57 uint32 denominator;
58}
59#include "vmware_pack_end.h"
60SVGA3dFraction64;
61
50typedef 62typedef
51#include "vmware_pack_begin.h" 63#include "vmware_pack_begin.h"
52struct SVGA3dCopyRect { 64struct SVGA3dCopyRect {
@@ -145,7 +157,7 @@ typedef enum SVGA3dSurfaceFormat {
145 SVGA3D_BUMPU8V8 = 20, 157 SVGA3D_BUMPU8V8 = 20,
146 SVGA3D_BUMPL6V5U5 = 21, 158 SVGA3D_BUMPL6V5U5 = 21,
147 SVGA3D_BUMPX8L8V8U8 = 22, 159 SVGA3D_BUMPX8L8V8U8 = 22,
148 SVGA3D_BUMPL8V8U8 = 23, 160 SVGA3D_FORMAT_DEAD1 = 23,
149 161
150 SVGA3D_ARGB_S10E5 = 24, /* 16-bit floating-point ARGB */ 162 SVGA3D_ARGB_S10E5 = 24, /* 16-bit floating-point ARGB */
151 SVGA3D_ARGB_S23E8 = 25, /* 32-bit floating-point ARGB */ 163 SVGA3D_ARGB_S23E8 = 25, /* 32-bit floating-point ARGB */
@@ -204,8 +216,8 @@ typedef enum SVGA3dSurfaceFormat {
204 SVGA3D_R32G32_SINT = 59, 216 SVGA3D_R32G32_SINT = 59,
205 SVGA3D_R32G8X24_TYPELESS = 60, 217 SVGA3D_R32G8X24_TYPELESS = 60,
206 SVGA3D_D32_FLOAT_S8X24_UINT = 61, 218 SVGA3D_D32_FLOAT_S8X24_UINT = 61,
207 SVGA3D_R32_FLOAT_X8X24_TYPELESS = 62, 219 SVGA3D_R32_FLOAT_X8X24 = 62,
208 SVGA3D_X32_TYPELESS_G8X24_UINT = 63, 220 SVGA3D_X32_G8X24_UINT = 63,
209 SVGA3D_R10G10B10A2_TYPELESS = 64, 221 SVGA3D_R10G10B10A2_TYPELESS = 64,
210 SVGA3D_R10G10B10A2_UINT = 65, 222 SVGA3D_R10G10B10A2_UINT = 65,
211 SVGA3D_R11G11B10_FLOAT = 66, 223 SVGA3D_R11G11B10_FLOAT = 66,
@@ -223,8 +235,8 @@ typedef enum SVGA3dSurfaceFormat {
223 SVGA3D_R32_SINT = 78, 235 SVGA3D_R32_SINT = 78,
224 SVGA3D_R24G8_TYPELESS = 79, 236 SVGA3D_R24G8_TYPELESS = 79,
225 SVGA3D_D24_UNORM_S8_UINT = 80, 237 SVGA3D_D24_UNORM_S8_UINT = 80,
226 SVGA3D_R24_UNORM_X8_TYPELESS = 81, 238 SVGA3D_R24_UNORM_X8 = 81,
227 SVGA3D_X24_TYPELESS_G8_UINT = 82, 239 SVGA3D_X24_G8_UINT = 82,
228 SVGA3D_R8G8_TYPELESS = 83, 240 SVGA3D_R8G8_TYPELESS = 83,
229 SVGA3D_R8G8_UNORM = 84, 241 SVGA3D_R8G8_UNORM = 84,
230 SVGA3D_R8G8_UINT = 85, 242 SVGA3D_R8G8_UINT = 85,
@@ -296,92 +308,114 @@ typedef enum SVGA3dSurfaceFormat {
296 SVGA3D_FORMAT_MAX 308 SVGA3D_FORMAT_MAX
297} SVGA3dSurfaceFormat; 309} SVGA3dSurfaceFormat;
298 310
299typedef enum SVGA3dSurfaceFlags { 311/*
300 SVGA3D_SURFACE_CUBEMAP = (1 << 0), 312 * SVGA3d Surface Flags --
313 */
314#define SVGA3D_SURFACE_CUBEMAP (1 << 0)
301 315
302 /* 316/*
303 * HINT flags are not enforced by the device but are useful for 317 * HINT flags are not enforced by the device but are useful for
304 * performance. 318 * performance.
305 */ 319 */
306 SVGA3D_SURFACE_HINT_STATIC = (1 << 1), 320#define SVGA3D_SURFACE_HINT_STATIC (CONST64U(1) << 1)
307 SVGA3D_SURFACE_HINT_DYNAMIC = (1 << 2), 321#define SVGA3D_SURFACE_HINT_DYNAMIC (CONST64U(1) << 2)
308 SVGA3D_SURFACE_HINT_INDEXBUFFER = (1 << 3), 322#define SVGA3D_SURFACE_HINT_INDEXBUFFER (CONST64U(1) << 3)
309 SVGA3D_SURFACE_HINT_VERTEXBUFFER = (1 << 4), 323#define SVGA3D_SURFACE_HINT_VERTEXBUFFER (CONST64U(1) << 4)
310 SVGA3D_SURFACE_HINT_TEXTURE = (1 << 5), 324#define SVGA3D_SURFACE_HINT_TEXTURE (CONST64U(1) << 5)
311 SVGA3D_SURFACE_HINT_RENDERTARGET = (1 << 6), 325#define SVGA3D_SURFACE_HINT_RENDERTARGET (CONST64U(1) << 6)
312 SVGA3D_SURFACE_HINT_DEPTHSTENCIL = (1 << 7), 326#define SVGA3D_SURFACE_HINT_DEPTHSTENCIL (CONST64U(1) << 7)
313 SVGA3D_SURFACE_HINT_WRITEONLY = (1 << 8), 327#define SVGA3D_SURFACE_HINT_WRITEONLY (CONST64U(1) << 8)
314 SVGA3D_SURFACE_MASKABLE_ANTIALIAS = (1 << 9), 328#define SVGA3D_SURFACE_MASKABLE_ANTIALIAS (CONST64U(1) << 9)
315 SVGA3D_SURFACE_AUTOGENMIPMAPS = (1 << 10), 329#define SVGA3D_SURFACE_AUTOGENMIPMAPS (CONST64U(1) << 10)
316 SVGA3D_SURFACE_DECODE_RENDERTARGET = (1 << 11), 330
331#define SVGA3D_SURFACE_DECODE_RENDERTARGET (CONST64U(1) << 11)
317 332
318 /* 333/*
319 * Is this surface using a base-level pitch for it's mob backing? 334 * Is this surface using a base-level pitch for it's mob backing?
320 * 335 *
321 * This flag is not intended to be set by guest-drivers, but is instead 336 * This flag is not intended to be set by guest-drivers, but is instead
322 * set by the device when the surface is bound to a mob with a specified 337 * set by the device when the surface is bound to a mob with a specified
323 * pitch. 338 * pitch.
324 */ 339 */
325 SVGA3D_SURFACE_MOB_PITCH = (1 << 12), 340#define SVGA3D_SURFACE_MOB_PITCH (CONST64U(1) << 12)
326 341
327 SVGA3D_SURFACE_INACTIVE = (1 << 13), 342#define SVGA3D_SURFACE_INACTIVE (CONST64U(1) << 13)
328 SVGA3D_SURFACE_HINT_RT_LOCKABLE = (1 << 14), 343#define SVGA3D_SURFACE_HINT_RT_LOCKABLE (CONST64U(1) << 14)
329 SVGA3D_SURFACE_VOLUME = (1 << 15), 344#define SVGA3D_SURFACE_VOLUME (CONST64U(1) << 15)
330 345
331 /* 346/*
332 * Required to be set on a surface to bind it to a screen target. 347 * Required to be set on a surface to bind it to a screen target.
333 */ 348 */
334 SVGA3D_SURFACE_SCREENTARGET = (1 << 16), 349#define SVGA3D_SURFACE_SCREENTARGET (CONST64U(1) << 16)
335 350
336 /* 351/*
337 * Align images in the guest-backing mob to 16-bytes. 352 * Align images in the guest-backing mob to 16-bytes.
338 */ 353 */
339 SVGA3D_SURFACE_ALIGN16 = (1 << 17), 354#define SVGA3D_SURFACE_ALIGN16 (CONST64U(1) << 17)
340 355
341 SVGA3D_SURFACE_1D = (1 << 18), 356#define SVGA3D_SURFACE_1D (CONST64U(1) << 18)
342 SVGA3D_SURFACE_ARRAY = (1 << 19), 357#define SVGA3D_SURFACE_ARRAY (CONST64U(1) << 19)
343 358
344 /* 359/*
345 * Bind flags. 360 * Bind flags.
346 * These are enforced for any surface defined with DefineGBSurface_v2. 361 * These are enforced for any surface defined with DefineGBSurface_v2.
347 */ 362 */
348 SVGA3D_SURFACE_BIND_VERTEX_BUFFER = (1 << 20), 363#define SVGA3D_SURFACE_BIND_VERTEX_BUFFER (CONST64U(1) << 20)
349 SVGA3D_SURFACE_BIND_INDEX_BUFFER = (1 << 21), 364#define SVGA3D_SURFACE_BIND_INDEX_BUFFER (CONST64U(1) << 21)
350 SVGA3D_SURFACE_BIND_CONSTANT_BUFFER = (1 << 22), 365#define SVGA3D_SURFACE_BIND_CONSTANT_BUFFER (CONST64U(1) << 22)
351 SVGA3D_SURFACE_BIND_SHADER_RESOURCE = (1 << 23), 366#define SVGA3D_SURFACE_BIND_SHADER_RESOURCE (CONST64U(1) << 23)
352 SVGA3D_SURFACE_BIND_RENDER_TARGET = (1 << 24), 367#define SVGA3D_SURFACE_BIND_RENDER_TARGET (CONST64U(1) << 24)
353 SVGA3D_SURFACE_BIND_DEPTH_STENCIL = (1 << 25), 368#define SVGA3D_SURFACE_BIND_DEPTH_STENCIL (CONST64U(1) << 25)
354 SVGA3D_SURFACE_BIND_STREAM_OUTPUT = (1 << 26), 369#define SVGA3D_SURFACE_BIND_STREAM_OUTPUT (CONST64U(1) << 26)
355 370
356 /* 371/*
357 * A note on staging flags: 372 * The STAGING flags notes that the surface will not be used directly by the
358 * 373 * drawing pipeline, i.e. that it will not be bound to any bind point.
359 * The STAGING flags notes that the surface will not be used directly by the 374 * Staging surfaces may be used by copy operations to move data in and out
360 * drawing pipeline, i.e. that it will not be bound to any bind point. 375 * of other surfaces. No bind flags may be set on surfaces with this flag.
361 * Staging surfaces may be used by copy operations to move data in and out 376 *
362 * of other surfaces. 377 * The HINT_INDIRECT_UPDATE flag suggests that the surface will receive
363 * 378 * updates indirectly, i.e. the surface will not be updated directly, but
364 * The HINT_INDIRECT_UPDATE flag suggests that the surface will receive 379 * will receive copies from staging surfaces.
365 * updates indirectly, i.e. the surface will not be updated directly, but 380 */
366 * will receive copies from staging surfaces. 381#define SVGA3D_SURFACE_STAGING_UPLOAD (CONST64U(1) << 27)
367 */ 382#define SVGA3D_SURFACE_STAGING_DOWNLOAD (CONST64U(1) << 28)
368 SVGA3D_SURFACE_STAGING_UPLOAD = (1 << 27), 383#define SVGA3D_SURFACE_HINT_INDIRECT_UPDATE (CONST64U(1) << 29)
369 SVGA3D_SURFACE_STAGING_DOWNLOAD = (1 << 28),
370 SVGA3D_SURFACE_HINT_INDIRECT_UPDATE = (1 << 29),
371 384
372 /* 385/*
373 * Setting this flag allow this surface to be used with the 386 * Setting this flag allow this surface to be used with the
374 * SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER command. It is only valid for 387 * SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER command. It is only valid for
375 * buffer surfaces, an no bind flags are allowed to be set on surfaces 388 * buffer surfaces, and no bind flags are allowed to be set on surfaces
376 * with this flag. 389 * with this flag.
377 */ 390 */
378 SVGA3D_SURFACE_TRANSFER_FROM_BUFFER = (1 << 30), 391#define SVGA3D_SURFACE_TRANSFER_FROM_BUFFER (CONST64U(1) << 30)
379 392
380 /* 393/*
381 * Marker for the last defined bit. 394 * Reserved for video operations.
382 */ 395 */
383 SVGA3D_SURFACE_FLAG_MAX = (1 << 31), 396#define SVGA3D_SURFACE_RESERVED1 (CONST64U(1) << 31)
384} SVGA3dSurfaceFlags; 397
398/*
399 * Specifies that a surface is multisample, and therefore requires the full
400 * mob-backing to store all the samples.
401 */
402#define SVGA3D_SURFACE_MULTISAMPLE (CONST64U(1) << 32)
403
404#define SVGA3D_SURFACE_FLAG_MAX (CONST64U(1) << 33)
405
406/*
407 * Surface flags types:
408 *
409 * SVGA3dSurface1Flags: Lower 32-bits of flags.
410 * SVGA3dSurface2Flags: Upper 32-bits of flags.
411 * SVGA3dSurfaceAllFlags: Full 64-bits of flags.
412 */
413typedef uint32 SVGA3dSurface1Flags;
414typedef uint32 SVGA3dSurface2Flags;
415typedef uint64 SVGA3dSurfaceAllFlags;
416
417#define SVGA3D_SURFACE_FLAGS1_MASK ((uint64_t)MAX_UINT32)
418#define SVGA3D_SURFACE_FLAGS2_MASK (MAX_UINT64 & ~SVGA3D_SURFACE_FLAGS1_MASK)
385 419
386#define SVGA3D_SURFACE_HB_DISALLOWED_MASK \ 420#define SVGA3D_SURFACE_HB_DISALLOWED_MASK \
387 ( SVGA3D_SURFACE_MOB_PITCH | \ 421 ( SVGA3D_SURFACE_MOB_PITCH | \
@@ -392,29 +426,41 @@ typedef enum SVGA3dSurfaceFlags {
392 SVGA3D_SURFACE_STAGING_UPLOAD | \ 426 SVGA3D_SURFACE_STAGING_UPLOAD | \
393 SVGA3D_SURFACE_STAGING_DOWNLOAD | \ 427 SVGA3D_SURFACE_STAGING_DOWNLOAD | \
394 SVGA3D_SURFACE_HINT_INDIRECT_UPDATE | \ 428 SVGA3D_SURFACE_HINT_INDIRECT_UPDATE | \
395 SVGA3D_SURFACE_TRANSFER_FROM_BUFFER \ 429 SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | \
430 SVGA3D_SURFACE_MULTISAMPLE \
431 )
432
433#define SVGA3D_SURFACE_HB_PRESENT_DISALLOWED_MASK \
434 ( SVGA3D_SURFACE_1D | \
435 SVGA3D_SURFACE_MULTISAMPLE \
396 ) 436 )
397 437
398#define SVGA3D_SURFACE_2D_DISALLOWED_MASK \ 438#define SVGA3D_SURFACE_2D_DISALLOWED_MASK \
399 ( SVGA3D_SURFACE_CUBEMAP | \ 439 ( SVGA3D_SURFACE_CUBEMAP | \
400 SVGA3D_SURFACE_MASKABLE_ANTIALIAS | \ 440 SVGA3D_SURFACE_MASKABLE_ANTIALIAS | \
401 SVGA3D_SURFACE_AUTOGENMIPMAPS | \ 441 SVGA3D_SURFACE_AUTOGENMIPMAPS | \
402 SVGA3D_SURFACE_DECODE_RENDERTARGET | \
403 SVGA3D_SURFACE_VOLUME | \ 442 SVGA3D_SURFACE_VOLUME | \
404 SVGA3D_SURFACE_1D | \ 443 SVGA3D_SURFACE_1D | \
405 SVGA3D_SURFACE_ARRAY | \
406 SVGA3D_SURFACE_BIND_VERTEX_BUFFER | \ 444 SVGA3D_SURFACE_BIND_VERTEX_BUFFER | \
407 SVGA3D_SURFACE_BIND_INDEX_BUFFER | \ 445 SVGA3D_SURFACE_BIND_INDEX_BUFFER | \
408 SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \ 446 SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \
409 SVGA3D_SURFACE_BIND_DEPTH_STENCIL | \ 447 SVGA3D_SURFACE_BIND_DEPTH_STENCIL | \
410 SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \ 448 SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \
411 SVGA3D_SURFACE_TRANSFER_FROM_BUFFER \ 449 SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | \
450 SVGA3D_SURFACE_MULTISAMPLE \
451 )
452
453#define SVGA3D_SURFACE_BASICOPS_DISALLOWED_MASK \
454 ( SVGA3D_SURFACE_CUBEMAP | \
455 SVGA3D_SURFACE_AUTOGENMIPMAPS | \
456 SVGA3D_SURFACE_VOLUME | \
457 SVGA3D_SURFACE_1D | \
458 SVGA3D_SURFACE_MULTISAMPLE \
412 ) 459 )
413 460
414#define SVGA3D_SURFACE_SCREENTARGET_DISALLOWED_MASK \ 461#define SVGA3D_SURFACE_SCREENTARGET_DISALLOWED_MASK \
415 ( SVGA3D_SURFACE_CUBEMAP | \ 462 ( SVGA3D_SURFACE_CUBEMAP | \
416 SVGA3D_SURFACE_AUTOGENMIPMAPS | \ 463 SVGA3D_SURFACE_AUTOGENMIPMAPS | \
417 SVGA3D_SURFACE_DECODE_RENDERTARGET | \
418 SVGA3D_SURFACE_VOLUME | \ 464 SVGA3D_SURFACE_VOLUME | \
419 SVGA3D_SURFACE_1D | \ 465 SVGA3D_SURFACE_1D | \
420 SVGA3D_SURFACE_BIND_VERTEX_BUFFER | \ 466 SVGA3D_SURFACE_BIND_VERTEX_BUFFER | \
@@ -426,12 +472,36 @@ typedef enum SVGA3dSurfaceFlags {
426 SVGA3D_SURFACE_STAGING_UPLOAD | \ 472 SVGA3D_SURFACE_STAGING_UPLOAD | \
427 SVGA3D_SURFACE_STAGING_DOWNLOAD | \ 473 SVGA3D_SURFACE_STAGING_DOWNLOAD | \
428 SVGA3D_SURFACE_HINT_INDIRECT_UPDATE | \ 474 SVGA3D_SURFACE_HINT_INDIRECT_UPDATE | \
429 SVGA3D_SURFACE_TRANSFER_FROM_BUFFER \ 475 SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | \
476 SVGA3D_SURFACE_MULTISAMPLE \
477 )
478
479#define SVGA3D_SURFACE_BUFFER_DISALLOWED_MASK \
480 ( SVGA3D_SURFACE_CUBEMAP | \
481 SVGA3D_SURFACE_AUTOGENMIPMAPS | \
482 SVGA3D_SURFACE_VOLUME | \
483 SVGA3D_SURFACE_1D | \
484 SVGA3D_SURFACE_MASKABLE_ANTIALIAS | \
485 SVGA3D_SURFACE_ARRAY | \
486 SVGA3D_SURFACE_MULTISAMPLE | \
487 SVGA3D_SURFACE_MOB_PITCH \
488 )
489
490#define SVGA3D_SURFACE_MULTISAMPLE_DISALLOWED_MASK \
491 ( SVGA3D_SURFACE_CUBEMAP | \
492 SVGA3D_SURFACE_AUTOGENMIPMAPS | \
493 SVGA3D_SURFACE_VOLUME | \
494 SVGA3D_SURFACE_1D | \
495 SVGA3D_SURFACE_SCREENTARGET | \
496 SVGA3D_SURFACE_MOB_PITCH \
430 ) 497 )
431 498
432#define SVGA3D_SURFACE_DX_ONLY_MASK \ 499#define SVGA3D_SURFACE_DX_ONLY_MASK \
433 ( SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \ 500 ( SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \
501 SVGA3D_SURFACE_STAGING_UPLOAD | \
502 SVGA3D_SURFACE_STAGING_DOWNLOAD | \
434 SVGA3D_SURFACE_TRANSFER_FROM_BUFFER \ 503 SVGA3D_SURFACE_TRANSFER_FROM_BUFFER \
504 )
435 505
436#define SVGA3D_SURFACE_STAGING_MASK \ 506#define SVGA3D_SURFACE_STAGING_MASK \
437 ( SVGA3D_SURFACE_STAGING_UPLOAD | \ 507 ( SVGA3D_SURFACE_STAGING_UPLOAD | \
@@ -487,7 +557,7 @@ typedef enum {
487 557
488/* 558/*
489 * Indicates that this format can be converted to any RGB format for which 559 * Indicates that this format can be converted to any RGB format for which
490 * SVGA3DFORMAT_OP_MEMBEROFGROUP_ARGB is specified 560 * SVGA3DFORMAT_OP_MEMBEROFGROUP_ARGB is specified.
491 */ 561 */
492 SVGA3DFORMAT_OP_CONVERT_TO_ARGB = 0x00002000, 562 SVGA3DFORMAT_OP_CONVERT_TO_ARGB = 0x00002000,
493 563
@@ -498,22 +568,22 @@ typedef enum {
498 568
499/* 569/*
500 * Indicated that this format can be read as an SRGB texture (meaning that the 570 * Indicated that this format can be read as an SRGB texture (meaning that the
501 * sampler will linearize the looked up data) 571 * sampler will linearize the looked up data).
502 */ 572 */
503 SVGA3DFORMAT_OP_SRGBREAD = 0x00008000, 573 SVGA3DFORMAT_OP_SRGBREAD = 0x00008000,
504 574
505/* 575/*
506 * Indicates that this format can be used in the bumpmap instructions 576 * Indicates that this format can be used in the bumpmap instructions.
507 */ 577 */
508 SVGA3DFORMAT_OP_BUMPMAP = 0x00010000, 578 SVGA3DFORMAT_OP_BUMPMAP = 0x00010000,
509 579
510/* 580/*
511 * Indicates that this format can be sampled by the displacement map sampler 581 * Indicates that this format can be sampled by the displacement map sampler.
512 */ 582 */
513 SVGA3DFORMAT_OP_DMAP = 0x00020000, 583 SVGA3DFORMAT_OP_DMAP = 0x00020000,
514 584
515/* 585/*
516 * Indicates that this format cannot be used with texture filtering 586 * Indicates that this format cannot be used with texture filtering.
517 */ 587 */
518 SVGA3DFORMAT_OP_NOFILTER = 0x00040000, 588 SVGA3DFORMAT_OP_NOFILTER = 0x00040000,
519 589
@@ -530,18 +600,18 @@ typedef enum {
530 SVGA3DFORMAT_OP_SRGBWRITE = 0x00100000, 600 SVGA3DFORMAT_OP_SRGBWRITE = 0x00100000,
531 601
532/* 602/*
533 * Indicates that this format cannot be used with alpha blending 603 * Indicates that this format cannot be used with alpha blending.
534 */ 604 */
535 SVGA3DFORMAT_OP_NOALPHABLEND = 0x00200000, 605 SVGA3DFORMAT_OP_NOALPHABLEND = 0x00200000,
536 606
537/* 607/*
538 * Indicates that the device can auto-generated sublevels for resources 608 * Indicates that the device can auto-generated sublevels for resources
539 * of this format 609 * of this format.
540 */ 610 */
541 SVGA3DFORMAT_OP_AUTOGENMIPMAP = 0x00400000, 611 SVGA3DFORMAT_OP_AUTOGENMIPMAP = 0x00400000,
542 612
543/* 613/*
544 * Indicates that this format can be used by vertex texture sampler 614 * Indicates that this format can be used by vertex texture sampler.
545 */ 615 */
546 SVGA3DFORMAT_OP_VERTEXTEXTURE = 0x00800000, 616 SVGA3DFORMAT_OP_VERTEXTEXTURE = 0x00800000,
547 617
@@ -1501,7 +1571,6 @@ union SVGADXQueryResultUnion {
1501#include "vmware_pack_end.h" 1571#include "vmware_pack_end.h"
1502SVGADXQueryResultUnion; 1572SVGADXQueryResultUnion;
1503 1573
1504
1505typedef enum { 1574typedef enum {
1506 SVGA3D_QUERYSTATE_PENDING = 0, /* Query is not finished yet */ 1575 SVGA3D_QUERYSTATE_PENDING = 0, /* Query is not finished yet */
1507 SVGA3D_QUERYSTATE_SUCCEEDED = 1, /* Completed successfully */ 1576 SVGA3D_QUERYSTATE_SUCCEEDED = 1, /* Completed successfully */
@@ -1533,9 +1602,9 @@ typedef
1533struct { 1602struct {
1534 union { 1603 union {
1535 struct { 1604 struct {
1536 uint16 function; /* SVGA3dFogFunction */ 1605 uint16 function; /* SVGA3dFogFunction */
1537 uint8 type; /* SVGA3dFogType */ 1606 uint8 type; /* SVGA3dFogType */
1538 uint8 base; /* SVGA3dFogBase */ 1607 uint8 base; /* SVGA3dFogBase */
1539 }; 1608 };
1540 uint32 uintValue; 1609 uint32 uintValue;
1541 }; 1610 };
@@ -1547,19 +1616,27 @@ SVGA3dFogMode;
1547 * Uniquely identify one image (a 1D/2D/3D array) from a surface. This 1616 * Uniquely identify one image (a 1D/2D/3D array) from a surface. This
1548 * is a surface ID as well as face/mipmap indices. 1617 * is a surface ID as well as face/mipmap indices.
1549 */ 1618 */
1550
1551typedef 1619typedef
1552#include "vmware_pack_begin.h" 1620#include "vmware_pack_begin.h"
1553struct SVGA3dSurfaceImageId { 1621struct SVGA3dSurfaceImageId {
1554 uint32 sid; 1622 uint32 sid;
1555 uint32 face; 1623 uint32 face;
1556 uint32 mipmap; 1624 uint32 mipmap;
1557} 1625}
1558#include "vmware_pack_end.h" 1626#include "vmware_pack_end.h"
1559SVGA3dSurfaceImageId; 1627SVGA3dSurfaceImageId;
1560 1628
1561typedef 1629typedef
1562#include "vmware_pack_begin.h" 1630#include "vmware_pack_begin.h"
1631struct SVGA3dSubSurfaceId {
1632 uint32 sid;
1633 uint32 subResourceId;
1634}
1635#include "vmware_pack_end.h"
1636SVGA3dSubSurfaceId;
1637
1638typedef
1639#include "vmware_pack_begin.h"
1563struct { 1640struct {
1564 uint32 width; 1641 uint32 width;
1565 uint32 height; 1642 uint32 height;
@@ -1582,13 +1659,18 @@ typedef enum {
1582 SVGA_OTABLE_DX9_MAX = 5, 1659 SVGA_OTABLE_DX9_MAX = 5,
1583 1660
1584 SVGA_OTABLE_DXCONTEXT = 5, 1661 SVGA_OTABLE_DXCONTEXT = 5,
1585 SVGA_OTABLE_MAX = 6 1662 SVGA_OTABLE_DX_MAX = 6,
1586} SVGAOTableType;
1587 1663
1588/* 1664 SVGA_OTABLE_RESERVED1 = 6,
1589 * Deprecated. 1665 SVGA_OTABLE_RESERVED2 = 7,
1590 */ 1666
1591#define SVGA_OTABLE_COUNT 4 1667 /*
1668 * Additions to this table need to be tied to HW-version features and
1669 * checkpointed accordingly.
1670 */
1671 SVGA_OTABLE_DEVEL_MAX = 8,
1672 SVGA_OTABLE_MAX = 8
1673} SVGAOTableType;
1592 1674
1593typedef enum { 1675typedef enum {
1594 SVGA_COTABLE_MIN = 0, 1676 SVGA_COTABLE_MIN = 0,
@@ -1605,7 +1687,7 @@ typedef enum {
1605 SVGA_COTABLE_DXSHADER = 10, 1687 SVGA_COTABLE_DXSHADER = 10,
1606 SVGA_COTABLE_DX10_MAX = 11, 1688 SVGA_COTABLE_DX10_MAX = 11,
1607 SVGA_COTABLE_UAVIEW = 11, 1689 SVGA_COTABLE_UAVIEW = 11,
1608 SVGA_COTABLE_MAX 1690 SVGA_COTABLE_MAX = 12,
1609} SVGACOTableType; 1691} SVGACOTableType;
1610 1692
1611/* 1693/*
@@ -1626,8 +1708,37 @@ typedef enum SVGAMobFormat {
1626 SVGA3D_MOBFMT_PREDX_MAX = 7, 1708 SVGA3D_MOBFMT_PREDX_MAX = 7,
1627 SVGA3D_MOBFMT_EMPTY = 7, 1709 SVGA3D_MOBFMT_EMPTY = 7,
1628 SVGA3D_MOBFMT_MAX, 1710 SVGA3D_MOBFMT_MAX,
1711
1712 /*
1713 * This isn't actually used by the guest, but is a mob-format used
1714 * internally by the SVGA device (and is therefore not binary compatible).
1715 */
1716 SVGA3D_MOBFMT_HB,
1629} SVGAMobFormat; 1717} SVGAMobFormat;
1630 1718
1631#define SVGA3D_MOB_EMPTY_BASE 1 1719#define SVGA3D_MOB_EMPTY_BASE 1
1632 1720
1721/*
1722 * Multisample pattern types.
1723 */
1724
1725typedef enum SVGA3dMSPattern {
1726 SVGA3D_MS_PATTERN_NONE = 0,
1727 SVGA3D_MS_PATTERN_MIN = 0,
1728 SVGA3D_MS_PATTERN_STANDARD = 1,
1729 SVGA3D_MS_PATTERN_CENTER = 2,
1730 SVGA3D_MS_PATTERN_MAX = 3,
1731} SVGA3dMSPattern;
1732
1733/*
1734 * Precision settings for each sample.
1735 */
1736
1737typedef enum SVGA3dMSQualityLevel {
1738 SVGA3D_MS_QUALITY_NONE = 0,
1739 SVGA3D_MS_QUALITY_MIN = 0,
1740 SVGA3D_MS_QUALITY_FULL = 1,
1741 SVGA3D_MS_QUALITY_MAX = 2,
1742} SVGA3dMSQualityLevel;
1743
1633#endif /* _SVGA3D_TYPES_H_ */ 1744#endif /* _SVGA3D_TYPES_H_ */
diff --git a/drivers/gpu/drm/vmwgfx/device_include/svga_reg.h b/drivers/gpu/drm/vmwgfx/device_include/svga_reg.h
index cdd48a3763db..ab8ea6b3cdb1 100644
--- a/drivers/gpu/drm/vmwgfx/device_include/svga_reg.h
+++ b/drivers/gpu/drm/vmwgfx/device_include/svga_reg.h
@@ -63,16 +63,26 @@ typedef uint32 SVGAMobId;
63#define SVGA_MAX_BITS_PER_PIXEL 32 63#define SVGA_MAX_BITS_PER_PIXEL 32
64#define SVGA_MAX_DEPTH 24 64#define SVGA_MAX_DEPTH 24
65#define SVGA_MAX_DISPLAYS 10 65#define SVGA_MAX_DISPLAYS 10
66#define SVGA_MAX_SCREEN_SIZE 8192
67#define SVGA_SCREEN_ROOT_LIMIT (SVGA_MAX_SCREEN_SIZE * SVGA_MAX_DISPLAYS)
68
66 69
67/* 70/*
68 * Legal values for the SVGA_REG_CURSOR_ON register in old-fashioned 71 * Legal values for the SVGA_REG_CURSOR_ON register in old-fashioned
69 * cursor bypass mode. This is still supported, but no new guest 72 * cursor bypass mode. This is still supported, but no new guest
70 * drivers should use it. 73 * drivers should use it.
71 */ 74 */
72#define SVGA_CURSOR_ON_HIDE 0x0 /* Must be 0 to maintain backward compatibility */ 75#define SVGA_CURSOR_ON_HIDE 0x0
73#define SVGA_CURSOR_ON_SHOW 0x1 /* Must be 1 to maintain backward compatibility */ 76#define SVGA_CURSOR_ON_SHOW 0x1
74#define SVGA_CURSOR_ON_REMOVE_FROM_FB 0x2 /* Remove the cursor from the framebuffer because we need to see what's under it */ 77
75#define SVGA_CURSOR_ON_RESTORE_TO_FB 0x3 /* Put the cursor back in the framebuffer so the user can see it */ 78/*
79 * Remove the cursor from the framebuffer
80 * because we need to see what's under it
81 */
82#define SVGA_CURSOR_ON_REMOVE_FROM_FB 0x2
83
84/* Put the cursor back in the framebuffer so the user can see it */
85#define SVGA_CURSOR_ON_RESTORE_TO_FB 0x3
76 86
77/* 87/*
78 * The maximum framebuffer size that can traced for guests unless the 88 * The maximum framebuffer size that can traced for guests unless the
@@ -101,7 +111,10 @@ typedef uint32 SVGAMobId;
101#define SVGA_VERSION_0 0 111#define SVGA_VERSION_0 0
102#define SVGA_ID_0 SVGA_MAKE_ID(SVGA_VERSION_0) 112#define SVGA_ID_0 SVGA_MAKE_ID(SVGA_VERSION_0)
103 113
104/* "Invalid" value for all SVGA IDs. (Version ID, screen object ID, surface ID...) */ 114/*
115 * "Invalid" value for all SVGA IDs.
116 * (Version ID, screen object ID, surface ID...)
117 */
105#define SVGA_ID_INVALID 0xFFFFFFFF 118#define SVGA_ID_INVALID 0xFFFFFFFF
106 119
107/* Port offsets, relative to BAR0 */ 120/* Port offsets, relative to BAR0 */
@@ -154,7 +167,7 @@ enum {
154 SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */ 167 SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */
155 SVGA_REG_SYNC = 21, /* See "FIFO Synchronization Registers" */ 168 SVGA_REG_SYNC = 21, /* See "FIFO Synchronization Registers" */
156 SVGA_REG_BUSY = 22, /* See "FIFO Synchronization Registers" */ 169 SVGA_REG_BUSY = 22, /* See "FIFO Synchronization Registers" */
157 SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */ 170 SVGA_REG_GUEST_ID = 23, /* (Deprecated) */
158 SVGA_REG_CURSOR_ID = 24, /* (Deprecated) */ 171 SVGA_REG_CURSOR_ID = 24, /* (Deprecated) */
159 SVGA_REG_CURSOR_X = 25, /* (Deprecated) */ 172 SVGA_REG_CURSOR_X = 25, /* (Deprecated) */
160 SVGA_REG_CURSOR_Y = 26, /* (Deprecated) */ 173 SVGA_REG_CURSOR_Y = 26, /* (Deprecated) */
@@ -186,7 +199,14 @@ enum {
186 SVGA_REG_MEMORY_SIZE = 47, /* Total dedicated device memory excluding FIFO */ 199 SVGA_REG_MEMORY_SIZE = 47, /* Total dedicated device memory excluding FIFO */
187 SVGA_REG_COMMAND_LOW = 48, /* Lower 32 bits and submits commands */ 200 SVGA_REG_COMMAND_LOW = 48, /* Lower 32 bits and submits commands */
188 SVGA_REG_COMMAND_HIGH = 49, /* Upper 32 bits of command buffer PA */ 201 SVGA_REG_COMMAND_HIGH = 49, /* Upper 32 bits of command buffer PA */
189 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM = 50, /* Max primary memory */ 202
203 /*
204 * Max primary memory.
205 * See SVGA_CAP_NO_BB_RESTRICTION.
206 */
207 SVGA_REG_MAX_PRIMARY_MEM = 50,
208 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM = 50,
209
190 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB = 51, /* Sugested limit on mob mem */ 210 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB = 51, /* Sugested limit on mob mem */
191 SVGA_REG_DEV_CAP = 52, /* Write dev cap index, read value */ 211 SVGA_REG_DEV_CAP = 52, /* Write dev cap index, read value */
192 SVGA_REG_CMD_PREPEND_LOW = 53, 212 SVGA_REG_CMD_PREPEND_LOW = 53,
@@ -194,7 +214,10 @@ enum {
194 SVGA_REG_SCREENTARGET_MAX_WIDTH = 55, 214 SVGA_REG_SCREENTARGET_MAX_WIDTH = 55,
195 SVGA_REG_SCREENTARGET_MAX_HEIGHT = 56, 215 SVGA_REG_SCREENTARGET_MAX_HEIGHT = 56,
196 SVGA_REG_MOB_MAX_SIZE = 57, 216 SVGA_REG_MOB_MAX_SIZE = 57,
197 SVGA_REG_TOP = 58, /* Must be 1 more than the last register */ 217 SVGA_REG_BLANK_SCREEN_TARGETS = 58,
218 SVGA_REG_CAP2 = 59,
219 SVGA_REG_DEVEL_CAP = 60,
220 SVGA_REG_TOP = 61, /* Must be 1 more than the last register */
198 221
199 SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */ 222 SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */
200 /* Next 768 (== 256*3) registers exist for colormap */ 223 /* Next 768 (== 256*3) registers exist for colormap */
@@ -392,6 +415,7 @@ typedef enum {
392 SVGA_CB_CONTEXT_0 = 0x0, 415 SVGA_CB_CONTEXT_0 = 0x0,
393 SVGA_CB_CONTEXT_1 = 0x1, /* Supported with SVGA_CAP_HP_CMD_QUEUE */ 416 SVGA_CB_CONTEXT_1 = 0x1, /* Supported with SVGA_CAP_HP_CMD_QUEUE */
394 SVGA_CB_CONTEXT_MAX = 0x2, 417 SVGA_CB_CONTEXT_MAX = 0x2,
418 SVGA_CB_CONTEXT_HP_MAX = 0x2,
395} SVGACBContext; 419} SVGACBContext;
396 420
397 421
@@ -448,6 +472,18 @@ typedef enum {
448 * due to an error. No IRQ is raised. 472 * due to an error. No IRQ is raised.
449 */ 473 */
450 SVGA_CB_STATUS_SUBMISSION_ERROR = 6, 474 SVGA_CB_STATUS_SUBMISSION_ERROR = 6,
475
476 /*
477 * Written by the host when the host finished a
478 * SVGA_DC_CMD_ASYNC_STOP_QUEUE request for this command buffer
479 * queue. The offset of the first byte not processed is stored in
480 * the errorOffset field of the command buffer header. All guest
481 * visible side effects of commands till that point are guaranteed
482 * to be finished before this is written. The
483 * SVGA_IRQFLAG_COMMAND_BUFFER IRQ is raised as long as the
484 * SVGA_CB_FLAG_NO_IRQ is not set.
485 */
486 SVGA_CB_STATUS_PARTIAL_COMPLETE = 7,
451} SVGACBStatus; 487} SVGACBStatus;
452 488
453typedef enum { 489typedef enum {
@@ -460,8 +496,8 @@ typedef enum {
460typedef 496typedef
461#include "vmware_pack_begin.h" 497#include "vmware_pack_begin.h"
462struct { 498struct {
463 volatile SVGACBStatus status; 499 volatile SVGACBStatus status; /* Modified by device. */
464 volatile uint32 errorOffset; 500 volatile uint32 errorOffset; /* Modified by device. */
465 uint64 id; 501 uint64 id;
466 SVGACBFlags flags; 502 SVGACBFlags flags;
467 uint32 length; 503 uint32 length;
@@ -472,7 +508,9 @@ struct {
472 uint32 mobOffset; 508 uint32 mobOffset;
473 } mob; 509 } mob;
474 } ptr; 510 } ptr;
475 uint32 offset; /* Valid if CMD_BUFFERS_2 cap set, must be zero otherwise */ 511 uint32 offset; /* Valid if CMD_BUFFERS_2 cap set, must be zero otherwise,
512 * modified by device.
513 */
476 uint32 dxContext; /* Valid if DX_CONTEXT flag set, must be zero otherwise */ 514 uint32 dxContext; /* Valid if DX_CONTEXT flag set, must be zero otherwise */
477 uint32 mustBeZero[6]; 515 uint32 mustBeZero[6];
478} 516}
@@ -483,20 +521,26 @@ typedef enum {
483 SVGA_DC_CMD_NOP = 0, 521 SVGA_DC_CMD_NOP = 0,
484 SVGA_DC_CMD_START_STOP_CONTEXT = 1, 522 SVGA_DC_CMD_START_STOP_CONTEXT = 1,
485 SVGA_DC_CMD_PREEMPT = 2, 523 SVGA_DC_CMD_PREEMPT = 2,
486 SVGA_DC_CMD_MAX = 3, 524 SVGA_DC_CMD_START_QUEUE = 3, /* Requires SVGA_CAP_HP_CMD_QUEUE */
487 SVGA_DC_CMD_FORCE_UINT = MAX_UINT32, 525 SVGA_DC_CMD_ASYNC_STOP_QUEUE = 4, /* Requires SVGA_CAP_HP_CMD_QUEUE */
526 SVGA_DC_CMD_EMPTY_CONTEXT_QUEUE = 5, /* Requires SVGA_CAP_HP_CMD_QUEUE */
527 SVGA_DC_CMD_MAX = 6,
488} SVGADeviceContextCmdId; 528} SVGADeviceContextCmdId;
489 529
490typedef struct { 530/*
531 * Starts or stops both SVGA_CB_CONTEXT_0 and SVGA_CB_CONTEXT_1.
532 */
533
534typedef struct SVGADCCmdStartStop {
491 uint32 enable; 535 uint32 enable;
492 SVGACBContext context; 536 SVGACBContext context; /* Must be zero */
493} SVGADCCmdStartStop; 537} SVGADCCmdStartStop;
494 538
495/* 539/*
496 * SVGADCCmdPreempt -- 540 * SVGADCCmdPreempt --
497 * 541 *
498 * This command allows the guest to request that all command buffers 542 * This command allows the guest to request that all command buffers
499 * on the specified context be preempted that can be. After execution 543 * on SVGA_CB_CONTEXT_0 be preempted that can be. After execution
500 * of this command all command buffers that were preempted will 544 * of this command all command buffers that were preempted will
501 * already have SVGA_CB_STATUS_PREEMPTED written into the status 545 * already have SVGA_CB_STATUS_PREEMPTED written into the status
502 * field. The device might still be processing a command buffer, 546 * field. The device might still be processing a command buffer,
@@ -506,12 +550,69 @@ typedef struct {
506 * command buffer header set to zero. 550 * command buffer header set to zero.
507 */ 551 */
508 552
509typedef struct { 553typedef struct SVGADCCmdPreempt {
510 SVGACBContext context; 554 SVGACBContext context; /* Must be zero */
511 uint32 ignoreIDZero; 555 uint32 ignoreIDZero;
512} SVGADCCmdPreempt; 556} SVGADCCmdPreempt;
513 557
514/* 558/*
559 * Starts the requested command buffer processing queue. Valid only
560 * if the SVGA_CAP_HP_CMD_QUEUE cap is set.
561 *
562 * For a command queue to be considered runnable it must be enabled
563 * and any corresponding higher priority queues must also be enabled.
564 * For example in order for command buffers to be processed on
565 * SVGA_CB_CONTEXT_0 both SVGA_CB_CONTEXT_0 and SVGA_CB_CONTEXT_1 must
566 * be enabled. But for commands to be runnable on SVGA_CB_CONTEXT_1
567 * only that queue must be enabled.
568 */
569
570typedef struct SVGADCCmdStartQueue {
571 SVGACBContext context;
572} SVGADCCmdStartQueue;
573
574/*
575 * Requests the SVGA device to stop processing the requested command
576 * buffer queue as soon as possible. The guest knows the stop has
577 * completed when one of the following happens.
578 *
579 * 1) A command buffer status of SVGA_CB_STATUS_PARTIAL_COMPLETE is returned
580 * 2) A command buffer error is encountered with would stop the queue
581 * regardless of the async stop request.
582 * 3) All command buffers that have been submitted complete successfully.
583 * 4) The stop completes synchronously if no command buffers are
584 * active on the queue when it is issued.
585 *
586 * If the command queue is not in a runnable state there is no
587 * guarentee this async stop will finish. For instance if the high
588 * priority queue is not enabled and a stop is requested on the low
589 * priority queue, the high priority queue must be reenabled to
590 * guarantee that the async stop will finish.
591 *
592 * This command along with SVGA_DC_CMD_EMPTY_CONTEXT_QUEUE can be used
593 * to implement mid command buffer preemption.
594 *
595 * Valid only if the SVGA_CAP_HP_CMD_QUEUE cap is set.
596 */
597
598typedef struct SVGADCCmdAsyncStopQueue {
599 SVGACBContext context;
600} SVGADCCmdAsyncStopQueue;
601
602/*
603 * Requests the SVGA device to throw away any full command buffers on
604 * the requested command queue that have not been started. For a
605 * driver to know which command buffers were thrown away a driver
606 * should only issue this command when the queue is stopped, for
607 * whatever reason.
608 */
609
610typedef struct SVGADCCmdEmptyQueue {
611 SVGACBContext context;
612} SVGADCCmdEmptyQueue;
613
614
615/*
515 * SVGAGMRImageFormat -- 616 * SVGAGMRImageFormat --
516 * 617 *
517 * This is a packed representation of the source 2D image format 618 * This is a packed representation of the source 2D image format
@@ -536,7 +637,7 @@ typedef struct SVGAGMRImageFormat {
536 struct { 637 struct {
537 uint32 bitsPerPixel : 8; 638 uint32 bitsPerPixel : 8;
538 uint32 colorDepth : 8; 639 uint32 colorDepth : 8;
539 uint32 reserved : 16; /* Must be zero */ 640 uint32 reserved : 16; /* Must be zero */
540 }; 641 };
541 642
542 uint32 value; 643 uint32 value;
@@ -700,6 +801,8 @@ SVGASignedPoint;
700 * large enough to express any possible topology without holes between 801 * large enough to express any possible topology without holes between
701 * monitors.) 802 * monitors.)
702 * 803 *
804 * SVGA_CAP_CAP2_REGISTER --
805 * If this cap is present, the SVGA_REG_CAP2 register is supported.
703 */ 806 */
704 807
705#define SVGA_CAP_NONE 0x00000000 808#define SVGA_CAP_NONE 0x00000000
@@ -726,8 +829,29 @@ SVGASignedPoint;
726#define SVGA_CAP_DX 0x10000000 829#define SVGA_CAP_DX 0x10000000
727#define SVGA_CAP_HP_CMD_QUEUE 0x20000000 830#define SVGA_CAP_HP_CMD_QUEUE 0x20000000
728#define SVGA_CAP_NO_BB_RESTRICTION 0x40000000 831#define SVGA_CAP_NO_BB_RESTRICTION 0x40000000
832#define SVGA_CAP_CAP2_REGISTER 0x80000000
729 833
730#define SVGA_CAP_CMD_RESERVED 0x80000000 834/*
835 * The SVGA_REG_CAP2 register is an additional set of SVGA capability bits.
836 *
837 * SVGA_CAP2_GROW_OTABLE --
838 * Allow the GrowOTable/DXGrowCOTable commands.
839 *
840 * SVGA_CAP2_INTRA_SURFACE_COPY --
841 * Allow the IntraSurfaceCopy command.
842 *
843 * SVGA_CAP2_DX2 --
844 * Allow the DefineGBSurface_v3, WholeSurfaceCopy.
845 *
846 * SVGA_CAP2_RESERVED --
847 * Reserve the last bit for extending the SVGA capabilities to some
848 * future mechanisms.
849 */
850#define SVGA_CAP2_NONE 0x00000000
851#define SVGA_CAP2_GROW_OTABLE 0x00000001
852#define SVGA_CAP2_INTRA_SURFACE_COPY 0x00000002
853#define SVGA_CAP2_DX2 0x00000004
854#define SVGA_CAP2_RESERVED 0x80000000
731 855
732 856
733/* 857/*
@@ -749,7 +873,8 @@ typedef enum {
749 SVGABackdoorCapDeviceCaps = 0, 873 SVGABackdoorCapDeviceCaps = 0,
750 SVGABackdoorCapFifoCaps = 1, 874 SVGABackdoorCapFifoCaps = 1,
751 SVGABackdoorCap3dHWVersion = 2, 875 SVGABackdoorCap3dHWVersion = 2,
752 SVGABackdoorCapMax = 3, 876 SVGABackdoorCapDeviceCaps2 = 3,
877 SVGABackdoorCapMax = 4,
753} SVGABackdoorCapType; 878} SVGABackdoorCapType;
754 879
755 880
@@ -1941,16 +2066,6 @@ SVGAFifoCmdRemapGMR2;
1941 2066
1942#define SVGA_VRAM_SIZE_W2K (64 * 1024 * 1024) /* 64 MB */ 2067#define SVGA_VRAM_SIZE_W2K (64 * 1024 * 1024) /* 64 MB */
1943 2068
1944/*
1945 * To simplify autoDetect display configuration, support a minimum of
1946 * two 1920x1200 monitors, 32bpp, side-by-side, optionally rotated:
1947 * numDisplays = 2
1948 * maxWidth = numDisplay * 1920 = 3840
1949 * maxHeight = rotated width of single monitor = 1920
1950 * vramSize = maxWidth * maxHeight * 4 = 29491200
1951 */
1952#define SVGA_VRAM_SIZE_AUTODETECT (32 * 1024 * 1024)
1953
1954#if defined(VMX86_SERVER) 2069#if defined(VMX86_SERVER)
1955#define SVGA_VRAM_SIZE (4 * 1024 * 1024) 2070#define SVGA_VRAM_SIZE (4 * 1024 * 1024)
1956#define SVGA_VRAM_SIZE_3D (64 * 1024 * 1024) 2071#define SVGA_VRAM_SIZE_3D (64 * 1024 * 1024)
diff --git a/drivers/gpu/drm/vmwgfx/device_include/svga_types.h b/drivers/gpu/drm/vmwgfx/device_include/svga_types.h
index 2e8ba4df8de9..2ba15f131858 100644
--- a/drivers/gpu/drm/vmwgfx/device_include/svga_types.h
+++ b/drivers/gpu/drm/vmwgfx/device_include/svga_types.h
@@ -40,7 +40,10 @@ typedef uint64 PPN64;
40 40
41typedef bool Bool; 41typedef bool Bool;
42 42
43#define MAX_UINT64 U64_MAX
43#define MAX_UINT32 U32_MAX 44#define MAX_UINT32 U32_MAX
44#define MAX_UINT16 U16_MAX 45#define MAX_UINT16 U16_MAX
45 46
47#define CONST64U(x) x##ULL
48
46#endif 49#endif
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
index 45dfff7733d6..1128420de2c0 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
@@ -884,7 +884,7 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
884 884
885 if (dev_priv->has_mob) { 885 if (dev_priv->has_mob) {
886 spin_lock(&dev_priv->cap_lock); 886 spin_lock(&dev_priv->cap_lock);
887 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DX); 887 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DXCONTEXT);
888 dev_priv->has_dx = !!vmw_read(dev_priv, SVGA_REG_DEV_CAP); 888 dev_priv->has_dx = !!vmw_read(dev_priv, SVGA_REG_DEV_CAP);
889 spin_unlock(&dev_priv->cap_lock); 889 spin_unlock(&dev_priv->cap_lock);
890 } 890 }
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
index a8b194655c40..2d6efc36288f 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
@@ -3230,9 +3230,9 @@ static const struct vmw_cmd_entry vmw_cmd_entries[SVGA_3D_CMD_MAX] = {
3230 false, false, false), 3230 false, false, false),
3231 VMW_CMD_DEF(SVGA_3D_CMD_SCREEN_DMA, &vmw_cmd_invalid, 3231 VMW_CMD_DEF(SVGA_3D_CMD_SCREEN_DMA, &vmw_cmd_invalid,
3232 false, false, false), 3232 false, false, false),
3233 VMW_CMD_DEF(SVGA_3D_CMD_SET_UNITY_SURFACE_COOKIE, &vmw_cmd_invalid, 3233 VMW_CMD_DEF(SVGA_3D_CMD_DEAD1, &vmw_cmd_invalid,
3234 false, false, false), 3234 false, false, false),
3235 VMW_CMD_DEF(SVGA_3D_CMD_OPEN_CONTEXT_SURFACE, &vmw_cmd_invalid, 3235 VMW_CMD_DEF(SVGA_3D_CMD_DEAD2, &vmw_cmd_invalid,
3236 false, false, false), 3236 false, false, false),
3237 VMW_CMD_DEF(SVGA_3D_CMD_LOGICOPS_BITBLT, &vmw_cmd_invalid, 3237 VMW_CMD_DEF(SVGA_3D_CMD_LOGICOPS_BITBLT, &vmw_cmd_invalid,
3238 false, false, false), 3238 false, false, false),
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c b/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
index 5e0c8f775c92..6872c7ee8a08 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
@@ -122,15 +122,12 @@ int vmw_getparam_ioctl(struct drm_device *dev, void *data,
122 122
123static u32 vmw_mask_multisample(unsigned int cap, u32 fmt_value) 123static u32 vmw_mask_multisample(unsigned int cap, u32 fmt_value)
124{ 124{
125 /* If the header is updated, update the format test as well! */ 125 /*
126 BUILD_BUG_ON(SVGA3D_DEVCAP_DXFMT_BC5_UNORM + 1 != SVGA3D_DEVCAP_MAX); 126 * A version of user-space exists which use MULTISAMPLE_MASKABLESAMPLES
127 127 * to check the sample count supported by virtual device. Since there
128 if (cap >= SVGA3D_DEVCAP_DXFMT_X8R8G8B8 && 128 * never was support for multisample count for backing MOB return 0.
129 cap <= SVGA3D_DEVCAP_DXFMT_BC5_UNORM) 129 */
130 fmt_value &= ~(SVGADX_DXFMT_MULTISAMPLE_2 | 130 if (cap == SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES)
131 SVGADX_DXFMT_MULTISAMPLE_4 |
132 SVGADX_DXFMT_MULTISAMPLE_8);
133 else if (cap == SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES)
134 return 0; 131 return 0;
135 132
136 return fmt_value; 133 return fmt_value;
generated by cgit v1.2.2 (git 2.25.0) at 2026-05-27 14:25:13 -0400