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authorYakir Yang <ykk@rock-chips.com>2016-06-29 05:16:05 -0400
committerYakir Yang <ykk@rock-chips.com>2016-07-05 09:53:41 -0400
commitdc1c93bef4690f7262bc10cf75a74564b477224d (patch)
tree805e39b55e7e8cf4de163e0b2de73f171cb586ac /drivers/gpu/drm
parent7608a9fb37b02c5cce3199f87eafb0a6c07d6f93 (diff)
drm/rockchip: analogix_dp: introduce the pclk for grf
For RK3399's GRF module, if we want to operate the graphic related grf registers, we need to enable the pclk_vio_grf which supply power for VIO GRF IOs, so it's better to introduce an optional grf clock in driver. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Tomasz Figa <tomasz.figa@chromium.com>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/rockchip/analogix_dp-rockchip.c23
1 files changed, 20 insertions, 3 deletions
diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
index 850edc4d99c8..e81e19a660ad 100644
--- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -64,6 +64,7 @@ struct rockchip_dp_device {
64 struct drm_display_mode mode; 64 struct drm_display_mode mode;
65 65
66 struct clk *pclk; 66 struct clk *pclk;
67 struct clk *grfclk;
67 struct regmap *grf; 68 struct regmap *grf;
68 struct reset_control *rst; 69 struct reset_control *rst;
69 70
@@ -160,11 +161,17 @@ static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder)
160 161
161 dev_dbg(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG"); 162 dev_dbg(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");
162 163
163 ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val); 164 ret = clk_prepare_enable(dp->grfclk);
164 if (ret != 0) { 165 if (ret < 0) {
165 dev_err(dp->dev, "Could not write to GRF: %d\n", ret); 166 dev_err(dp->dev, "failed to enable grfclk %d\n", ret);
166 return; 167 return;
167 } 168 }
169
170 ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val);
171 if (ret != 0)
172 dev_err(dp->dev, "Could not write to GRF: %d\n", ret);
173
174 clk_disable_unprepare(dp->grfclk);
168} 175}
169 176
170static void rockchip_dp_drm_encoder_nop(struct drm_encoder *encoder) 177static void rockchip_dp_drm_encoder_nop(struct drm_encoder *encoder)
@@ -234,6 +241,16 @@ static int rockchip_dp_init(struct rockchip_dp_device *dp)
234 return PTR_ERR(dp->grf); 241 return PTR_ERR(dp->grf);
235 } 242 }
236 243
244 dp->grfclk = devm_clk_get(dev, "grf");
245 if (PTR_ERR(dp->grfclk) == -ENOENT) {
246 dp->grfclk = NULL;
247 } else if (PTR_ERR(dp->grfclk) == -EPROBE_DEFER) {
248 return -EPROBE_DEFER;
249 } else if (IS_ERR(dp->grfclk)) {
250 dev_err(dev, "failed to get grf clock\n");
251 return PTR_ERR(dp->grfclk);
252 }
253
237 dp->pclk = devm_clk_get(dev, "pclk"); 254 dp->pclk = devm_clk_get(dev, "pclk");
238 if (IS_ERR(dp->pclk)) { 255 if (IS_ERR(dp->pclk)) {
239 dev_err(dev, "failed to get pclk property\n"); 256 dev_err(dev, "failed to get pclk property\n");