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authorChristian König <christian.koenig@amd.com>2016-03-01 09:51:53 -0500
committerAlex Deucher <alexander.deucher@amd.com>2016-03-08 11:01:50 -0500
commitd564a06e1c9c285bab1c1579c18c811aa1271884 (patch)
tree049470cb0c185c934e831b2f5b3ade387827e5ee /drivers/gpu/drm
parentb8c7b39ec1db98199df5bee33ca145ed9c2c62e7 (diff)
drm/amdgpu: if a GDS switch is needed emit a pipeline sync as well
Otherwise we might change the GDS settings while they are still in use. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c22
1 files changed, 12 insertions, 10 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 9a9abbab9b7c..a0896c761108 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -254,22 +254,24 @@ void amdgpu_vm_flush(struct amdgpu_ring *ring,
254{ 254{
255 struct amdgpu_device *adev = ring->adev; 255 struct amdgpu_device *adev = ring->adev;
256 struct amdgpu_vm_manager_id *mgr_id = &adev->vm_manager.ids[vm_id]; 256 struct amdgpu_vm_manager_id *mgr_id = &adev->vm_manager.ids[vm_id];
257 bool gds_switch_needed = ring->funcs->emit_gds_switch && (
258 mgr_id->gds_base != gds_base ||
259 mgr_id->gds_size != gds_size ||
260 mgr_id->gws_base != gws_base ||
261 mgr_id->gws_size != gws_size ||
262 mgr_id->oa_base != oa_base ||
263 mgr_id->oa_size != oa_size);
264
265 if (ring->funcs->emit_pipeline_sync && (
266 pd_addr != AMDGPU_VM_NO_FLUSH || gds_switch_needed))
267 amdgpu_ring_emit_pipeline_sync(ring);
257 268
258 if (pd_addr != AMDGPU_VM_NO_FLUSH) { 269 if (pd_addr != AMDGPU_VM_NO_FLUSH) {
259 trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id); 270 trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id);
260 if (ring->funcs->emit_pipeline_sync)
261 amdgpu_ring_emit_pipeline_sync(ring);
262 amdgpu_ring_emit_vm_flush(ring, vm_id, pd_addr); 271 amdgpu_ring_emit_vm_flush(ring, vm_id, pd_addr);
263 } 272 }
264 273
265 if (ring->funcs->emit_gds_switch && ( 274 if (gds_switch_needed) {
266 mgr_id->gds_base != gds_base ||
267 mgr_id->gds_size != gds_size ||
268 mgr_id->gws_base != gws_base ||
269 mgr_id->gws_size != gws_size ||
270 mgr_id->oa_base != oa_base ||
271 mgr_id->oa_size != oa_size)) {
272
273 mgr_id->gds_base = gds_base; 275 mgr_id->gds_base = gds_base;
274 mgr_id->gds_size = gds_size; 276 mgr_id->gds_size = gds_size;
275 mgr_id->gws_base = gws_base; 277 mgr_id->gws_base = gws_base;