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authorKrzysztof Kozlowski <krzk@kernel.org>2017-12-26 08:07:19 -0500
committerInki Dae <inki.dae@samsung.com>2018-01-01 18:38:49 -0500
commitca52c7121f80eb13176e04645010f9c4bce375d6 (patch)
tree6297dadb6032f72aaf44cbcf8ca25273238d80af /drivers/gpu/drm
parent4f52e55081fb81d6348ecca1f5e2cd45480ca559 (diff)
drm/exynos/decon: Add include guard to the Exynos7 header
Although header is included only once but still having an include guard is a good practice. To avoid confusion, add SoC prefix to existing Exynos5433 header include guard. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Inki Dae <inki.dae@samsung.com>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/exynos/regs-decon5433.h6
-rw-r--r--drivers/gpu/drm/exynos/regs-decon7.h5
2 files changed, 8 insertions, 3 deletions
diff --git a/drivers/gpu/drm/exynos/regs-decon5433.h b/drivers/gpu/drm/exynos/regs-decon5433.h
index 78957c9626f5..19ad9e47945e 100644
--- a/drivers/gpu/drm/exynos/regs-decon5433.h
+++ b/drivers/gpu/drm/exynos/regs-decon5433.h
@@ -6,8 +6,8 @@
6 * published by the Free Software Foundationr 6 * published by the Free Software Foundationr
7 */ 7 */
8 8
9#ifndef EXYNOS_REGS_DECON_H 9#ifndef EXYNOS_REGS_DECON5433_H
10#define EXYNOS_REGS_DECON_H 10#define EXYNOS_REGS_DECON5433_H
11 11
12/* Exynos543X DECON */ 12/* Exynos543X DECON */
13#define DECON_VIDCON0 0x0000 13#define DECON_VIDCON0 0x0000
@@ -206,4 +206,4 @@
206#define CRCCTRL_CRCEN (0x1 << 0) 206#define CRCCTRL_CRCEN (0x1 << 0)
207#define CRCCTRL_MASK (0x7) 207#define CRCCTRL_MASK (0x7)
208 208
209#endif /* EXYNOS_REGS_DECON_H */ 209#endif /* EXYNOS_REGS_DECON5433_H */
diff --git a/drivers/gpu/drm/exynos/regs-decon7.h b/drivers/gpu/drm/exynos/regs-decon7.h
index 339ea1007ff5..5df7765d2397 100644
--- a/drivers/gpu/drm/exynos/regs-decon7.h
+++ b/drivers/gpu/drm/exynos/regs-decon7.h
@@ -8,6 +8,9 @@
8 * option) any later version. 8 * option) any later version.
9 */ 9 */
10 10
11#ifndef EXYNOS_REGS_DECON7_H
12#define EXYNOS_REGS_DECON7_H
13
11/* VIDCON0 */ 14/* VIDCON0 */
12#define VIDCON0 0x00 15#define VIDCON0 0x00
13 16
@@ -346,3 +349,5 @@
346 349
347#define DECON_UPDATE_SLAVE_SYNC (1 << 4) 350#define DECON_UPDATE_SLAVE_SYNC (1 << 4)
348#define DECON_UPDATE_STANDALONE_F (1 << 0) 351#define DECON_UPDATE_STANDALONE_F (1 << 0)
352
353#endif /* EXYNOS_REGS_DECON7_H */