diff options
author | Dave Airlie <airlied@redhat.com> | 2018-05-15 01:33:29 -0400 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2018-05-15 01:33:30 -0400 |
commit | ba72385b3319752967fdec96e19d45b71d217586 (patch) | |
tree | 63bd2ae9a78aa193c0439427ba4ab37f15a0470b /drivers/gpu/drm | |
parent | 9037d4b98b255979c6636045794775f5a89cc623 (diff) | |
parent | 72ac6969033dc9f5e526566240a3a7934f0916ee (diff) |
Merge branch 'mediatek-drm-next-4.18' of https://github.com/ckhu-mediatek/linux.git-tags into drm-next
Signed-off-by: Dave Airlie <airlied@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1525670872.3147.6.camel@mtksdaap41
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r-- | drivers/gpu/drm/mediatek/Kconfig | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/mediatek/mtk_dpi.c | 60 | ||||
-rw-r--r-- | drivers/gpu/drm/mediatek/mtk_drm_gem.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/mediatek/mtk_dsi.c | 14 |
4 files changed, 34 insertions, 43 deletions
diff --git a/drivers/gpu/drm/mediatek/Kconfig b/drivers/gpu/drm/mediatek/Kconfig index 294de4549922..119ec0a21de2 100644 --- a/drivers/gpu/drm/mediatek/Kconfig +++ b/drivers/gpu/drm/mediatek/Kconfig | |||
@@ -11,6 +11,7 @@ config DRM_MEDIATEK | |||
11 | select DRM_PANEL | 11 | select DRM_PANEL |
12 | select MEMORY | 12 | select MEMORY |
13 | select MTK_SMI | 13 | select MTK_SMI |
14 | select VIDEOMODE_HELPERS | ||
14 | help | 15 | help |
15 | Choose this option if you have a Mediatek SoCs. | 16 | Choose this option if you have a Mediatek SoCs. |
16 | The module will be called mediatek-drm | 17 | The module will be called mediatek-drm |
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index e80a603e5fb0..6c0ea39d5739 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c | |||
@@ -22,6 +22,7 @@ | |||
22 | #include <linux/interrupt.h> | 22 | #include <linux/interrupt.h> |
23 | #include <linux/types.h> | 23 | #include <linux/types.h> |
24 | #include <linux/clk.h> | 24 | #include <linux/clk.h> |
25 | #include <video/videomode.h> | ||
25 | 26 | ||
26 | #include "mtk_dpi_regs.h" | 27 | #include "mtk_dpi_regs.h" |
27 | #include "mtk_drm_ddp_comp.h" | 28 | #include "mtk_drm_ddp_comp.h" |
@@ -429,34 +430,35 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, | |||
429 | struct mtk_dpi_sync_param vsync_leven = { 0 }; | 430 | struct mtk_dpi_sync_param vsync_leven = { 0 }; |
430 | struct mtk_dpi_sync_param vsync_rodd = { 0 }; | 431 | struct mtk_dpi_sync_param vsync_rodd = { 0 }; |
431 | struct mtk_dpi_sync_param vsync_reven = { 0 }; | 432 | struct mtk_dpi_sync_param vsync_reven = { 0 }; |
432 | unsigned long pix_rate; | 433 | struct videomode vm = { 0 }; |
433 | unsigned long pll_rate; | 434 | unsigned long pll_rate; |
434 | unsigned int factor; | 435 | unsigned int factor; |
435 | 436 | ||
436 | /* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */ | 437 | /* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */ |
437 | pix_rate = 1000UL * mode->clock; | 438 | |
438 | if (mode->clock <= 27000) | 439 | if (mode->clock <= 27000) |
439 | factor = 16 * 3; | 440 | factor = 3 << 4; |
440 | else if (mode->clock <= 84000) | 441 | else if (mode->clock <= 84000) |
441 | factor = 8 * 3; | 442 | factor = 3 << 3; |
442 | else if (mode->clock <= 167000) | 443 | else if (mode->clock <= 167000) |
443 | factor = 4 * 3; | 444 | factor = 3 << 2; |
444 | else | 445 | else |
445 | factor = 2 * 3; | 446 | factor = 3 << 1; |
446 | pll_rate = pix_rate * factor; | 447 | drm_display_mode_to_videomode(mode, &vm); |
448 | pll_rate = vm.pixelclock * factor; | ||
447 | 449 | ||
448 | dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n", | 450 | dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n", |
449 | pll_rate, pix_rate); | 451 | pll_rate, vm.pixelclock); |
450 | 452 | ||
451 | clk_set_rate(dpi->tvd_clk, pll_rate); | 453 | clk_set_rate(dpi->tvd_clk, pll_rate); |
452 | pll_rate = clk_get_rate(dpi->tvd_clk); | 454 | pll_rate = clk_get_rate(dpi->tvd_clk); |
453 | 455 | ||
454 | pix_rate = pll_rate / factor; | 456 | vm.pixelclock = pll_rate / factor; |
455 | clk_set_rate(dpi->pixel_clk, pix_rate); | 457 | clk_set_rate(dpi->pixel_clk, vm.pixelclock); |
456 | pix_rate = clk_get_rate(dpi->pixel_clk); | 458 | vm.pixelclock = clk_get_rate(dpi->pixel_clk); |
457 | 459 | ||
458 | dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n", | 460 | dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n", |
459 | pll_rate, pix_rate); | 461 | pll_rate, vm.pixelclock); |
460 | 462 | ||
461 | limit.c_bottom = 0x0010; | 463 | limit.c_bottom = 0x0010; |
462 | limit.c_top = 0x0FE0; | 464 | limit.c_top = 0x0FE0; |
@@ -465,33 +467,31 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, | |||
465 | 467 | ||
466 | dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING; | 468 | dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING; |
467 | dpi_pol.de_pol = MTK_DPI_POLARITY_RISING; | 469 | dpi_pol.de_pol = MTK_DPI_POLARITY_RISING; |
468 | dpi_pol.hsync_pol = mode->flags & DRM_MODE_FLAG_PHSYNC ? | 470 | dpi_pol.hsync_pol = vm.flags & DISPLAY_FLAGS_HSYNC_HIGH ? |
469 | MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; | 471 | MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; |
470 | dpi_pol.vsync_pol = mode->flags & DRM_MODE_FLAG_PVSYNC ? | 472 | dpi_pol.vsync_pol = vm.flags & DISPLAY_FLAGS_VSYNC_HIGH ? |
471 | MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; | 473 | MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; |
472 | 474 | hsync.sync_width = vm.hsync_len; | |
473 | hsync.sync_width = mode->hsync_end - mode->hsync_start; | 475 | hsync.back_porch = vm.hback_porch; |
474 | hsync.back_porch = mode->htotal - mode->hsync_end; | 476 | hsync.front_porch = vm.hfront_porch; |
475 | hsync.front_porch = mode->hsync_start - mode->hdisplay; | ||
476 | hsync.shift_half_line = false; | 477 | hsync.shift_half_line = false; |
477 | 478 | vsync_lodd.sync_width = vm.vsync_len; | |
478 | vsync_lodd.sync_width = mode->vsync_end - mode->vsync_start; | 479 | vsync_lodd.back_porch = vm.vback_porch; |
479 | vsync_lodd.back_porch = mode->vtotal - mode->vsync_end; | 480 | vsync_lodd.front_porch = vm.vfront_porch; |
480 | vsync_lodd.front_porch = mode->vsync_start - mode->vdisplay; | ||
481 | vsync_lodd.shift_half_line = false; | 481 | vsync_lodd.shift_half_line = false; |
482 | 482 | ||
483 | if (mode->flags & DRM_MODE_FLAG_INTERLACE && | 483 | if (vm.flags & DISPLAY_FLAGS_INTERLACED && |
484 | mode->flags & DRM_MODE_FLAG_3D_MASK) { | 484 | mode->flags & DRM_MODE_FLAG_3D_MASK) { |
485 | vsync_leven = vsync_lodd; | 485 | vsync_leven = vsync_lodd; |
486 | vsync_rodd = vsync_lodd; | 486 | vsync_rodd = vsync_lodd; |
487 | vsync_reven = vsync_lodd; | 487 | vsync_reven = vsync_lodd; |
488 | vsync_leven.shift_half_line = true; | 488 | vsync_leven.shift_half_line = true; |
489 | vsync_reven.shift_half_line = true; | 489 | vsync_reven.shift_half_line = true; |
490 | } else if (mode->flags & DRM_MODE_FLAG_INTERLACE && | 490 | } else if (vm.flags & DISPLAY_FLAGS_INTERLACED && |
491 | !(mode->flags & DRM_MODE_FLAG_3D_MASK)) { | 491 | !(mode->flags & DRM_MODE_FLAG_3D_MASK)) { |
492 | vsync_leven = vsync_lodd; | 492 | vsync_leven = vsync_lodd; |
493 | vsync_leven.shift_half_line = true; | 493 | vsync_leven.shift_half_line = true; |
494 | } else if (!(mode->flags & DRM_MODE_FLAG_INTERLACE) && | 494 | } else if (!(vm.flags & DISPLAY_FLAGS_INTERLACED) && |
495 | mode->flags & DRM_MODE_FLAG_3D_MASK) { | 495 | mode->flags & DRM_MODE_FLAG_3D_MASK) { |
496 | vsync_rodd = vsync_lodd; | 496 | vsync_rodd = vsync_lodd; |
497 | } | 497 | } |
@@ -505,12 +505,12 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, | |||
505 | mtk_dpi_config_vsync_reven(dpi, &vsync_reven); | 505 | mtk_dpi_config_vsync_reven(dpi, &vsync_reven); |
506 | 506 | ||
507 | mtk_dpi_config_3d(dpi, !!(mode->flags & DRM_MODE_FLAG_3D_MASK)); | 507 | mtk_dpi_config_3d(dpi, !!(mode->flags & DRM_MODE_FLAG_3D_MASK)); |
508 | mtk_dpi_config_interface(dpi, !!(mode->flags & | 508 | mtk_dpi_config_interface(dpi, !!(vm.flags & |
509 | DRM_MODE_FLAG_INTERLACE)); | 509 | DISPLAY_FLAGS_INTERLACED)); |
510 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | 510 | if (vm.flags & DISPLAY_FLAGS_INTERLACED) |
511 | mtk_dpi_config_fb_size(dpi, mode->hdisplay, mode->vdisplay / 2); | 511 | mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive >> 1); |
512 | else | 512 | else |
513 | mtk_dpi_config_fb_size(dpi, mode->hdisplay, mode->vdisplay); | 513 | mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive); |
514 | 514 | ||
515 | mtk_dpi_config_channel_limit(dpi, &limit); | 515 | mtk_dpi_config_channel_limit(dpi, &limit); |
516 | mtk_dpi_config_bit_num(dpi, dpi->bit_num); | 516 | mtk_dpi_config_bit_num(dpi, dpi->bit_num); |
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_gem.c b/drivers/gpu/drm/mediatek/mtk_drm_gem.c index f595ac816b55..259b7b0de1d2 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_gem.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_gem.c | |||
@@ -220,7 +220,7 @@ struct drm_gem_object *mtk_gem_prime_import_sg_table(struct drm_device *dev, | |||
220 | mtk_gem = mtk_drm_gem_init(dev, attach->dmabuf->size); | 220 | mtk_gem = mtk_drm_gem_init(dev, attach->dmabuf->size); |
221 | 221 | ||
222 | if (IS_ERR(mtk_gem)) | 222 | if (IS_ERR(mtk_gem)) |
223 | return ERR_PTR(PTR_ERR(mtk_gem)); | 223 | return ERR_CAST(mtk_gem); |
224 | 224 | ||
225 | expected = sg_dma_address(sg->sgl); | 225 | expected = sg_dma_address(sg->sgl); |
226 | for_each_sg(sg->sgl, s, sg->nents, i) { | 226 | for_each_sg(sg->sgl, s, sg->nents, i) { |
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index 7e5e24c2152a..aa0943ec32b0 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c | |||
@@ -551,13 +551,12 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) | |||
551 | } | 551 | } |
552 | 552 | ||
553 | /** | 553 | /** |
554 | * vm.pixelclock is in kHz, pixel_clock unit is Hz, so multiply by 1000 | ||
555 | * htotal_time = htotal * byte_per_pixel / num_lanes | 554 | * htotal_time = htotal * byte_per_pixel / num_lanes |
556 | * overhead_time = lpx + hs_prepare + hs_zero + hs_trail + hs_exit | 555 | * overhead_time = lpx + hs_prepare + hs_zero + hs_trail + hs_exit |
557 | * mipi_ratio = (htotal_time + overhead_time) / htotal_time | 556 | * mipi_ratio = (htotal_time + overhead_time) / htotal_time |
558 | * data_rate = pixel_clock * bit_per_pixel * mipi_ratio / num_lanes; | 557 | * data_rate = pixel_clock * bit_per_pixel * mipi_ratio / num_lanes; |
559 | */ | 558 | */ |
560 | pixel_clock = dsi->vm.pixelclock * 1000; | 559 | pixel_clock = dsi->vm.pixelclock; |
561 | htotal = dsi->vm.hactive + dsi->vm.hback_porch + dsi->vm.hfront_porch + | 560 | htotal = dsi->vm.hactive + dsi->vm.hback_porch + dsi->vm.hfront_porch + |
562 | dsi->vm.hsync_len; | 561 | dsi->vm.hsync_len; |
563 | htotal_bits = htotal * bit_per_pixel; | 562 | htotal_bits = htotal * bit_per_pixel; |
@@ -725,16 +724,7 @@ static void mtk_dsi_encoder_mode_set(struct drm_encoder *encoder, | |||
725 | { | 724 | { |
726 | struct mtk_dsi *dsi = encoder_to_dsi(encoder); | 725 | struct mtk_dsi *dsi = encoder_to_dsi(encoder); |
727 | 726 | ||
728 | dsi->vm.pixelclock = adjusted->clock; | 727 | drm_display_mode_to_videomode(adjusted, &dsi->vm); |
729 | dsi->vm.hactive = adjusted->hdisplay; | ||
730 | dsi->vm.hback_porch = adjusted->htotal - adjusted->hsync_end; | ||
731 | dsi->vm.hfront_porch = adjusted->hsync_start - adjusted->hdisplay; | ||
732 | dsi->vm.hsync_len = adjusted->hsync_end - adjusted->hsync_start; | ||
733 | |||
734 | dsi->vm.vactive = adjusted->vdisplay; | ||
735 | dsi->vm.vback_porch = adjusted->vtotal - adjusted->vsync_end; | ||
736 | dsi->vm.vfront_porch = adjusted->vsync_start - adjusted->vdisplay; | ||
737 | dsi->vm.vsync_len = adjusted->vsync_end - adjusted->vsync_start; | ||
738 | } | 728 | } |
739 | 729 | ||
740 | static void mtk_dsi_encoder_disable(struct drm_encoder *encoder) | 730 | static void mtk_dsi_encoder_disable(struct drm_encoder *encoder) |