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authorRex Zhu <Rex.Zhu@amd.com>2018-08-22 06:54:45 -0400
committerAlex Deucher <alexander.deucher@amd.com>2018-08-27 16:12:03 -0400
commita9a8a788e5e946a9835a1365256fc4ce9e96ba2c (patch)
tree6be7308b28fb4629d724205500dcb922ed15851f /drivers/gpu/drm
parent36859cd5354b9cb418c28930936a8a6fce18a1d7 (diff)
drm/amdgpu: Change kiq ring initialize sequence on gfx9
1. initialize kiq before initialize gfx ring. 2. set kiq ring ready immediately when kiq initialize successfully. 3. split function gfx_v9_0_kiq_resume into two functions. gfx_v9_0_kiq_resume is for kiq initialize. gfx_v9_0_kcq_resume is for kcq initialize. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c38
1 files changed, 24 insertions, 14 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 21e66f86de92..3594704a6f9b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2684,7 +2684,6 @@ static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev)
2684 queue_mask |= (1ull << i); 2684 queue_mask |= (1ull << i);
2685 } 2685 }
2686 2686
2687 kiq_ring->ready = true;
2688 r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 8); 2687 r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 8);
2689 if (r) { 2688 if (r) {
2690 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 2689 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
@@ -3091,26 +3090,33 @@ static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
3091 3090
3092static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev) 3091static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)
3093{ 3092{
3094 struct amdgpu_ring *ring = NULL; 3093 struct amdgpu_ring *ring;
3095 int r = 0, i; 3094 int r;
3096
3097 gfx_v9_0_cp_compute_enable(adev, true);
3098 3095
3099 ring = &adev->gfx.kiq.ring; 3096 ring = &adev->gfx.kiq.ring;
3100 3097
3101 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3098 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3102 if (unlikely(r != 0)) 3099 if (unlikely(r != 0))
3103 goto done; 3100 return r;
3104 3101
3105 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3102 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3106 if (!r) { 3103 if (unlikely(r != 0))
3107 r = gfx_v9_0_kiq_init_queue(ring); 3104 return r;
3108 amdgpu_bo_kunmap(ring->mqd_obj); 3105
3109 ring->mqd_ptr = NULL; 3106 gfx_v9_0_kiq_init_queue(ring);
3110 } 3107 amdgpu_bo_kunmap(ring->mqd_obj);
3108 ring->mqd_ptr = NULL;
3111 amdgpu_bo_unreserve(ring->mqd_obj); 3109 amdgpu_bo_unreserve(ring->mqd_obj);
3112 if (r) 3110 ring->ready = true;
3113 goto done; 3111 return 0;
3112}
3113
3114static int gfx_v9_0_kcq_resume(struct amdgpu_device *adev)
3115{
3116 struct amdgpu_ring *ring = NULL;
3117 int r = 0, i;
3118
3119 gfx_v9_0_cp_compute_enable(adev, true);
3114 3120
3115 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3121 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3116 ring = &adev->gfx.compute_ring[i]; 3122 ring = &adev->gfx.compute_ring[i];
@@ -3153,11 +3159,15 @@ static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
3153 return r; 3159 return r;
3154 } 3160 }
3155 3161
3162 r = gfx_v9_0_kiq_resume(adev);
3163 if (r)
3164 return r;
3165
3156 r = gfx_v9_0_cp_gfx_resume(adev); 3166 r = gfx_v9_0_cp_gfx_resume(adev);
3157 if (r) 3167 if (r)
3158 return r; 3168 return r;
3159 3169
3160 r = gfx_v9_0_kiq_resume(adev); 3170 r = gfx_v9_0_kcq_resume(adev);
3161 if (r) 3171 if (r)
3162 return r; 3172 return r;
3163 3173