diff options
author | Evan Quan <evan.quan@amd.com> | 2019-01-17 04:52:41 -0500 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2019-01-25 16:15:35 -0500 |
commit | 921935dc64040b56c785a02b2f39fd5d28932c78 (patch) | |
tree | 85fac0586a6ca758d901785d33c2058906922ea8 /drivers/gpu/drm | |
parent | a0e4fa2f2889c2d02448a9c20d3f24f2fd13e01c (diff) |
drm/amd/powerplay: enforce display related settings only on needed
No display related settings are needed on dpm level change.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 10 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c | 11 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.h | 2 |
3 files changed, 11 insertions, 12 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c index 310b102a9292..6cd6497c6fc2 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | |||
@@ -273,7 +273,7 @@ int hwmgr_hw_fini(struct pp_hwmgr *hwmgr) | |||
273 | 273 | ||
274 | phm_stop_thermal_controller(hwmgr); | 274 | phm_stop_thermal_controller(hwmgr); |
275 | psm_set_boot_states(hwmgr); | 275 | psm_set_boot_states(hwmgr); |
276 | psm_adjust_power_state_dynamic(hwmgr, false, NULL); | 276 | psm_adjust_power_state_dynamic(hwmgr, true, NULL); |
277 | phm_disable_dynamic_state_management(hwmgr); | 277 | phm_disable_dynamic_state_management(hwmgr); |
278 | phm_disable_clock_power_gatings(hwmgr); | 278 | phm_disable_clock_power_gatings(hwmgr); |
279 | 279 | ||
@@ -295,7 +295,7 @@ int hwmgr_suspend(struct pp_hwmgr *hwmgr) | |||
295 | ret = psm_set_boot_states(hwmgr); | 295 | ret = psm_set_boot_states(hwmgr); |
296 | if (ret) | 296 | if (ret) |
297 | return ret; | 297 | return ret; |
298 | ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL); | 298 | ret = psm_adjust_power_state_dynamic(hwmgr, true, NULL); |
299 | if (ret) | 299 | if (ret) |
300 | return ret; | 300 | return ret; |
301 | ret = phm_power_down_asic(hwmgr); | 301 | ret = phm_power_down_asic(hwmgr); |
@@ -325,7 +325,7 @@ int hwmgr_resume(struct pp_hwmgr *hwmgr) | |||
325 | if (ret) | 325 | if (ret) |
326 | return ret; | 326 | return ret; |
327 | 327 | ||
328 | ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL); | 328 | ret = psm_adjust_power_state_dynamic(hwmgr, true, NULL); |
329 | 329 | ||
330 | return ret; | 330 | return ret; |
331 | } | 331 | } |
@@ -379,12 +379,12 @@ int hwmgr_handle_task(struct pp_hwmgr *hwmgr, enum amd_pp_task task_id, | |||
379 | ret = psm_set_user_performance_state(hwmgr, requested_ui_label, &requested_ps); | 379 | ret = psm_set_user_performance_state(hwmgr, requested_ui_label, &requested_ps); |
380 | if (ret) | 380 | if (ret) |
381 | return ret; | 381 | return ret; |
382 | ret = psm_adjust_power_state_dynamic(hwmgr, false, requested_ps); | 382 | ret = psm_adjust_power_state_dynamic(hwmgr, true, requested_ps); |
383 | break; | 383 | break; |
384 | } | 384 | } |
385 | case AMD_PP_TASK_COMPLETE_INIT: | 385 | case AMD_PP_TASK_COMPLETE_INIT: |
386 | case AMD_PP_TASK_READJUST_POWER_STATE: | 386 | case AMD_PP_TASK_READJUST_POWER_STATE: |
387 | ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL); | 387 | ret = psm_adjust_power_state_dynamic(hwmgr, true, NULL); |
388 | break; | 388 | break; |
389 | default: | 389 | default: |
390 | break; | 390 | break; |
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c index 68f3dcaa8070..ce177d7f04cb 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c | |||
@@ -256,16 +256,14 @@ static void power_state_management(struct pp_hwmgr *hwmgr, | |||
256 | } | 256 | } |
257 | } | 257 | } |
258 | 258 | ||
259 | int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr, bool skip, | 259 | int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr, bool skip_display_settings, |
260 | struct pp_power_state *new_ps) | 260 | struct pp_power_state *new_ps) |
261 | { | 261 | { |
262 | uint32_t index; | 262 | uint32_t index; |
263 | long workload; | 263 | long workload; |
264 | 264 | ||
265 | if (skip) | 265 | if (!skip_display_settings) |
266 | return 0; | 266 | phm_display_configuration_changed(hwmgr); |
267 | |||
268 | phm_display_configuration_changed(hwmgr); | ||
269 | 267 | ||
270 | if (hwmgr->ps) | 268 | if (hwmgr->ps) |
271 | power_state_management(hwmgr, new_ps); | 269 | power_state_management(hwmgr, new_ps); |
@@ -276,7 +274,8 @@ int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr, bool skip, | |||
276 | */ | 274 | */ |
277 | phm_apply_clock_adjust_rules(hwmgr); | 275 | phm_apply_clock_adjust_rules(hwmgr); |
278 | 276 | ||
279 | phm_notify_smc_display_config_after_ps_adjustment(hwmgr); | 277 | if (!skip_display_settings) |
278 | phm_notify_smc_display_config_after_ps_adjustment(hwmgr); | ||
280 | 279 | ||
281 | if ((hwmgr->request_dpm_level != hwmgr->dpm_level) && | 280 | if ((hwmgr->request_dpm_level != hwmgr->dpm_level) && |
282 | !phm_force_dpm_levels(hwmgr, hwmgr->request_dpm_level)) | 281 | !phm_force_dpm_levels(hwmgr, hwmgr->request_dpm_level)) |
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.h b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.h index fa1b6825036a..b62d55f1f289 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.h | |||
@@ -34,7 +34,7 @@ int psm_set_user_performance_state(struct pp_hwmgr *hwmgr, | |||
34 | enum PP_StateUILabel label_id, | 34 | enum PP_StateUILabel label_id, |
35 | struct pp_power_state **state); | 35 | struct pp_power_state **state); |
36 | int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr, | 36 | int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr, |
37 | bool skip, | 37 | bool skip_display_settings, |
38 | struct pp_power_state *new_ps); | 38 | struct pp_power_state *new_ps); |
39 | 39 | ||
40 | #endif | 40 | #endif |