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authorDave Airlie <airlied@redhat.com>2018-09-19 20:01:46 -0400
committerDave Airlie <airlied@redhat.com>2018-09-19 20:01:53 -0400
commit8ca4fff974ad5288d38298f15bf218f2eac2d5e7 (patch)
tree6807271cccdc3813e7a2045e87d1f6dddba6f906 /drivers/gpu/drm
parentd5b3a31b1ceaa9d6f44646848ebde590f2a03d84 (diff)
parenta530bf948ab77b0f5cc57c55dd525eb813768782 (diff)
Merge tag 'drm-intel-fixes-2018-09-19' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes
Only fixes coming from gvt containing "Two more BXT fixes from Colin, one srcu locking fix and one fix for GGTT clear when destroy vGPU." Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180919151915.GA6309@intel.com
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/i915/gvt/handlers.c1
-rw-r--r--drivers/gpu/drm/i915/gvt/kvmgt.c7
-rw-r--r--drivers/gpu/drm/i915/gvt/mmio.c28
-rw-r--r--drivers/gpu/drm/i915/gvt/vgpu.c1
4 files changed, 36 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 72afa518edd9..94c1089ecf59 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -3210,6 +3210,7 @@ static int init_bxt_mmio_info(struct intel_gvt *gvt)
3210 MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT); 3210 MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT);
3211 3211
3212 MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT); 3212 MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT);
3213 MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT);
3213 3214
3214 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT); 3215 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT);
3215 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT); 3216 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index c7afee37b2b8..9ad89e38f6c0 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -1833,6 +1833,8 @@ static bool kvmgt_is_valid_gfn(unsigned long handle, unsigned long gfn)
1833{ 1833{
1834 struct kvmgt_guest_info *info; 1834 struct kvmgt_guest_info *info;
1835 struct kvm *kvm; 1835 struct kvm *kvm;
1836 int idx;
1837 bool ret;
1836 1838
1837 if (!handle_valid(handle)) 1839 if (!handle_valid(handle))
1838 return false; 1840 return false;
@@ -1840,8 +1842,11 @@ static bool kvmgt_is_valid_gfn(unsigned long handle, unsigned long gfn)
1840 info = (struct kvmgt_guest_info *)handle; 1842 info = (struct kvmgt_guest_info *)handle;
1841 kvm = info->kvm; 1843 kvm = info->kvm;
1842 1844
1843 return kvm_is_visible_gfn(kvm, gfn); 1845 idx = srcu_read_lock(&kvm->srcu);
1846 ret = kvm_is_visible_gfn(kvm, gfn);
1847 srcu_read_unlock(&kvm->srcu, idx);
1844 1848
1849 return ret;
1845} 1850}
1846 1851
1847struct intel_gvt_mpt kvmgt_mpt = { 1852struct intel_gvt_mpt kvmgt_mpt = {
diff --git a/drivers/gpu/drm/i915/gvt/mmio.c b/drivers/gpu/drm/i915/gvt/mmio.c
index 994366035364..9bb9a85c992c 100644
--- a/drivers/gpu/drm/i915/gvt/mmio.c
+++ b/drivers/gpu/drm/i915/gvt/mmio.c
@@ -244,6 +244,34 @@ void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr)
244 244
245 /* set the bit 0:2(Core C-State ) to C0 */ 245 /* set the bit 0:2(Core C-State ) to C0 */
246 vgpu_vreg_t(vgpu, GEN6_GT_CORE_STATUS) = 0; 246 vgpu_vreg_t(vgpu, GEN6_GT_CORE_STATUS) = 0;
247
248 if (IS_BROXTON(vgpu->gvt->dev_priv)) {
249 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &=
250 ~(BIT(0) | BIT(1));
251 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
252 ~PHY_POWER_GOOD;
253 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=
254 ~PHY_POWER_GOOD;
255 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &=
256 ~BIT(30);
257 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &=
258 ~BIT(30);
259 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &=
260 ~BXT_PHY_LANE_ENABLED;
261 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |=
262 BXT_PHY_CMNLANE_POWERDOWN_ACK |
263 BXT_PHY_LANE_POWERDOWN_ACK;
264 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &=
265 ~BXT_PHY_LANE_ENABLED;
266 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |=
267 BXT_PHY_CMNLANE_POWERDOWN_ACK |
268 BXT_PHY_LANE_POWERDOWN_ACK;
269 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &=
270 ~BXT_PHY_LANE_ENABLED;
271 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |=
272 BXT_PHY_CMNLANE_POWERDOWN_ACK |
273 BXT_PHY_LANE_POWERDOWN_ACK;
274 }
247 } else { 275 } else {
248#define GVT_GEN8_MMIO_RESET_OFFSET (0x44200) 276#define GVT_GEN8_MMIO_RESET_OFFSET (0x44200)
249 /* only reset the engine related, so starting with 0x44200 277 /* only reset the engine related, so starting with 0x44200
diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index a4e8e3cf74fd..c628be05fbfe 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -281,6 +281,7 @@ void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu)
281 intel_vgpu_clean_submission(vgpu); 281 intel_vgpu_clean_submission(vgpu);
282 intel_vgpu_clean_display(vgpu); 282 intel_vgpu_clean_display(vgpu);
283 intel_vgpu_clean_opregion(vgpu); 283 intel_vgpu_clean_opregion(vgpu);
284 intel_vgpu_reset_ggtt(vgpu, true);
284 intel_vgpu_clean_gtt(vgpu); 285 intel_vgpu_clean_gtt(vgpu);
285 intel_gvt_hypervisor_detach_vgpu(vgpu); 286 intel_gvt_hypervisor_detach_vgpu(vgpu);
286 intel_vgpu_free_resource(vgpu); 287 intel_vgpu_free_resource(vgpu);