diff options
author | Evan Quan <evan.quan@amd.com> | 2017-08-21 23:19:10 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2017-08-24 11:48:43 -0400 |
commit | 547f1091b972cec23feec21611eb33105c86240c (patch) | |
tree | 27dcaf2b46fc08d9c190252c28707bf53a6cf70e /drivers/gpu/drm | |
parent | 6af0883ed9770cf9b0a4f224c91481484cd1b025 (diff) |
drm/amd/powerplay: ACG frequency added in PPTable
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 11 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h | 6 |
2 files changed, 12 insertions, 5 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c index 9d71a259d97d..f8f02e70b8bc 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | |||
@@ -1558,7 +1558,8 @@ static int vega10_populate_smc_link_levels(struct pp_hwmgr *hwmgr) | |||
1558 | */ | 1558 | */ |
1559 | 1559 | ||
1560 | static int vega10_populate_single_gfx_level(struct pp_hwmgr *hwmgr, | 1560 | static int vega10_populate_single_gfx_level(struct pp_hwmgr *hwmgr, |
1561 | uint32_t gfx_clock, PllSetting_t *current_gfxclk_level) | 1561 | uint32_t gfx_clock, PllSetting_t *current_gfxclk_level, |
1562 | uint32_t *acg_freq) | ||
1562 | { | 1563 | { |
1563 | struct phm_ppt_v2_information *table_info = | 1564 | struct phm_ppt_v2_information *table_info = |
1564 | (struct phm_ppt_v2_information *)(hwmgr->pptable); | 1565 | (struct phm_ppt_v2_information *)(hwmgr->pptable); |
@@ -1609,6 +1610,8 @@ static int vega10_populate_single_gfx_level(struct pp_hwmgr *hwmgr, | |||
1609 | cpu_to_le16(dividers.usPll_ss_slew_frac); | 1610 | cpu_to_le16(dividers.usPll_ss_slew_frac); |
1610 | current_gfxclk_level->Did = (uint8_t)(dividers.ulDid); | 1611 | current_gfxclk_level->Did = (uint8_t)(dividers.ulDid); |
1611 | 1612 | ||
1613 | *acg_freq = gfx_clock / 100; /* 100 Khz to Mhz conversion */ | ||
1614 | |||
1612 | return 0; | 1615 | return 0; |
1613 | } | 1616 | } |
1614 | 1617 | ||
@@ -1689,7 +1692,8 @@ static int vega10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) | |||
1689 | for (i = 0; i < dpm_table->count; i++) { | 1692 | for (i = 0; i < dpm_table->count; i++) { |
1690 | result = vega10_populate_single_gfx_level(hwmgr, | 1693 | result = vega10_populate_single_gfx_level(hwmgr, |
1691 | dpm_table->dpm_levels[i].value, | 1694 | dpm_table->dpm_levels[i].value, |
1692 | &(pp_table->GfxclkLevel[i])); | 1695 | &(pp_table->GfxclkLevel[i]), |
1696 | &(pp_table->AcgFreqTable[i])); | ||
1693 | if (result) | 1697 | if (result) |
1694 | return result; | 1698 | return result; |
1695 | } | 1699 | } |
@@ -1698,7 +1702,8 @@ static int vega10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) | |||
1698 | while (i < NUM_GFXCLK_DPM_LEVELS) { | 1702 | while (i < NUM_GFXCLK_DPM_LEVELS) { |
1699 | result = vega10_populate_single_gfx_level(hwmgr, | 1703 | result = vega10_populate_single_gfx_level(hwmgr, |
1700 | dpm_table->dpm_levels[j].value, | 1704 | dpm_table->dpm_levels[j].value, |
1701 | &(pp_table->GfxclkLevel[i])); | 1705 | &(pp_table->GfxclkLevel[i]), |
1706 | &(pp_table->AcgFreqTable[i])); | ||
1702 | if (result) | 1707 | if (result) |
1703 | return result; | 1708 | return result; |
1704 | i++; | 1709 | i++; |
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h b/drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h index f6d6c61f796a..2818c98ff5ca 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h +++ b/drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h | |||
@@ -315,10 +315,12 @@ typedef struct { | |||
315 | uint8_t AcgEnable[NUM_GFXCLK_DPM_LEVELS]; | 315 | uint8_t AcgEnable[NUM_GFXCLK_DPM_LEVELS]; |
316 | GbVdroopTable_t AcgBtcGbVdroopTable; | 316 | GbVdroopTable_t AcgBtcGbVdroopTable; |
317 | QuadraticInt_t AcgAvfsGb; | 317 | QuadraticInt_t AcgAvfsGb; |
318 | uint32_t Reserved[4]; | 318 | |
319 | /* ACG Frequency Table, in Mhz */ | ||
320 | uint32_t AcgFreqTable[NUM_GFXCLK_DPM_LEVELS]; | ||
319 | 321 | ||
320 | /* Padding - ignore */ | 322 | /* Padding - ignore */ |
321 | uint32_t MmHubPadding[7]; /* SMU internal use */ | 323 | uint32_t MmHubPadding[3]; /* SMU internal use */ |
322 | 324 | ||
323 | } PPTable_t; | 325 | } PPTable_t; |
324 | 326 | ||