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authorAlex Deucher <alexander.deucher@amd.com>2016-09-28 14:23:49 -0400
committerAlex Deucher <alexander.deucher@amd.com>2016-10-25 14:38:12 -0400
commit46c9cc11a5e362bfc850426d892086bf7c4e2d26 (patch)
tree755380435fd35b45a6115ad1e7a6873ad97db912 /drivers/gpu/drm
parent079ea1901b7186165d958ee54338c68883096d92 (diff)
drm/amdgpu/dce6: don't enable HPD Rx interrupts
Not used currently. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v6_0.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index 72ab20a757c8..502e97963d6d 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -2519,12 +2519,12 @@ static int dce_v6_0_set_hpd_interrupt_state(struct amdgpu_device *adev,
2519 switch (state) { 2519 switch (state) {
2520 case AMDGPU_IRQ_STATE_DISABLE: 2520 case AMDGPU_IRQ_STATE_DISABLE:
2521 dc_hpd_int_cntl = RREG32(DC_HPD1_INT_CONTROL + hpd_offsets[type]); 2521 dc_hpd_int_cntl = RREG32(DC_HPD1_INT_CONTROL + hpd_offsets[type]);
2522 dc_hpd_int_cntl &= ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); 2522 dc_hpd_int_cntl &= ~DC_HPDx_INT_EN;
2523 WREG32(DC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); 2523 WREG32(DC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
2524 break; 2524 break;
2525 case AMDGPU_IRQ_STATE_ENABLE: 2525 case AMDGPU_IRQ_STATE_ENABLE:
2526 dc_hpd_int_cntl = RREG32(DC_HPD1_INT_CONTROL + hpd_offsets[type]); 2526 dc_hpd_int_cntl = RREG32(DC_HPD1_INT_CONTROL + hpd_offsets[type]);
2527 dc_hpd_int_cntl |= (DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); 2527 dc_hpd_int_cntl |= DC_HPDx_INT_EN;
2528 WREG32(DC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); 2528 WREG32(DC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
2529 break; 2529 break;
2530 default: 2530 default: