drm/amdgpu: read hw register to check pg status.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

12 files changed, 22 insertions, 14 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 96ad79627dbb..e9af03113fc3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1037,7 +1037,6 @@ struct amdgpu_uvd {
         bool                    use_ctx_buf;
         struct amd_sched_entity entity;
         uint32_t                srbm_soft_reset;
-        bool                    is_powergated;
 };
 
 /*
@@ -1066,7 +1065,6 @@ struct amdgpu_vce {
         struct amd_sched_entity entity;
         uint32_t                srbm_soft_reset;
         unsigned                num_rings;
-        bool                    is_powergated;
 };
 
 /*
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
index f15df99f0a06..97af4827f652 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
@@ -723,7 +723,8 @@ static int uvd_v4_2_set_powergating_state(void *handle,
         if (state == AMD_PG_STATE_GATE) {
                 uvd_v4_2_stop(adev);
                 if (adev->pg_flags & AMD_PG_SUPPORT_UVD && amdgpu_dpm == 0) {
-                        if (!(RREG32_SMC(ixCURRENT_PG_STATUS) & 0x4)) {
+                        if (!(RREG32_SMC(ixCURRENT_PG_STATUS) &
+                                CURRENT_PG_STATUS__UVD_PG_STATUS_MASK)) {
                                 WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK   |
                                                         UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK |
                                                         UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK));
@@ -733,7 +734,8 @@ static int uvd_v4_2_set_powergating_state(void *handle,
                 return 0;
         } else {
                 if (adev->pg_flags & AMD_PG_SUPPORT_UVD && amdgpu_dpm == 0) {
-                        if (RREG32_SMC(ixCURRENT_PG_STATUS) & 0x4) {
+                        if (RREG32_SMC(ixCURRENT_PG_STATUS) &
+                                CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) {
                                 WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK   |
                                                 UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK |
                                                 UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK));
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
index 46e715193924..ad8c02e423d4 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
@@ -825,12 +825,10 @@ static int uvd_v5_0_set_powergating_state(void *handle,
 
         if (state == AMD_PG_STATE_GATE) {
                 uvd_v5_0_stop(adev);
-                adev->uvd.is_powergated = true;
         } else {
                 ret = uvd_v5_0_start(adev);
                 if (ret)
                         goto out;
-                adev->uvd.is_powergated = false;
         }
 
 out:
@@ -844,7 +842,8 @@ static void uvd_v5_0_get_clockgating_state(void *handle, u32 *flags)
 
         mutex_lock(&adev->pm.mutex);
 
-        if (adev->uvd.is_powergated) {
+        if (RREG32_SMC(ixCURRENT_PG_STATUS) &
+                                CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) {
                 DRM_INFO("Cannot get clockgating state when UVD is powergated.\n");
                 goto out;
         }
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index af83ab8c1250..18a6de4e1512 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -1051,12 +1051,10 @@ static int uvd_v6_0_set_powergating_state(void *handle,
 
         if (state == AMD_PG_STATE_GATE) {
                 uvd_v6_0_stop(adev);
-                adev->uvd.is_powergated = true;
         } else {
                 ret = uvd_v6_0_start(adev);
                 if (ret)
                         goto out;
-                adev->uvd.is_powergated = false;
         }
 
 out:
@@ -1070,7 +1068,8 @@ static void uvd_v6_0_get_clockgating_state(void *handle, u32 *flags)
 
         mutex_lock(&adev->pm.mutex);
 
-        if (adev->uvd.is_powergated) {
+        if (RREG32_SMC(ixCURRENT_PG_STATUS) &
+                                CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) {
                 DRM_INFO("Cannot get clockgating state when UVD is powergated.\n");
                 goto out;
         }
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index a78298529f07..93ec8815bb13 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -768,12 +768,10 @@ static int vce_v3_0_set_powergating_state(void *handle,
                 ret = vce_v3_0_stop(adev);
                 if (ret)
                         goto out;
-                adev->vce.is_powergated = true;
         } else {
                 ret = vce_v3_0_start(adev);
                 if (ret)
                         goto out;
-                adev->vce.is_powergated = false;
         }
 
 out:
@@ -787,7 +785,8 @@ static void vce_v3_0_get_clockgating_state(void *handle, u32 *flags)
 
         mutex_lock(&adev->pm.mutex);
 
-        if (adev->vce.is_powergated) {
+        if (RREG32_SMC(ixCURRENT_PG_STATUS) &
+                        CURRENT_PG_STATUS__VCE_PG_STATUS_MASK) {
                 DRM_INFO("Cannot get clockgating state when VCE is powergated.\n");
                 goto out;
         }
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h
index 25882a4dea5d..34c6ff52710e 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h
@@ -5452,5 +5452,7 @@
 #define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0
 #define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xffffffff
 #define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0
+#define CURRENT_PG_STATUS__VCE_PG_STATUS_MASK 0x00000002
+#define CURRENT_PG_STATUS__UVD_PG_STATUS_MASK 0x00000004
 
 #endif /* SMU_7_0_1_SH_MASK_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_d.h
index a9ef1562f43b..66597c64f525 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_d.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_d.h
@@ -1121,5 +1121,6 @@
 #define ixROM_SW_DATA_62                                                        0xc060011c
 #define ixROM_SW_DATA_63                                                        0xc0600120
 #define ixROM_SW_DATA_64                                                        0xc0600124
+#define ixCURRENT_PG_STATUS                                                     0xc020029c
 
 #endif /* SMU_7_1_1_D_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h
index 2c997f7b5d13..fb06f2e2f6e6 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h
@@ -4860,5 +4860,7 @@
 #define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0
 #define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xffffffff
 #define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0
+#define CURRENT_PG_STATUS__VCE_PG_STATUS_MASK 0x00000002
+#define CURRENT_PG_STATUS__UVD_PG_STATUS_MASK 0x00000004
 
 #endif /* SMU_7_1_1_SH_MASK_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h
index 22dd4c2b7290..4446d43d2a8f 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h
@@ -1271,5 +1271,6 @@
 #define ixROM_SW_DATA_62                                                        0xc060011c
 #define ixROM_SW_DATA_63                                                        0xc0600120
 #define ixROM_SW_DATA_64                                                        0xc0600124
+#define ixCURRENT_PG_STATUS                                                     0xc020029c
 
 #endif /* SMU_7_1_2_D_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h
index 518fd02e9d35..627906674fe8 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h
@@ -5830,5 +5830,7 @@
 #define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0
 #define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xffffffff
 #define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0
+#define CURRENT_PG_STATUS__VCE_PG_STATUS_MASK 0x00000002
+#define CURRENT_PG_STATUS__UVD_PG_STATUS_MASK 0x00000004
 
 #endif /* SMU_7_1_2_SH_MASK_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h
index eca2b851f25f..0333d880bc9e 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h
@@ -1244,5 +1244,5 @@
 #define ixGC_CAC_ACC_CU14                                                       0xc8
 #define ixGC_CAC_ACC_CU15                                                       0xc9
 #define ixGC_CAC_OVRD_CU                                                        0xe7
-
+#define ixCURRENT_PG_STATUS                                                     0xc020029c
 #endif /* SMU_7_1_3_D_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h
index 1ede9e274714..654c1093d362 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h
@@ -6076,5 +6076,8 @@
 #define GC_CAC_OVRD_CU__OVRRD_SELECT__SHIFT 0x0
 #define GC_CAC_OVRD_CU__OVRRD_VALUE_MASK 0xffff0000
 #define GC_CAC_OVRD_CU__OVRRD_VALUE__SHIFT 0x10
+#define CURRENT_PG_STATUS__VCE_PG_STATUS_MASK 0x00000002
+#define CURRENT_PG_STATUS__UVD_PG_STATUS_MASK 0x00000004
+
 
 #endif /* SMU_7_1_3_SH_MASK_H */