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authorDave Airlie <airlied@redhat.com>2017-02-09 19:13:30 -0500
committerDave Airlie <airlied@redhat.com>2017-02-09 19:13:30 -0500
commit13f62f54d174d3417c3caaafedf5e22a0a03e442 (patch)
treebc7bbc06c12f5125ae7f3e681ef3855d57651012 /drivers/gpu/drm
parentf320d3572344d34a6d8b516261416df0193602f6 (diff)
parentfad061270ac43ff9eed315f0eae7c40b694592de (diff)
Merge branch 'drm-next-4.11' of git://people.freedesktop.org/~agd5f/linux into drm-next
Some additional fixes for 4.11. Delayed a bit due to Chinese New Year. Highlights: - Powerplay fixes - VCE and UVD powergating fixes - Clean up amdgpu SI gfx code to match CI and VI - Misc bug fixes * 'drm-next-4.11' of git://people.freedesktop.org/~agd5f/linux: (30 commits) drm/amdgpu: report the number of bytes moved at buffer creation drm/amdgpu: fix a potential deadlock in amdgpu_bo_create_restricted() drm/amdgpu: add support for new smc firmware on polaris drm/amd/powerplay: refine code to avoid potential bug that the memory not cleared. drm/amdgpu: shut up #warning for compile testing drm/amdgpu/virt: fix double kfree on bo_va drm/radeon: remove some dead code drm/radeon: avoid kernel segfault in vce when gpu fails to resume drm/amd/powerplay: set fan speed to max in profile peak mode only. drm/amd/gfx6: update gb_addr_config drm/amdgpu: update HAINAN_GB_ADDR_CONFIG_GOLDEN drm/amdgpu: update VERDE_GB_ADDR_CONFIG_GOLDEN drm/amdgpu: refine si_read_register drm/amdgpu/gfx6: clean up spi configuration drm/amdgpu/gfx6: clean up cu configuration drm/amdgpu/gfx6: clean up rb configuration drm/amdgpu: refine vce3.0 code and related powerplay pg code. drm/amdgpu: move subfunctions to the front of vce_v2_0.c. drm/amdgpu: enable vce pg feature on Kv. drm/amdgpu: refine code for VCE2.0 and related dpm code. ...
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu.h1
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c33
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c3
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c54
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_object.c13
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c12
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c9
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c9
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c1
-rw-r--r--drivers/gpu/drm/amd/amdgpu/ci_dpm.c29
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cik.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c216
-rw-r--r--drivers/gpu/drm/amd/amdgpu/kv_dpm.c68
-rw-r--r--drivers/gpu/drm/amd/amdgpu/si.c90
-rw-r--r--drivers/gpu/drm/amd/amdgpu/si_enums.h4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c128
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c24
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c21
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vce_v2_0.c451
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vce_v3_0.c17
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_d.h1
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c74
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c23
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c22
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_bios.c4
-rw-r--r--drivers/gpu/drm/radeon/vce_v1_0.c2
27 files changed, 682 insertions, 633 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 94a64e3bc682..96ad79627dbb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1709,6 +1709,7 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
1709int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, 1709int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
1710 u32 ip_instance, u32 ring, 1710 u32 ip_instance, u32 ring,
1711 struct amdgpu_ring **out_ring); 1711 struct amdgpu_ring **out_ring);
1712void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes);
1712void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain); 1713void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
1713bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); 1714bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
1714int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages); 1715int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index a5df1ef306d9..fa34dcae392f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -850,16 +850,37 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
850 strcpy(fw_name, "amdgpu/fiji_smc.bin"); 850 strcpy(fw_name, "amdgpu/fiji_smc.bin");
851 break; 851 break;
852 case CHIP_POLARIS11: 852 case CHIP_POLARIS11:
853 if (type == CGS_UCODE_ID_SMU) 853 if (type == CGS_UCODE_ID_SMU) {
854 strcpy(fw_name, "amdgpu/polaris11_smc.bin"); 854 if (((adev->pdev->device == 0x67ef) &&
855 else if (type == CGS_UCODE_ID_SMU_SK) 855 ((adev->pdev->revision == 0xe0) ||
856 (adev->pdev->revision == 0xe2) ||
857 (adev->pdev->revision == 0xe5))) ||
858 ((adev->pdev->device == 0x67ff) &&
859 ((adev->pdev->revision == 0xcf) ||
860 (adev->pdev->revision == 0xef) ||
861 (adev->pdev->revision == 0xff))))
862 strcpy(fw_name, "amdgpu/polaris11_k_smc.bin");
863 else
864 strcpy(fw_name, "amdgpu/polaris11_smc.bin");
865 } else if (type == CGS_UCODE_ID_SMU_SK) {
856 strcpy(fw_name, "amdgpu/polaris11_smc_sk.bin"); 866 strcpy(fw_name, "amdgpu/polaris11_smc_sk.bin");
867 }
857 break; 868 break;
858 case CHIP_POLARIS10: 869 case CHIP_POLARIS10:
859 if (type == CGS_UCODE_ID_SMU) 870 if (type == CGS_UCODE_ID_SMU) {
860 strcpy(fw_name, "amdgpu/polaris10_smc.bin"); 871 if ((adev->pdev->device == 0x67df) &&
861 else if (type == CGS_UCODE_ID_SMU_SK) 872 ((adev->pdev->revision == 0xe0) ||
873 (adev->pdev->revision == 0xe3) ||
874 (adev->pdev->revision == 0xe4) ||
875 (adev->pdev->revision == 0xe5) ||
876 (adev->pdev->revision == 0xe7) ||
877 (adev->pdev->revision == 0xef)))
878 strcpy(fw_name, "amdgpu/polaris10_k_smc.bin");
879 else
880 strcpy(fw_name, "amdgpu/polaris10_smc.bin");
881 } else if (type == CGS_UCODE_ID_SMU_SK) {
862 strcpy(fw_name, "amdgpu/polaris10_smc_sk.bin"); 882 strcpy(fw_name, "amdgpu/polaris10_smc_sk.bin");
883 }
863 break; 884 break;
864 case CHIP_POLARIS12: 885 case CHIP_POLARIS12:
865 strcpy(fw_name, "amdgpu/polaris12_smc.bin"); 886 strcpy(fw_name, "amdgpu/polaris12_smc.bin");
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index cf2e8c4e9b8b..57301f5936fa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -344,8 +344,7 @@ static u64 amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev)
344 * submission. This can result in a debt that can stop buffer migrations 344 * submission. This can result in a debt that can stop buffer migrations
345 * temporarily. 345 * temporarily.
346 */ 346 */
347static void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, 347void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes)
348 u64 num_bytes)
349{ 348{
350 spin_lock(&adev->mm_stats.lock); 349 spin_lock(&adev->mm_stats.lock);
351 adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes); 350 adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 9bd1b4eae32e..ec7037a48b6e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -487,67 +487,50 @@ static int amdgpu_gem_va_check(void *param, struct amdgpu_bo *bo)
487 * 487 *
488 * @adev: amdgpu_device pointer 488 * @adev: amdgpu_device pointer
489 * @bo_va: bo_va to update 489 * @bo_va: bo_va to update
490 * @list: validation list
491 * @operation: map or unmap
490 * 492 *
491 * Update the bo_va directly after setting it's address. Errors are not 493 * Update the bo_va directly after setting its address. Errors are not
492 * vital here, so they are not reported back to userspace. 494 * vital here, so they are not reported back to userspace.
493 */ 495 */
494static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, 496static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
495 struct amdgpu_bo_va *bo_va, 497 struct amdgpu_bo_va *bo_va,
498 struct list_head *list,
496 uint32_t operation) 499 uint32_t operation)
497{ 500{
498 struct ttm_validate_buffer tv, *entry; 501 struct ttm_validate_buffer *entry;
499 struct amdgpu_bo_list_entry vm_pd; 502 int r = -ERESTARTSYS;
500 struct ww_acquire_ctx ticket;
501 struct list_head list, duplicates;
502 int r;
503
504 INIT_LIST_HEAD(&list);
505 INIT_LIST_HEAD(&duplicates);
506
507 tv.bo = &bo_va->bo->tbo;
508 tv.shared = true;
509 list_add(&tv.head, &list);
510 503
511 amdgpu_vm_get_pd_bo(bo_va->vm, &list, &vm_pd); 504 list_for_each_entry(entry, list, head) {
512
513 /* Provide duplicates to avoid -EALREADY */
514 r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates);
515 if (r)
516 goto error_print;
517
518 list_for_each_entry(entry, &list, head) {
519 struct amdgpu_bo *bo = 505 struct amdgpu_bo *bo =
520 container_of(entry->bo, struct amdgpu_bo, tbo); 506 container_of(entry->bo, struct amdgpu_bo, tbo);
521 507
522 /* if anything is swapped out don't swap it in here, 508 /* if anything is swapped out don't swap it in here,
523 just abort and wait for the next CS */ 509 just abort and wait for the next CS */
524 if (!amdgpu_bo_gpu_accessible(bo)) 510 if (!amdgpu_bo_gpu_accessible(bo))
525 goto error_unreserve; 511 goto error;
526 512
527 if (bo->shadow && !amdgpu_bo_gpu_accessible(bo->shadow)) 513 if (bo->shadow && !amdgpu_bo_gpu_accessible(bo->shadow))
528 goto error_unreserve; 514 goto error;
529 } 515 }
530 516
531 r = amdgpu_vm_validate_pt_bos(adev, bo_va->vm, amdgpu_gem_va_check, 517 r = amdgpu_vm_validate_pt_bos(adev, bo_va->vm, amdgpu_gem_va_check,
532 NULL); 518 NULL);
533 if (r) 519 if (r)
534 goto error_unreserve; 520 goto error;
535 521
536 r = amdgpu_vm_update_page_directory(adev, bo_va->vm); 522 r = amdgpu_vm_update_page_directory(adev, bo_va->vm);
537 if (r) 523 if (r)
538 goto error_unreserve; 524 goto error;
539 525
540 r = amdgpu_vm_clear_freed(adev, bo_va->vm); 526 r = amdgpu_vm_clear_freed(adev, bo_va->vm);
541 if (r) 527 if (r)
542 goto error_unreserve; 528 goto error;
543 529
544 if (operation == AMDGPU_VA_OP_MAP) 530 if (operation == AMDGPU_VA_OP_MAP)
545 r = amdgpu_vm_bo_update(adev, bo_va, false); 531 r = amdgpu_vm_bo_update(adev, bo_va, false);
546 532
547error_unreserve: 533error:
548 ttm_eu_backoff_reservation(&ticket, &list);
549
550error_print:
551 if (r && r != -ERESTARTSYS) 534 if (r && r != -ERESTARTSYS)
552 DRM_ERROR("Couldn't update BO_VA (%d)\n", r); 535 DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
553} 536}
@@ -564,7 +547,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
564 struct amdgpu_bo_list_entry vm_pd; 547 struct amdgpu_bo_list_entry vm_pd;
565 struct ttm_validate_buffer tv; 548 struct ttm_validate_buffer tv;
566 struct ww_acquire_ctx ticket; 549 struct ww_acquire_ctx ticket;
567 struct list_head list, duplicates; 550 struct list_head list;
568 uint32_t invalid_flags, va_flags = 0; 551 uint32_t invalid_flags, va_flags = 0;
569 int r = 0; 552 int r = 0;
570 553
@@ -602,14 +585,13 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
602 return -ENOENT; 585 return -ENOENT;
603 abo = gem_to_amdgpu_bo(gobj); 586 abo = gem_to_amdgpu_bo(gobj);
604 INIT_LIST_HEAD(&list); 587 INIT_LIST_HEAD(&list);
605 INIT_LIST_HEAD(&duplicates);
606 tv.bo = &abo->tbo; 588 tv.bo = &abo->tbo;
607 tv.shared = true; 589 tv.shared = false;
608 list_add(&tv.head, &list); 590 list_add(&tv.head, &list);
609 591
610 amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd); 592 amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd);
611 593
612 r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates); 594 r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL);
613 if (r) { 595 if (r) {
614 drm_gem_object_unreference_unlocked(gobj); 596 drm_gem_object_unreference_unlocked(gobj);
615 return r; 597 return r;
@@ -640,10 +622,10 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
640 default: 622 default:
641 break; 623 break;
642 } 624 }
643 ttm_eu_backoff_reservation(&ticket, &list);
644 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && 625 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) &&
645 !amdgpu_vm_debug) 626 !amdgpu_vm_debug)
646 amdgpu_gem_va_update_vm(adev, bo_va, args->operation); 627 amdgpu_gem_va_update_vm(adev, bo_va, &list, args->operation);
628 ttm_eu_backoff_reservation(&ticket, &list);
647 629
648 drm_gem_object_unreference_unlocked(gobj); 630 drm_gem_object_unreference_unlocked(gobj);
649 return r; 631 return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index d1aa291b2638..be80a4a68d7b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -323,6 +323,7 @@ int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
323 struct amdgpu_bo *bo; 323 struct amdgpu_bo *bo;
324 enum ttm_bo_type type; 324 enum ttm_bo_type type;
325 unsigned long page_align; 325 unsigned long page_align;
326 u64 initial_bytes_moved;
326 size_t acc_size; 327 size_t acc_size;
327 int r; 328 int r;
328 329
@@ -374,8 +375,10 @@ int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
374 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758 375 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
375 */ 376 */
376 377
378#ifndef CONFIG_COMPILE_TEST
377#warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \ 379#warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
378 thanks to write-combining 380 thanks to write-combining
381#endif
379 382
380 if (bo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 383 if (bo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
381 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " 384 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
@@ -399,12 +402,20 @@ int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
399 locked = ww_mutex_trylock(&bo->tbo.ttm_resv.lock); 402 locked = ww_mutex_trylock(&bo->tbo.ttm_resv.lock);
400 WARN_ON(!locked); 403 WARN_ON(!locked);
401 } 404 }
405
406 initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
402 r = ttm_bo_init(&adev->mman.bdev, &bo->tbo, size, type, 407 r = ttm_bo_init(&adev->mman.bdev, &bo->tbo, size, type,
403 &bo->placement, page_align, !kernel, NULL, 408 &bo->placement, page_align, !kernel, NULL,
404 acc_size, sg, resv ? resv : &bo->tbo.ttm_resv, 409 acc_size, sg, resv ? resv : &bo->tbo.ttm_resv,
405 &amdgpu_ttm_bo_destroy); 410 &amdgpu_ttm_bo_destroy);
406 if (unlikely(r != 0)) 411 amdgpu_cs_report_moved_bytes(adev,
412 atomic64_read(&adev->num_bytes_moved) - initial_bytes_moved);
413
414 if (unlikely(r != 0)) {
415 if (!resv)
416 ww_mutex_unlock(&bo->tbo.resv->lock);
407 return r; 417 return r;
418 }
408 419
409 bo->tbo.priority = ilog2(bo->tbo.num_pages); 420 bo->tbo.priority = ilog2(bo->tbo.num_pages);
410 if (kernel) 421 if (kernel)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index a61882ddc804..95e026a4a2de 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1142,12 +1142,22 @@ void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
1142 /* XXX select vce level based on ring/task */ 1142 /* XXX select vce level based on ring/task */
1143 adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL; 1143 adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL;
1144 mutex_unlock(&adev->pm.mutex); 1144 mutex_unlock(&adev->pm.mutex);
1145 amdgpu_pm_compute_clocks(adev);
1146 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1147 AMD_PG_STATE_UNGATE);
1148 amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1149 AMD_CG_STATE_UNGATE);
1145 } else { 1150 } else {
1151 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1152 AMD_PG_STATE_GATE);
1153 amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1154 AMD_CG_STATE_GATE);
1146 mutex_lock(&adev->pm.mutex); 1155 mutex_lock(&adev->pm.mutex);
1147 adev->pm.dpm.vce_active = false; 1156 adev->pm.dpm.vce_active = false;
1148 mutex_unlock(&adev->pm.mutex); 1157 mutex_unlock(&adev->pm.mutex);
1158 amdgpu_pm_compute_clocks(adev);
1149 } 1159 }
1150 amdgpu_pm_compute_clocks(adev); 1160
1151 } 1161 }
1152} 1162}
1153 1163
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index 6f62ac473064..6d6ab7f11b4c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -1113,6 +1113,11 @@ static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
1113 amdgpu_dpm_enable_uvd(adev, false); 1113 amdgpu_dpm_enable_uvd(adev, false);
1114 } else { 1114 } else {
1115 amdgpu_asic_set_uvd_clocks(adev, 0, 0); 1115 amdgpu_asic_set_uvd_clocks(adev, 0, 0);
1116 /* shutdown the UVD block */
1117 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1118 AMD_PG_STATE_GATE);
1119 amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1120 AMD_CG_STATE_GATE);
1116 } 1121 }
1117 } else { 1122 } else {
1118 schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT); 1123 schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT);
@@ -1129,6 +1134,10 @@ void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring)
1129 amdgpu_dpm_enable_uvd(adev, true); 1134 amdgpu_dpm_enable_uvd(adev, true);
1130 } else { 1135 } else {
1131 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 1136 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
1137 amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1138 AMD_CG_STATE_UNGATE);
1139 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1140 AMD_PG_STATE_UNGATE);
1132 } 1141 }
1133 } 1142 }
1134} 1143}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index 79bc9c7aad45..e2c06780ce49 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -321,6 +321,10 @@ static void amdgpu_vce_idle_work_handler(struct work_struct *work)
321 amdgpu_dpm_enable_vce(adev, false); 321 amdgpu_dpm_enable_vce(adev, false);
322 } else { 322 } else {
323 amdgpu_asic_set_vce_clocks(adev, 0, 0); 323 amdgpu_asic_set_vce_clocks(adev, 0, 0);
324 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
325 AMD_PG_STATE_GATE);
326 amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
327 AMD_CG_STATE_GATE);
324 } 328 }
325 } else { 329 } else {
326 schedule_delayed_work(&adev->vce.idle_work, VCE_IDLE_TIMEOUT); 330 schedule_delayed_work(&adev->vce.idle_work, VCE_IDLE_TIMEOUT);
@@ -346,6 +350,11 @@ void amdgpu_vce_ring_begin_use(struct amdgpu_ring *ring)
346 amdgpu_dpm_enable_vce(adev, true); 350 amdgpu_dpm_enable_vce(adev, true);
347 } else { 351 } else {
348 amdgpu_asic_set_vce_clocks(adev, 53300, 40000); 352 amdgpu_asic_set_vce_clocks(adev, 53300, 40000);
353 amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
354 AMD_CG_STATE_UNGATE);
355 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
356 AMD_PG_STATE_UNGATE);
357
349 } 358 }
350 } 359 }
351 mutex_unlock(&adev->vce.idle_mutex); 360 mutex_unlock(&adev->vce.idle_mutex);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index 3fd951c71d1b..dcfb7df3caf4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -83,7 +83,6 @@ int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm)
83 DRM_ERROR("failed to do bo_map on static CSA, err=%d\n", r); 83 DRM_ERROR("failed to do bo_map on static CSA, err=%d\n", r);
84 amdgpu_vm_bo_rmv(adev, bo_va); 84 amdgpu_vm_bo_rmv(adev, bo_va);
85 ttm_eu_backoff_reservation(&ticket, &list); 85 ttm_eu_backoff_reservation(&ticket, &list);
86 kfree(bo_va);
87 return r; 86 return r;
88 } 87 }
89 88
diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index 9498e78b90d7..f97ecb49972e 100644
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -2210,7 +2210,6 @@ static void ci_clear_vc(struct amdgpu_device *adev)
2210 2210
2211static int ci_upload_firmware(struct amdgpu_device *adev) 2211static int ci_upload_firmware(struct amdgpu_device *adev)
2212{ 2212{
2213 struct ci_power_info *pi = ci_get_pi(adev);
2214 int i, ret; 2213 int i, ret;
2215 2214
2216 if (amdgpu_ci_is_smc_running(adev)) { 2215 if (amdgpu_ci_is_smc_running(adev)) {
@@ -2227,7 +2226,7 @@ static int ci_upload_firmware(struct amdgpu_device *adev)
2227 amdgpu_ci_stop_smc_clock(adev); 2226 amdgpu_ci_stop_smc_clock(adev);
2228 amdgpu_ci_reset_smc(adev); 2227 amdgpu_ci_reset_smc(adev);
2229 2228
2230 ret = amdgpu_ci_load_smc_ucode(adev, pi->sram_end); 2229 ret = amdgpu_ci_load_smc_ucode(adev, SMC_RAM_END);
2231 2230
2232 return ret; 2231 return ret;
2233 2232
@@ -4257,12 +4256,6 @@ static int ci_update_vce_dpm(struct amdgpu_device *adev,
4257 4256
4258 if (amdgpu_current_state->evclk != amdgpu_new_state->evclk) { 4257 if (amdgpu_current_state->evclk != amdgpu_new_state->evclk) {
4259 if (amdgpu_new_state->evclk) { 4258 if (amdgpu_new_state->evclk) {
4260 /* turn the clocks on when encoding */
4261 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
4262 AMD_CG_STATE_UNGATE);
4263 if (ret)
4264 return ret;
4265
4266 pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(adev); 4259 pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(adev);
4267 tmp = RREG32_SMC(ixDPM_TABLE_475); 4260 tmp = RREG32_SMC(ixDPM_TABLE_475);
4268 tmp &= ~DPM_TABLE_475__VceBootLevel_MASK; 4261 tmp &= ~DPM_TABLE_475__VceBootLevel_MASK;
@@ -4274,9 +4267,6 @@ static int ci_update_vce_dpm(struct amdgpu_device *adev,
4274 ret = ci_enable_vce_dpm(adev, false); 4267 ret = ci_enable_vce_dpm(adev, false);
4275 if (ret) 4268 if (ret)
4276 return ret; 4269 return ret;
4277 /* turn the clocks off when not encoding */
4278 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
4279 AMD_CG_STATE_GATE);
4280 } 4270 }
4281 } 4271 }
4282 return ret; 4272 return ret;
@@ -6278,13 +6268,13 @@ static int ci_dpm_sw_init(void *handle)
6278 adev->pm.current_mclk = adev->clock.default_mclk; 6268 adev->pm.current_mclk = adev->clock.default_mclk;
6279 adev->pm.int_thermal_type = THERMAL_TYPE_NONE; 6269 adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
6280 6270
6281 if (amdgpu_dpm == 0)
6282 return 0;
6283
6284 ret = ci_dpm_init_microcode(adev); 6271 ret = ci_dpm_init_microcode(adev);
6285 if (ret) 6272 if (ret)
6286 return ret; 6273 return ret;
6287 6274
6275 if (amdgpu_dpm == 0)
6276 return 0;
6277
6288 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler); 6278 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
6289 mutex_lock(&adev->pm.mutex); 6279 mutex_lock(&adev->pm.mutex);
6290 ret = ci_dpm_init(adev); 6280 ret = ci_dpm_init(adev);
@@ -6328,8 +6318,15 @@ static int ci_dpm_hw_init(void *handle)
6328 6318
6329 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6319 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6330 6320
6331 if (!amdgpu_dpm) 6321 if (!amdgpu_dpm) {
6322 ret = ci_upload_firmware(adev);
6323 if (ret) {
6324 DRM_ERROR("ci_upload_firmware failed\n");
6325 return ret;
6326 }
6327 ci_dpm_start_smc(adev);
6332 return 0; 6328 return 0;
6329 }
6333 6330
6334 mutex_lock(&adev->pm.mutex); 6331 mutex_lock(&adev->pm.mutex);
6335 ci_dpm_setup_asic(adev); 6332 ci_dpm_setup_asic(adev);
@@ -6351,6 +6348,8 @@ static int ci_dpm_hw_fini(void *handle)
6351 mutex_lock(&adev->pm.mutex); 6348 mutex_lock(&adev->pm.mutex);
6352 ci_dpm_disable(adev); 6349 ci_dpm_disable(adev);
6353 mutex_unlock(&adev->pm.mutex); 6350 mutex_unlock(&adev->pm.mutex);
6351 } else {
6352 ci_dpm_stop_smc(adev);
6354 } 6353 }
6355 6354
6356 return 0; 6355 return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 7da688b0d27d..7c39b538dc0e 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -1722,8 +1722,8 @@ static int cik_common_early_init(void *handle)
1722 AMD_PG_SUPPORT_GFX_SMG | 1722 AMD_PG_SUPPORT_GFX_SMG |
1723 AMD_PG_SUPPORT_GFX_DMG |*/ 1723 AMD_PG_SUPPORT_GFX_DMG |*/
1724 AMD_PG_SUPPORT_UVD | 1724 AMD_PG_SUPPORT_UVD |
1725 /*AMD_PG_SUPPORT_VCE | 1725 AMD_PG_SUPPORT_VCE |
1726 AMD_PG_SUPPORT_CP | 1726 /* AMD_PG_SUPPORT_CP |
1727 AMD_PG_SUPPORT_GDS | 1727 AMD_PG_SUPPORT_GDS |
1728 AMD_PG_SUPPORT_RLC_SMU_HS | 1728 AMD_PG_SUPPORT_RLC_SMU_HS |
1729 AMD_PG_SUPPORT_ACP | 1729 AMD_PG_SUPPORT_ACP |
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index c998f6aaaf36..2086e7e68de4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -1325,21 +1325,19 @@ static u32 gfx_v6_0_create_bitmask(u32 bit_width)
1325 return (u32)(((u64)1 << bit_width) - 1); 1325 return (u32)(((u64)1 << bit_width) - 1);
1326} 1326}
1327 1327
1328static u32 gfx_v6_0_get_rb_disabled(struct amdgpu_device *adev, 1328static u32 gfx_v6_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1329 u32 max_rb_num_per_se,
1330 u32 sh_per_se)
1331{ 1329{
1332 u32 data, mask; 1330 u32 data, mask;
1333 1331
1334 data = RREG32(mmCC_RB_BACKEND_DISABLE); 1332 data = RREG32(mmCC_RB_BACKEND_DISABLE) |
1335 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 1333 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1336 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1337 1334
1338 data >>= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 1335 data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE);
1339 1336
1340 mask = gfx_v6_0_create_bitmask(max_rb_num_per_se / sh_per_se); 1337 mask = gfx_v6_0_create_bitmask(adev->gfx.config.max_backends_per_se/
1338 adev->gfx.config.max_sh_per_se);
1341 1339
1342 return data & mask; 1340 return ~data & mask;
1343} 1341}
1344 1342
1345static void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32 *rconf) 1343static void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32 *rconf)
@@ -1468,68 +1466,55 @@ static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev,
1468 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1466 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1469} 1467}
1470 1468
1471static void gfx_v6_0_setup_rb(struct amdgpu_device *adev, 1469static void gfx_v6_0_setup_rb(struct amdgpu_device *adev)
1472 u32 se_num, u32 sh_per_se,
1473 u32 max_rb_num_per_se)
1474{ 1470{
1475 int i, j; 1471 int i, j;
1476 u32 data, mask; 1472 u32 data;
1477 u32 disabled_rbs = 0; 1473 u32 raster_config = 0;
1478 u32 enabled_rbs = 0; 1474 u32 active_rbs = 0;
1475 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1476 adev->gfx.config.max_sh_per_se;
1479 unsigned num_rb_pipes; 1477 unsigned num_rb_pipes;
1480 1478
1481 mutex_lock(&adev->grbm_idx_mutex); 1479 mutex_lock(&adev->grbm_idx_mutex);
1482 for (i = 0; i < se_num; i++) { 1480 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1483 for (j = 0; j < sh_per_se; j++) { 1481 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1484 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); 1482 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1485 data = gfx_v6_0_get_rb_disabled(adev, max_rb_num_per_se, sh_per_se); 1483 data = gfx_v6_0_get_rb_active_bitmap(adev);
1486 disabled_rbs |= data << ((i * sh_per_se + j) * 2); 1484 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1485 rb_bitmap_width_per_sh);
1487 } 1486 }
1488 } 1487 }
1489 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1488 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1490 mutex_unlock(&adev->grbm_idx_mutex);
1491
1492 mask = 1;
1493 for (i = 0; i < max_rb_num_per_se * se_num; i++) {
1494 if (!(disabled_rbs & mask))
1495 enabled_rbs |= mask;
1496 mask <<= 1;
1497 }
1498 1489
1499 adev->gfx.config.backend_enable_mask = enabled_rbs; 1490 adev->gfx.config.backend_enable_mask = active_rbs;
1500 adev->gfx.config.num_rbs = hweight32(enabled_rbs); 1491 adev->gfx.config.num_rbs = hweight32(active_rbs);
1501 1492
1502 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * 1493 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
1503 adev->gfx.config.max_shader_engines, 16); 1494 adev->gfx.config.max_shader_engines, 16);
1504 1495
1505 mutex_lock(&adev->grbm_idx_mutex); 1496 gfx_v6_0_raster_config(adev, &raster_config);
1506 for (i = 0; i < se_num; i++) {
1507 gfx_v6_0_select_se_sh(adev, i, 0xffffffff, 0xffffffff);
1508 data = 0;
1509 for (j = 0; j < sh_per_se; j++) {
1510 switch (enabled_rbs & 3) {
1511 case 1:
1512 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
1513 break;
1514 case 2:
1515 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
1516 break;
1517 case 3:
1518 default:
1519 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
1520 break;
1521 }
1522 enabled_rbs >>= 2;
1523 }
1524 gfx_v6_0_raster_config(adev, &data);
1525 1497
1526 if (!adev->gfx.config.backend_enable_mask || 1498 if (!adev->gfx.config.backend_enable_mask ||
1527 adev->gfx.config.num_rbs >= num_rb_pipes) 1499 adev->gfx.config.num_rbs >= num_rb_pipes) {
1528 WREG32(mmPA_SC_RASTER_CONFIG, data); 1500 WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
1529 else 1501 } else {
1530 gfx_v6_0_write_harvested_raster_configs(adev, data, 1502 gfx_v6_0_write_harvested_raster_configs(adev, raster_config,
1531 adev->gfx.config.backend_enable_mask, 1503 adev->gfx.config.backend_enable_mask,
1532 num_rb_pipes); 1504 num_rb_pipes);
1505 }
1506
1507 /* cache the values for userspace */
1508 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1509 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1510 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1511 adev->gfx.config.rb_config[i][j].rb_backend_disable =
1512 RREG32(mmCC_RB_BACKEND_DISABLE);
1513 adev->gfx.config.rb_config[i][j].user_rb_backend_disable =
1514 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1515 adev->gfx.config.rb_config[i][j].raster_config =
1516 RREG32(mmPA_SC_RASTER_CONFIG);
1517 }
1533 } 1518 }
1534 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1519 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1535 mutex_unlock(&adev->grbm_idx_mutex); 1520 mutex_unlock(&adev->grbm_idx_mutex);
@@ -1540,36 +1525,44 @@ static void gmc_v6_0_init_compute_vmid(struct amdgpu_device *adev)
1540} 1525}
1541*/ 1526*/
1542 1527
1543static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev, u32 cu_per_sh) 1528static void gfx_v6_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
1529 u32 bitmap)
1544{ 1530{
1545 u32 data, mask; 1531 u32 data;
1546 1532
1547 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG); 1533 if (!bitmap)
1548 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 1534 return;
1549 data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
1550 1535
1551 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 1536 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
1537 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
1552 1538
1553 mask = gfx_v6_0_create_bitmask(cu_per_sh); 1539 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
1540}
1554 1541
1555 return ~data & mask; 1542static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev)
1543{
1544 u32 data, mask;
1545
1546 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) |
1547 RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
1548
1549 mask = gfx_v6_0_create_bitmask(adev->gfx.config.max_cu_per_sh);
1550 return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask;
1556} 1551}
1557 1552
1558 1553
1559static void gfx_v6_0_setup_spi(struct amdgpu_device *adev, 1554static void gfx_v6_0_setup_spi(struct amdgpu_device *adev)
1560 u32 se_num, u32 sh_per_se,
1561 u32 cu_per_sh)
1562{ 1555{
1563 int i, j, k; 1556 int i, j, k;
1564 u32 data, mask; 1557 u32 data, mask;
1565 u32 active_cu = 0; 1558 u32 active_cu = 0;
1566 1559
1567 mutex_lock(&adev->grbm_idx_mutex); 1560 mutex_lock(&adev->grbm_idx_mutex);
1568 for (i = 0; i < se_num; i++) { 1561 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1569 for (j = 0; j < sh_per_se; j++) { 1562 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1570 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); 1563 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1571 data = RREG32(mmSPI_STATIC_THREAD_MGMT_3); 1564 data = RREG32(mmSPI_STATIC_THREAD_MGMT_3);
1572 active_cu = gfx_v6_0_get_cu_enabled(adev, cu_per_sh); 1565 active_cu = gfx_v6_0_get_cu_enabled(adev);
1573 1566
1574 mask = 1; 1567 mask = 1;
1575 for (k = 0; k < 16; k++) { 1568 for (k = 0; k < 16; k++) {
@@ -1717,6 +1710,9 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
1717 gb_addr_config |= 2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; 1710 gb_addr_config |= 2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1718 break; 1711 break;
1719 } 1712 }
1713 gb_addr_config &= ~GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK;
1714 if (adev->gfx.config.max_shader_engines == 2)
1715 gb_addr_config |= 1 << GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT;
1720 adev->gfx.config.gb_addr_config = gb_addr_config; 1716 adev->gfx.config.gb_addr_config = gb_addr_config;
1721 1717
1722 WREG32(mmGB_ADDR_CONFIG, gb_addr_config); 1718 WREG32(mmGB_ADDR_CONFIG, gb_addr_config);
@@ -1735,13 +1731,9 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
1735#endif 1731#endif
1736 gfx_v6_0_tiling_mode_table_init(adev); 1732 gfx_v6_0_tiling_mode_table_init(adev);
1737 1733
1738 gfx_v6_0_setup_rb(adev, adev->gfx.config.max_shader_engines, 1734 gfx_v6_0_setup_rb(adev);
1739 adev->gfx.config.max_sh_per_se,
1740 adev->gfx.config.max_backends_per_se);
1741 1735
1742 gfx_v6_0_setup_spi(adev, adev->gfx.config.max_shader_engines, 1736 gfx_v6_0_setup_spi(adev);
1743 adev->gfx.config.max_sh_per_se,
1744 adev->gfx.config.max_cu_per_sh);
1745 1737
1746 gfx_v6_0_get_cu_info(adev); 1738 gfx_v6_0_get_cu_info(adev);
1747 1739
@@ -2941,61 +2933,16 @@ static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev,
2941 } 2933 }
2942} 2934}
2943 2935
2944static u32 gfx_v6_0_get_cu_active_bitmap(struct amdgpu_device *adev,
2945 u32 se, u32 sh)
2946{
2947
2948 u32 mask = 0, tmp, tmp1;
2949 int i;
2950
2951 mutex_lock(&adev->grbm_idx_mutex);
2952 gfx_v6_0_select_se_sh(adev, se, sh, 0xffffffff);
2953 tmp = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
2954 tmp1 = RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
2955 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2956 mutex_unlock(&adev->grbm_idx_mutex);
2957
2958 tmp &= 0xffff0000;
2959
2960 tmp |= tmp1;
2961 tmp >>= 16;
2962
2963 for (i = 0; i < adev->gfx.config.max_cu_per_sh; i ++) {
2964 mask <<= 1;
2965 mask |= 1;
2966 }
2967
2968 return (~tmp) & mask;
2969}
2970
2971static void gfx_v6_0_init_ao_cu_mask(struct amdgpu_device *adev) 2936static void gfx_v6_0_init_ao_cu_mask(struct amdgpu_device *adev)
2972{ 2937{
2973 u32 i, j, k, active_cu_number = 0; 2938 u32 tmp;
2974
2975 u32 mask, counter, cu_bitmap;
2976 u32 tmp = 0;
2977
2978 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
2979 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2980 mask = 1;
2981 cu_bitmap = 0;
2982 counter = 0;
2983 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
2984 if (gfx_v6_0_get_cu_active_bitmap(adev, i, j) & mask) {
2985 if (counter < 2)
2986 cu_bitmap |= mask;
2987 counter++;
2988 }
2989 mask <<= 1;
2990 }
2991 2939
2992 active_cu_number += counter; 2940 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
2993 tmp |= (cu_bitmap << (i * 16 + j * 8));
2994 }
2995 }
2996 2941
2997 WREG32(mmRLC_PG_AO_CU_MASK, tmp); 2942 tmp = RREG32(mmRLC_MAX_PG_CU);
2998 WREG32_FIELD(RLC_MAX_PG_CU, MAX_POWERED_UP_CU, active_cu_number); 2943 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
2944 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
2945 WREG32(mmRLC_MAX_PG_CU, tmp);
2999} 2946}
3000 2947
3001static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev, 2948static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
@@ -3770,18 +3717,26 @@ static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev)
3770 int i, j, k, counter, active_cu_number = 0; 3717 int i, j, k, counter, active_cu_number = 0;
3771 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 3718 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
3772 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 3719 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
3720 unsigned disable_masks[4 * 2];
3773 3721
3774 memset(cu_info, 0, sizeof(*cu_info)); 3722 memset(cu_info, 0, sizeof(*cu_info));
3775 3723
3724 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
3725
3726 mutex_lock(&adev->grbm_idx_mutex);
3776 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 3727 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3777 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 3728 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3778 mask = 1; 3729 mask = 1;
3779 ao_bitmap = 0; 3730 ao_bitmap = 0;
3780 counter = 0; 3731 counter = 0;
3781 bitmap = gfx_v6_0_get_cu_active_bitmap(adev, i, j); 3732 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
3733 if (i < 4 && j < 2)
3734 gfx_v6_0_set_user_cu_inactive_bitmap(
3735 adev, disable_masks[i * 2 + j]);
3736 bitmap = gfx_v6_0_get_cu_enabled(adev);
3782 cu_info->bitmap[i][j] = bitmap; 3737 cu_info->bitmap[i][j] = bitmap;
3783 3738
3784 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { 3739 for (k = 0; k < 16; k++) {
3785 if (bitmap & mask) { 3740 if (bitmap & mask) {
3786 if (counter < 2) 3741 if (counter < 2)
3787 ao_bitmap |= mask; 3742 ao_bitmap |= mask;
@@ -3794,6 +3749,9 @@ static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev)
3794 } 3749 }
3795 } 3750 }
3796 3751
3752 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3753 mutex_unlock(&adev->grbm_idx_mutex);
3754
3797 cu_info->number = active_cu_number; 3755 cu_info->number = active_cu_number;
3798 cu_info->ao_cu_mask = ao_cu_mask; 3756 cu_info->ao_cu_mask = ao_cu_mask;
3799} 3757}
diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
index 8785ca570729..f5a343cb0010 100644
--- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
@@ -1550,11 +1550,6 @@ static int kv_update_vce_dpm(struct amdgpu_device *adev,
1550 1550
1551 if (amdgpu_new_state->evclk > 0 && amdgpu_current_state->evclk == 0) { 1551 if (amdgpu_new_state->evclk > 0 && amdgpu_current_state->evclk == 0) {
1552 kv_dpm_powergate_vce(adev, false); 1552 kv_dpm_powergate_vce(adev, false);
1553 /* turn the clocks on when encoding */
1554 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1555 AMD_CG_STATE_UNGATE);
1556 if (ret)
1557 return ret;
1558 if (pi->caps_stable_p_state) 1553 if (pi->caps_stable_p_state)
1559 pi->vce_boot_level = table->count - 1; 1554 pi->vce_boot_level = table->count - 1;
1560 else 1555 else
@@ -1573,15 +1568,9 @@ static int kv_update_vce_dpm(struct amdgpu_device *adev,
1573 amdgpu_kv_send_msg_to_smc_with_parameter(adev, 1568 amdgpu_kv_send_msg_to_smc_with_parameter(adev,
1574 PPSMC_MSG_VCEDPM_SetEnabledMask, 1569 PPSMC_MSG_VCEDPM_SetEnabledMask,
1575 (1 << pi->vce_boot_level)); 1570 (1 << pi->vce_boot_level));
1576
1577 kv_enable_vce_dpm(adev, true); 1571 kv_enable_vce_dpm(adev, true);
1578 } else if (amdgpu_new_state->evclk == 0 && amdgpu_current_state->evclk > 0) { 1572 } else if (amdgpu_new_state->evclk == 0 && amdgpu_current_state->evclk > 0) {
1579 kv_enable_vce_dpm(adev, false); 1573 kv_enable_vce_dpm(adev, false);
1580 /* turn the clocks off when not encoding */
1581 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1582 AMD_CG_STATE_GATE);
1583 if (ret)
1584 return ret;
1585 kv_dpm_powergate_vce(adev, true); 1574 kv_dpm_powergate_vce(adev, true);
1586 } 1575 }
1587 1576
@@ -1688,70 +1677,44 @@ static void kv_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
1688 struct kv_power_info *pi = kv_get_pi(adev); 1677 struct kv_power_info *pi = kv_get_pi(adev);
1689 int ret; 1678 int ret;
1690 1679
1691 if (pi->uvd_power_gated == gate)
1692 return;
1693
1694 pi->uvd_power_gated = gate; 1680 pi->uvd_power_gated = gate;
1695 1681
1696 if (gate) { 1682 if (gate) {
1697 if (pi->caps_uvd_pg) { 1683 /* stop the UVD block */
1698 /* disable clockgating so we can properly shut down the block */ 1684 ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1699 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1685 AMD_PG_STATE_GATE);
1700 AMD_CG_STATE_UNGATE);
1701 /* shutdown the UVD block */
1702 ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1703 AMD_PG_STATE_GATE);
1704 /* XXX: check for errors */
1705 }
1706 kv_update_uvd_dpm(adev, gate); 1686 kv_update_uvd_dpm(adev, gate);
1707 if (pi->caps_uvd_pg) 1687 if (pi->caps_uvd_pg)
1708 /* power off the UVD block */ 1688 /* power off the UVD block */
1709 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerOFF); 1689 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerOFF);
1710 } else { 1690 } else {
1711 if (pi->caps_uvd_pg) { 1691 if (pi->caps_uvd_pg)
1712 /* power on the UVD block */ 1692 /* power on the UVD block */
1713 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerON); 1693 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerON);
1714 /* re-init the UVD block */ 1694 /* re-init the UVD block */
1715 ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1716 AMD_PG_STATE_UNGATE);
1717 /* enable clockgating. hw will dynamically gate/ungate clocks on the fly */
1718 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1719 AMD_CG_STATE_GATE);
1720 /* XXX: check for errors */
1721 }
1722 kv_update_uvd_dpm(adev, gate); 1695 kv_update_uvd_dpm(adev, gate);
1696
1697 ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1698 AMD_PG_STATE_UNGATE);
1723 } 1699 }
1724} 1700}
1725 1701
1726static void kv_dpm_powergate_vce(struct amdgpu_device *adev, bool gate) 1702static void kv_dpm_powergate_vce(struct amdgpu_device *adev, bool gate)
1727{ 1703{
1728 struct kv_power_info *pi = kv_get_pi(adev); 1704 struct kv_power_info *pi = kv_get_pi(adev);
1729 int ret;
1730 1705
1731 if (pi->vce_power_gated == gate) 1706 if (pi->vce_power_gated == gate)
1732 return; 1707 return;
1733 1708
1734 pi->vce_power_gated = gate; 1709 pi->vce_power_gated = gate;
1735 1710
1736 if (gate) { 1711 if (!pi->caps_vce_pg)
1737 if (pi->caps_vce_pg) { 1712 return;
1738 /* shutdown the VCE block */ 1713
1739 ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, 1714 if (gate)
1740 AMD_PG_STATE_GATE); 1715 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerOFF);
1741 /* XXX: check for errors */ 1716 else
1742 /* power off the VCE block */ 1717 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerON);
1743 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerOFF);
1744 }
1745 } else {
1746 if (pi->caps_vce_pg) {
1747 /* power on the VCE block */
1748 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerON);
1749 /* re-init the VCE block */
1750 ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1751 AMD_PG_STATE_UNGATE);
1752 /* XXX: check for errors */
1753 }
1754 }
1755} 1718}
1756 1719
1757static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate) 1720static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate)
@@ -3009,8 +2972,7 @@ static int kv_dpm_late_init(void *handle)
3009 2972
3010 kv_dpm_powergate_acp(adev, true); 2973 kv_dpm_powergate_acp(adev, true);
3011 kv_dpm_powergate_samu(adev, true); 2974 kv_dpm_powergate_samu(adev, true);
3012 kv_dpm_powergate_vce(adev, true); 2975
3013 kv_dpm_powergate_uvd(adev, true);
3014 return 0; 2976 return 0;
3015} 2977}
3016 2978
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index da46992f7b18..b71e3faa40db 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1010,24 +1010,81 @@ static struct amdgpu_allowed_register_entry si_allowed_read_registers[] = {
1010 {PA_SC_RASTER_CONFIG, false, true}, 1010 {PA_SC_RASTER_CONFIG, false, true},
1011}; 1011};
1012 1012
1013static uint32_t si_read_indexed_register(struct amdgpu_device *adev, 1013static uint32_t si_get_register_value(struct amdgpu_device *adev,
1014 u32 se_num, u32 sh_num, 1014 bool indexed, u32 se_num,
1015 u32 reg_offset) 1015 u32 sh_num, u32 reg_offset)
1016{ 1016{
1017 uint32_t val; 1017 if (indexed) {
1018 uint32_t val;
1019 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num;
1020 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num;
1021
1022 switch (reg_offset) {
1023 case mmCC_RB_BACKEND_DISABLE:
1024 return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable;
1025 case mmGC_USER_RB_BACKEND_DISABLE:
1026 return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable;
1027 case mmPA_SC_RASTER_CONFIG:
1028 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config;
1029 }
1018 1030
1019 mutex_lock(&adev->grbm_idx_mutex); 1031 mutex_lock(&adev->grbm_idx_mutex);
1020 if (se_num != 0xffffffff || sh_num != 0xffffffff) 1032 if (se_num != 0xffffffff || sh_num != 0xffffffff)
1021 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 1033 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
1022 1034
1023 val = RREG32(reg_offset); 1035 val = RREG32(reg_offset);
1024 1036
1025 if (se_num != 0xffffffff || sh_num != 0xffffffff) 1037 if (se_num != 0xffffffff || sh_num != 0xffffffff)
1026 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1038 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1027 mutex_unlock(&adev->grbm_idx_mutex); 1039 mutex_unlock(&adev->grbm_idx_mutex);
1028 return val; 1040 return val;
1041 } else {
1042 unsigned idx;
1043
1044 switch (reg_offset) {
1045 case mmGB_ADDR_CONFIG:
1046 return adev->gfx.config.gb_addr_config;
1047 case mmMC_ARB_RAMCFG:
1048 return adev->gfx.config.mc_arb_ramcfg;
1049 case mmGB_TILE_MODE0:
1050 case mmGB_TILE_MODE1:
1051 case mmGB_TILE_MODE2:
1052 case mmGB_TILE_MODE3:
1053 case mmGB_TILE_MODE4:
1054 case mmGB_TILE_MODE5:
1055 case mmGB_TILE_MODE6:
1056 case mmGB_TILE_MODE7:
1057 case mmGB_TILE_MODE8:
1058 case mmGB_TILE_MODE9:
1059 case mmGB_TILE_MODE10:
1060 case mmGB_TILE_MODE11:
1061 case mmGB_TILE_MODE12:
1062 case mmGB_TILE_MODE13:
1063 case mmGB_TILE_MODE14:
1064 case mmGB_TILE_MODE15:
1065 case mmGB_TILE_MODE16:
1066 case mmGB_TILE_MODE17:
1067 case mmGB_TILE_MODE18:
1068 case mmGB_TILE_MODE19:
1069 case mmGB_TILE_MODE20:
1070 case mmGB_TILE_MODE21:
1071 case mmGB_TILE_MODE22:
1072 case mmGB_TILE_MODE23:
1073 case mmGB_TILE_MODE24:
1074 case mmGB_TILE_MODE25:
1075 case mmGB_TILE_MODE26:
1076 case mmGB_TILE_MODE27:
1077 case mmGB_TILE_MODE28:
1078 case mmGB_TILE_MODE29:
1079 case mmGB_TILE_MODE30:
1080 case mmGB_TILE_MODE31:
1081 idx = (reg_offset - mmGB_TILE_MODE0);
1082 return adev->gfx.config.tile_mode_array[idx];
1083 default:
1084 return RREG32(reg_offset);
1085 }
1086 }
1029} 1087}
1030
1031static int si_read_register(struct amdgpu_device *adev, u32 se_num, 1088static int si_read_register(struct amdgpu_device *adev, u32 se_num,
1032 u32 sh_num, u32 reg_offset, u32 *value) 1089 u32 sh_num, u32 reg_offset, u32 *value)
1033{ 1090{
@@ -1039,10 +1096,9 @@ static int si_read_register(struct amdgpu_device *adev, u32 se_num,
1039 continue; 1096 continue;
1040 1097
1041 if (!si_allowed_read_registers[i].untouched) 1098 if (!si_allowed_read_registers[i].untouched)
1042 *value = si_allowed_read_registers[i].grbm_indexed ? 1099 *value = si_get_register_value(adev,
1043 si_read_indexed_register(adev, se_num, 1100 si_allowed_read_registers[i].grbm_indexed,
1044 sh_num, reg_offset) : 1101 se_num, sh_num, reg_offset);
1045 RREG32(reg_offset);
1046 return 0; 1102 return 0;
1047 } 1103 }
1048 return -EINVAL; 1104 return -EINVAL;
diff --git a/drivers/gpu/drm/amd/amdgpu/si_enums.h b/drivers/gpu/drm/amd/amdgpu/si_enums.h
index fde2086246fa..dc9e0e6b4558 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_enums.h
+++ b/drivers/gpu/drm/amd/amdgpu/si_enums.h
@@ -143,8 +143,8 @@
143#define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D 143#define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D
144 144
145#define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003 145#define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003
146#define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002 146#define VERDE_GB_ADDR_CONFIG_GOLDEN 0x02010002
147#define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02010001 147#define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02011003
148 148
149#define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ 149#define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \
150 (((op) & 0xFF) << 8) | \ 150 (((op) & 0xFF) << 8) | \
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
index 7fb9137dd89b..f15df99f0a06 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
@@ -159,9 +159,6 @@ static int uvd_v4_2_hw_init(void *handle)
159 159
160 uvd_v4_2_enable_mgcg(adev, true); 160 uvd_v4_2_enable_mgcg(adev, true);
161 amdgpu_asic_set_uvd_clocks(adev, 10000, 10000); 161 amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
162 r = uvd_v4_2_start(adev);
163 if (r)
164 goto done;
165 162
166 ring->ready = true; 163 ring->ready = true;
167 r = amdgpu_ring_test_ring(ring); 164 r = amdgpu_ring_test_ring(ring);
@@ -198,7 +195,6 @@ static int uvd_v4_2_hw_init(void *handle)
198 amdgpu_ring_commit(ring); 195 amdgpu_ring_commit(ring);
199 196
200done: 197done:
201
202 if (!r) 198 if (!r)
203 DRM_INFO("UVD initialized successfully.\n"); 199 DRM_INFO("UVD initialized successfully.\n");
204 200
@@ -217,7 +213,9 @@ static int uvd_v4_2_hw_fini(void *handle)
217 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 213 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
218 struct amdgpu_ring *ring = &adev->uvd.ring; 214 struct amdgpu_ring *ring = &adev->uvd.ring;
219 215
220 uvd_v4_2_stop(adev); 216 if (RREG32(mmUVD_STATUS) != 0)
217 uvd_v4_2_stop(adev);
218
221 ring->ready = false; 219 ring->ready = false;
222 220
223 return 0; 221 return 0;
@@ -267,37 +265,26 @@ static int uvd_v4_2_start(struct amdgpu_device *adev)
267 struct amdgpu_ring *ring = &adev->uvd.ring; 265 struct amdgpu_ring *ring = &adev->uvd.ring;
268 uint32_t rb_bufsz; 266 uint32_t rb_bufsz;
269 int i, j, r; 267 int i, j, r;
268 u32 tmp;
270 /* disable byte swapping */ 269 /* disable byte swapping */
271 u32 lmi_swap_cntl = 0; 270 u32 lmi_swap_cntl = 0;
272 u32 mp_swap_cntl = 0; 271 u32 mp_swap_cntl = 0;
273 272
274 WREG32(mmUVD_CGC_GATE, 0); 273 /* set uvd busy */
275 uvd_v4_2_set_dcm(adev, true); 274 WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2));
276 275
277 uvd_v4_2_mc_resume(adev); 276 uvd_v4_2_set_dcm(adev, true);
278 277 WREG32(mmUVD_CGC_GATE, 0);
279 /* disable interupt */
280 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
281
282 /* Stall UMC and register bus before resetting VCPU */
283 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
284 mdelay(1);
285
286 /* put LMI, VCPU, RBC etc... into reset */
287 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
288 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
289 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
290 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
291 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
292 mdelay(5);
293 278
294 /* take UVD block out of reset */ 279 /* take UVD block out of reset */
295 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 280 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
296 mdelay(5); 281 mdelay(5);
297 282
298 /* initialize UVD memory controller */ 283 /* enable VCPU clock */
299 WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) | 284 WREG32(mmUVD_VCPU_CNTL, 1 << 9);
300 (1 << 21) | (1 << 9) | (1 << 20)); 285
286 /* disable interupt */
287 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
301 288
302#ifdef __BIG_ENDIAN 289#ifdef __BIG_ENDIAN
303 /* swap (8 in 32) RB and IB */ 290 /* swap (8 in 32) RB and IB */
@@ -306,6 +293,11 @@ static int uvd_v4_2_start(struct amdgpu_device *adev)
306#endif 293#endif
307 WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 294 WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
308 WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); 295 WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
296 /* initialize UVD memory controller */
297 WREG32(mmUVD_LMI_CTRL, 0x203108);
298
299 tmp = RREG32(mmUVD_MPC_CNTL);
300 WREG32(mmUVD_MPC_CNTL, tmp | 0x10);
309 301
310 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); 302 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
311 WREG32(mmUVD_MPC_SET_MUXA1, 0x0); 303 WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
@@ -314,18 +306,20 @@ static int uvd_v4_2_start(struct amdgpu_device *adev)
314 WREG32(mmUVD_MPC_SET_ALU, 0); 306 WREG32(mmUVD_MPC_SET_ALU, 0);
315 WREG32(mmUVD_MPC_SET_MUX, 0x88); 307 WREG32(mmUVD_MPC_SET_MUX, 0x88);
316 308
317 /* take all subblocks out of reset, except VCPU */ 309 uvd_v4_2_mc_resume(adev);
318 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
319 mdelay(5);
320 310
321 /* enable VCPU clock */ 311 tmp = RREG32_UVD_CTX(ixUVD_LMI_CACHE_CTRL);
322 WREG32(mmUVD_VCPU_CNTL, 1 << 9); 312 WREG32_UVD_CTX(ixUVD_LMI_CACHE_CTRL, tmp & (~0x10));
323 313
324 /* enable UMC */ 314 /* enable UMC */
325 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 315 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
326 316
327 /* boot up the VCPU */ 317 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);
328 WREG32(mmUVD_SOFT_RESET, 0); 318
319 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
320
321 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
322
329 mdelay(10); 323 mdelay(10);
330 324
331 for (i = 0; i < 10; ++i) { 325 for (i = 0; i < 10; ++i) {
@@ -357,6 +351,8 @@ static int uvd_v4_2_start(struct amdgpu_device *adev)
357 /* enable interupt */ 351 /* enable interupt */
358 WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1)); 352 WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1));
359 353
354 WREG32_P(mmUVD_STATUS, 0, ~(1<<2));
355
360 /* force RBC into idle state */ 356 /* force RBC into idle state */
361 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 357 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
362 358
@@ -393,22 +389,54 @@ static int uvd_v4_2_start(struct amdgpu_device *adev)
393 */ 389 */
394static void uvd_v4_2_stop(struct amdgpu_device *adev) 390static void uvd_v4_2_stop(struct amdgpu_device *adev)
395{ 391{
396 /* force RBC into idle state */ 392 uint32_t i, j;
393 uint32_t status;
394
397 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 395 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
398 396
397 for (i = 0; i < 10; ++i) {
398 for (j = 0; j < 100; ++j) {
399 status = RREG32(mmUVD_STATUS);
400 if (status & 2)
401 break;
402 mdelay(1);
403 }
404 break;
405 }
406
407 for (i = 0; i < 10; ++i) {
408 for (j = 0; j < 100; ++j) {
409 status = RREG32(mmUVD_LMI_STATUS);
410 if (status & 0xf)
411 break;
412 mdelay(1);
413 }
414 break;
415 }
416
399 /* Stall UMC and register bus before resetting VCPU */ 417 /* Stall UMC and register bus before resetting VCPU */
400 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 418 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
401 mdelay(1);
402 419
403 /* put VCPU into reset */ 420 for (i = 0; i < 10; ++i) {
404 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 421 for (j = 0; j < 100; ++j) {
405 mdelay(5); 422 status = RREG32(mmUVD_LMI_STATUS);
423 if (status & 0x240)
424 break;
425 mdelay(1);
426 }
427 break;
428 }
406 429
407 /* disable VCPU clock */ 430 WREG32_P(0x3D49, 0, ~(1 << 2));
408 WREG32(mmUVD_VCPU_CNTL, 0x0);
409 431
410 /* Unstall UMC and register bus */ 432 WREG32_P(mmUVD_VCPU_CNTL, 0, ~(1 << 9));
411 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 433
434 /* put LMI, VCPU, RBC etc... into reset */
435 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
436 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
437 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
438
439 WREG32(mmUVD_STATUS, 0);
412 440
413 uvd_v4_2_set_dcm(adev, false); 441 uvd_v4_2_set_dcm(adev, false);
414} 442}
@@ -694,8 +722,24 @@ static int uvd_v4_2_set_powergating_state(void *handle,
694 722
695 if (state == AMD_PG_STATE_GATE) { 723 if (state == AMD_PG_STATE_GATE) {
696 uvd_v4_2_stop(adev); 724 uvd_v4_2_stop(adev);
725 if (adev->pg_flags & AMD_PG_SUPPORT_UVD && amdgpu_dpm == 0) {
726 if (!(RREG32_SMC(ixCURRENT_PG_STATUS) & 0x4)) {
727 WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK |
728 UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK |
729 UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK));
730 mdelay(20);
731 }
732 }
697 return 0; 733 return 0;
698 } else { 734 } else {
735 if (adev->pg_flags & AMD_PG_SUPPORT_UVD && amdgpu_dpm == 0) {
736 if (RREG32_SMC(ixCURRENT_PG_STATUS) & 0x4) {
737 WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK |
738 UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK |
739 UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK));
740 mdelay(30);
741 }
742 }
699 return uvd_v4_2_start(adev); 743 return uvd_v4_2_start(adev);
700 } 744 }
701} 745}
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
index 9b49824233ae..46e715193924 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
@@ -152,9 +152,9 @@ static int uvd_v5_0_hw_init(void *handle)
152 uint32_t tmp; 152 uint32_t tmp;
153 int r; 153 int r;
154 154
155 r = uvd_v5_0_start(adev); 155 amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
156 if (r) 156 uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
157 goto done; 157 uvd_v5_0_enable_mgcg(adev, true);
158 158
159 ring->ready = true; 159 ring->ready = true;
160 r = amdgpu_ring_test_ring(ring); 160 r = amdgpu_ring_test_ring(ring);
@@ -189,11 +189,13 @@ static int uvd_v5_0_hw_init(void *handle)
189 amdgpu_ring_write(ring, 3); 189 amdgpu_ring_write(ring, 3);
190 190
191 amdgpu_ring_commit(ring); 191 amdgpu_ring_commit(ring);
192
192done: 193done:
193 if (!r) 194 if (!r)
194 DRM_INFO("UVD initialized successfully.\n"); 195 DRM_INFO("UVD initialized successfully.\n");
195 196
196 return r; 197 return r;
198
197} 199}
198 200
199/** 201/**
@@ -208,7 +210,9 @@ static int uvd_v5_0_hw_fini(void *handle)
208 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 210 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
209 struct amdgpu_ring *ring = &adev->uvd.ring; 211 struct amdgpu_ring *ring = &adev->uvd.ring;
210 212
211 uvd_v5_0_stop(adev); 213 if (RREG32(mmUVD_STATUS) != 0)
214 uvd_v5_0_stop(adev);
215
212 ring->ready = false; 216 ring->ready = false;
213 217
214 return 0; 218 return 0;
@@ -310,10 +314,6 @@ static int uvd_v5_0_start(struct amdgpu_device *adev)
310 314
311 uvd_v5_0_mc_resume(adev); 315 uvd_v5_0_mc_resume(adev);
312 316
313 amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
314 uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
315 uvd_v5_0_enable_mgcg(adev, true);
316
317 /* disable interupt */ 317 /* disable interupt */
318 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); 318 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
319 319
@@ -456,6 +456,8 @@ static void uvd_v5_0_stop(struct amdgpu_device *adev)
456 456
457 /* Unstall UMC and register bus */ 457 /* Unstall UMC and register bus */
458 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 458 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
459
460 WREG32(mmUVD_STATUS, 0);
459} 461}
460 462
461/** 463/**
@@ -792,9 +794,6 @@ static int uvd_v5_0_set_clockgating_state(void *handle,
792 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 794 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
793 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 795 bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
794 796
795 if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
796 return 0;
797
798 if (enable) { 797 if (enable) {
799 /* wait for STATUS to clear */ 798 /* wait for STATUS to clear */
800 if (uvd_v5_0_wait_for_idle(handle)) 799 if (uvd_v5_0_wait_for_idle(handle))
@@ -824,9 +823,6 @@ static int uvd_v5_0_set_powergating_state(void *handle,
824 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 823 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
825 int ret = 0; 824 int ret = 0;
826 825
827 if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
828 return 0;
829
830 if (state == AMD_PG_STATE_GATE) { 826 if (state == AMD_PG_STATE_GATE) {
831 uvd_v5_0_stop(adev); 827 uvd_v5_0_stop(adev);
832 adev->uvd.is_powergated = true; 828 adev->uvd.is_powergated = true;
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index de7e03544d00..af83ab8c1250 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -155,9 +155,9 @@ static int uvd_v6_0_hw_init(void *handle)
155 uint32_t tmp; 155 uint32_t tmp;
156 int r; 156 int r;
157 157
158 r = uvd_v6_0_start(adev); 158 amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
159 if (r) 159 uvd_v6_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
160 goto done; 160 uvd_v6_0_enable_mgcg(adev, true);
161 161
162 ring->ready = true; 162 ring->ready = true;
163 r = amdgpu_ring_test_ring(ring); 163 r = amdgpu_ring_test_ring(ring);
@@ -212,7 +212,9 @@ static int uvd_v6_0_hw_fini(void *handle)
212 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 212 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
213 struct amdgpu_ring *ring = &adev->uvd.ring; 213 struct amdgpu_ring *ring = &adev->uvd.ring;
214 214
215 uvd_v6_0_stop(adev); 215 if (RREG32(mmUVD_STATUS) != 0)
216 uvd_v6_0_stop(adev);
217
216 ring->ready = false; 218 ring->ready = false;
217 219
218 return 0; 220 return 0;
@@ -397,9 +399,6 @@ static int uvd_v6_0_start(struct amdgpu_device *adev)
397 lmi_swap_cntl = 0; 399 lmi_swap_cntl = 0;
398 mp_swap_cntl = 0; 400 mp_swap_cntl = 0;
399 401
400 amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
401 uvd_v6_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
402 uvd_v6_0_enable_mgcg(adev, true);
403 uvd_v6_0_mc_resume(adev); 402 uvd_v6_0_mc_resume(adev);
404 403
405 /* disable interupt */ 404 /* disable interupt */
@@ -554,6 +553,8 @@ static void uvd_v6_0_stop(struct amdgpu_device *adev)
554 553
555 /* Unstall UMC and register bus */ 554 /* Unstall UMC and register bus */
556 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 555 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
556
557 WREG32(mmUVD_STATUS, 0);
557} 558}
558 559
559/** 560/**
@@ -1018,9 +1019,6 @@ static int uvd_v6_0_set_clockgating_state(void *handle,
1018 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1019 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1019 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 1020 bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
1020 1021
1021 if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
1022 return 0;
1023
1024 if (enable) { 1022 if (enable) {
1025 /* wait for STATUS to clear */ 1023 /* wait for STATUS to clear */
1026 if (uvd_v6_0_wait_for_idle(handle)) 1024 if (uvd_v6_0_wait_for_idle(handle))
@@ -1049,9 +1047,6 @@ static int uvd_v6_0_set_powergating_state(void *handle,
1049 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1047 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1050 int ret = 0; 1048 int ret = 0;
1051 1049
1052 if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
1053 return 0;
1054
1055 WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK); 1050 WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
1056 1051
1057 if (state == AMD_PG_STATE_GATE) { 1052 if (state == AMD_PG_STATE_GATE) {
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
index 38ed903dd6f8..9ea99348e493 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
@@ -42,10 +42,9 @@
42#define VCE_V2_0_DATA_SIZE (23552 * AMDGPU_MAX_VCE_HANDLES) 42#define VCE_V2_0_DATA_SIZE (23552 * AMDGPU_MAX_VCE_HANDLES)
43#define VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK 0x02 43#define VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK 0x02
44 44
45static void vce_v2_0_mc_resume(struct amdgpu_device *adev);
46static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev); 45static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev);
47static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev); 46static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev);
48static int vce_v2_0_wait_for_idle(void *handle); 47
49/** 48/**
50 * vce_v2_0_ring_get_rptr - get read pointer 49 * vce_v2_0_ring_get_rptr - get read pointer
51 * 50 *
@@ -140,6 +139,86 @@ static int vce_v2_0_firmware_loaded(struct amdgpu_device *adev)
140 return -ETIMEDOUT; 139 return -ETIMEDOUT;
141} 140}
142 141
142static void vce_v2_0_disable_cg(struct amdgpu_device *adev)
143{
144 WREG32(mmVCE_CGTT_CLK_OVERRIDE, 7);
145}
146
147static void vce_v2_0_init_cg(struct amdgpu_device *adev)
148{
149 u32 tmp;
150
151 tmp = RREG32(mmVCE_CLOCK_GATING_A);
152 tmp &= ~0xfff;
153 tmp |= ((0 << 0) | (4 << 4));
154 tmp |= 0x40000;
155 WREG32(mmVCE_CLOCK_GATING_A, tmp);
156
157 tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
158 tmp &= ~0xfff;
159 tmp |= ((0 << 0) | (4 << 4));
160 WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
161
162 tmp = RREG32(mmVCE_CLOCK_GATING_B);
163 tmp |= 0x10;
164 tmp &= ~0x100000;
165 WREG32(mmVCE_CLOCK_GATING_B, tmp);
166}
167
168static void vce_v2_0_mc_resume(struct amdgpu_device *adev)
169{
170 uint64_t addr = adev->vce.gpu_addr;
171 uint32_t size;
172
173 WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16));
174 WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
175 WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
176 WREG32(mmVCE_CLOCK_GATING_B, 0xf7);
177
178 WREG32(mmVCE_LMI_CTRL, 0x00398000);
179 WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1);
180 WREG32(mmVCE_LMI_SWAP_CNTL, 0);
181 WREG32(mmVCE_LMI_SWAP_CNTL1, 0);
182 WREG32(mmVCE_LMI_VM_CTRL, 0);
183
184 addr += AMDGPU_VCE_FIRMWARE_OFFSET;
185 size = VCE_V2_0_FW_SIZE;
186 WREG32(mmVCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);
187 WREG32(mmVCE_VCPU_CACHE_SIZE0, size);
188
189 addr += size;
190 size = VCE_V2_0_STACK_SIZE;
191 WREG32(mmVCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff);
192 WREG32(mmVCE_VCPU_CACHE_SIZE1, size);
193
194 addr += size;
195 size = VCE_V2_0_DATA_SIZE;
196 WREG32(mmVCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff);
197 WREG32(mmVCE_VCPU_CACHE_SIZE2, size);
198
199 WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100);
200 WREG32_FIELD(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, 1);
201}
202
203static bool vce_v2_0_is_idle(void *handle)
204{
205 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
206
207 return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK);
208}
209
210static int vce_v2_0_wait_for_idle(void *handle)
211{
212 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
213 unsigned i;
214
215 for (i = 0; i < adev->usec_timeout; i++) {
216 if (vce_v2_0_is_idle(handle))
217 return 0;
218 }
219 return -ETIMEDOUT;
220}
221
143/** 222/**
144 * vce_v2_0_start - start VCE block 223 * vce_v2_0_start - start VCE block
145 * 224 *
@@ -152,11 +231,14 @@ static int vce_v2_0_start(struct amdgpu_device *adev)
152 struct amdgpu_ring *ring; 231 struct amdgpu_ring *ring;
153 int r; 232 int r;
154 233
155 vce_v2_0_mc_resume(adev);
156
157 /* set BUSY flag */ 234 /* set BUSY flag */
158 WREG32_P(mmVCE_STATUS, 1, ~1); 235 WREG32_P(mmVCE_STATUS, 1, ~1);
159 236
237 vce_v2_0_init_cg(adev);
238 vce_v2_0_disable_cg(adev);
239
240 vce_v2_0_mc_resume(adev);
241
160 ring = &adev->vce.ring[0]; 242 ring = &adev->vce.ring[0];
161 WREG32(mmVCE_RB_RPTR, ring->wptr); 243 WREG32(mmVCE_RB_RPTR, ring->wptr);
162 WREG32(mmVCE_RB_WPTR, ring->wptr); 244 WREG32(mmVCE_RB_WPTR, ring->wptr);
@@ -189,6 +271,145 @@ static int vce_v2_0_start(struct amdgpu_device *adev)
189 return 0; 271 return 0;
190} 272}
191 273
274static int vce_v2_0_stop(struct amdgpu_device *adev)
275{
276 int i, j;
277 int status;
278
279 if (vce_v2_0_lmi_clean(adev)) {
280 DRM_INFO("vce is not idle \n");
281 return 0;
282 }
283/*
284 for (i = 0; i < 10; ++i) {
285 for (j = 0; j < 100; ++j) {
286 status = RREG32(mmVCE_FW_REG_STATUS);
287 if (!(status & 1))
288 break;
289 mdelay(1);
290 }
291 break;
292 }
293*/
294 if (vce_v2_0_wait_for_idle(adev)) {
295 DRM_INFO("VCE is busy, Can't set clock gateing");
296 return 0;
297 }
298
299 /* Stall UMC and register bus before resetting VCPU */
300 WREG32_P(mmVCE_LMI_CTRL2, 1 << 8, ~(1 << 8));
301
302 for (i = 0; i < 10; ++i) {
303 for (j = 0; j < 100; ++j) {
304 status = RREG32(mmVCE_LMI_STATUS);
305 if (status & 0x240)
306 break;
307 mdelay(1);
308 }
309 break;
310 }
311
312 WREG32_P(mmVCE_VCPU_CNTL, 0, ~0x80001);
313
314 /* put LMI, VCPU, RBC etc... into reset */
315 WREG32_P(mmVCE_SOFT_RESET, 1, ~0x1);
316
317 WREG32(mmVCE_STATUS, 0);
318
319 return 0;
320}
321
322static void vce_v2_0_set_sw_cg(struct amdgpu_device *adev, bool gated)
323{
324 u32 tmp;
325
326 if (gated) {
327 tmp = RREG32(mmVCE_CLOCK_GATING_B);
328 tmp |= 0xe70000;
329 WREG32(mmVCE_CLOCK_GATING_B, tmp);
330
331 tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
332 tmp |= 0xff000000;
333 WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
334
335 tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
336 tmp &= ~0x3fc;
337 WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
338
339 WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);
340 } else {
341 tmp = RREG32(mmVCE_CLOCK_GATING_B);
342 tmp |= 0xe7;
343 tmp &= ~0xe70000;
344 WREG32(mmVCE_CLOCK_GATING_B, tmp);
345
346 tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
347 tmp |= 0x1fe000;
348 tmp &= ~0xff000000;
349 WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
350
351 tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
352 tmp |= 0x3fc;
353 WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
354 }
355}
356
357static void vce_v2_0_set_dyn_cg(struct amdgpu_device *adev, bool gated)
358{
359 u32 orig, tmp;
360
361/* LMI_MC/LMI_UMC always set in dynamic,
362 * set {CGC_*_GATE_MODE, CGC_*_SW_GATE} = {0, 0}
363 */
364 tmp = RREG32(mmVCE_CLOCK_GATING_B);
365 tmp &= ~0x00060006;
366
367/* Exception for ECPU, IH, SEM, SYS blocks needs to be turned on/off by SW */
368 if (gated) {
369 tmp |= 0xe10000;
370 WREG32(mmVCE_CLOCK_GATING_B, tmp);
371 } else {
372 tmp |= 0xe1;
373 tmp &= ~0xe10000;
374 WREG32(mmVCE_CLOCK_GATING_B, tmp);
375 }
376
377 orig = tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
378 tmp &= ~0x1fe000;
379 tmp &= ~0xff000000;
380 if (tmp != orig)
381 WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
382
383 orig = tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
384 tmp &= ~0x3fc;
385 if (tmp != orig)
386 WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
387
388 /* set VCE_UENC_REG_CLOCK_GATING always in dynamic mode */
389 WREG32(mmVCE_UENC_REG_CLOCK_GATING, 0x00);
390
391 if(gated)
392 WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);
393}
394
395static void vce_v2_0_enable_mgcg(struct amdgpu_device *adev, bool enable,
396 bool sw_cg)
397{
398 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG)) {
399 if (sw_cg)
400 vce_v2_0_set_sw_cg(adev, true);
401 else
402 vce_v2_0_set_dyn_cg(adev, true);
403 } else {
404 vce_v2_0_disable_cg(adev);
405
406 if (sw_cg)
407 vce_v2_0_set_sw_cg(adev, false);
408 else
409 vce_v2_0_set_dyn_cg(adev, false);
410 }
411}
412
192static int vce_v2_0_early_init(void *handle) 413static int vce_v2_0_early_init(void *handle)
193{ 414{
194 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 415 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -254,11 +475,8 @@ static int vce_v2_0_hw_init(void *handle)
254 int r, i; 475 int r, i;
255 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 476 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
256 477
257 r = vce_v2_0_start(adev); 478 amdgpu_asic_set_vce_clocks(adev, 10000, 10000);
258 /* this error mean vcpu not in running state, so just skip ring test, not stop driver initialize */ 479 vce_v2_0_enable_mgcg(adev, true, false);
259 if (r)
260 return 0;
261
262 for (i = 0; i < adev->vce.num_rings; i++) 480 for (i = 0; i < adev->vce.num_rings; i++)
263 adev->vce.ring[i].ready = false; 481 adev->vce.ring[i].ready = false;
264 482
@@ -312,190 +530,6 @@ static int vce_v2_0_resume(void *handle)
312 return r; 530 return r;
313} 531}
314 532
315static void vce_v2_0_set_sw_cg(struct amdgpu_device *adev, bool gated)
316{
317 u32 tmp;
318
319 if (gated) {
320 tmp = RREG32(mmVCE_CLOCK_GATING_B);
321 tmp |= 0xe70000;
322 WREG32(mmVCE_CLOCK_GATING_B, tmp);
323
324 tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
325 tmp |= 0xff000000;
326 WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
327
328 tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
329 tmp &= ~0x3fc;
330 WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
331
332 WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);
333 } else {
334 tmp = RREG32(mmVCE_CLOCK_GATING_B);
335 tmp |= 0xe7;
336 tmp &= ~0xe70000;
337 WREG32(mmVCE_CLOCK_GATING_B, tmp);
338
339 tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
340 tmp |= 0x1fe000;
341 tmp &= ~0xff000000;
342 WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
343
344 tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
345 tmp |= 0x3fc;
346 WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
347 }
348}
349
350static void vce_v2_0_set_dyn_cg(struct amdgpu_device *adev, bool gated)
351{
352 if (vce_v2_0_wait_for_idle(adev)) {
353 DRM_INFO("VCE is busy, Can't set clock gateing");
354 return;
355 }
356
357 WREG32_P(mmVCE_LMI_CTRL2, 0x100, ~0x100);
358
359 if (vce_v2_0_lmi_clean(adev)) {
360 DRM_INFO("LMI is busy, Can't set clock gateing");
361 return;
362 }
363
364 WREG32_P(mmVCE_VCPU_CNTL, 0, ~VCE_VCPU_CNTL__CLK_EN_MASK);
365 WREG32_P(mmVCE_SOFT_RESET,
366 VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
367 ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
368 WREG32(mmVCE_STATUS, 0);
369
370 if (gated)
371 WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);
372 /* LMI_MC/LMI_UMC always set in dynamic, set {CGC_*_GATE_MODE, CGC_*_SW_GATE} = {0, 0} */
373 if (gated) {
374 /* Force CLOCK OFF , set {CGC_*_GATE_MODE, CGC_*_SW_GATE} = {*, 1} */
375 WREG32(mmVCE_CLOCK_GATING_B, 0xe90010);
376 } else {
377 /* Force CLOCK ON, set {CGC_*_GATE_MODE, CGC_*_SW_GATE} = {1, 0} */
378 WREG32(mmVCE_CLOCK_GATING_B, 0x800f1);
379 }
380
381 /* Set VCE_UENC_CLOCK_GATING always in dynamic mode {*_FORCE_ON, *_FORCE_OFF} = {0, 0}*/;
382 WREG32(mmVCE_UENC_CLOCK_GATING, 0x40);
383
384 /* set VCE_UENC_REG_CLOCK_GATING always in dynamic mode */
385 WREG32(mmVCE_UENC_REG_CLOCK_GATING, 0x00);
386
387 WREG32_P(mmVCE_LMI_CTRL2, 0, ~0x100);
388 if(!gated) {
389 WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK, ~VCE_VCPU_CNTL__CLK_EN_MASK);
390 mdelay(100);
391 WREG32_P(mmVCE_SOFT_RESET, 0, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
392
393 vce_v2_0_firmware_loaded(adev);
394 WREG32_P(mmVCE_STATUS, 0, ~VCE_STATUS__JOB_BUSY_MASK);
395 }
396}
397
398static void vce_v2_0_disable_cg(struct amdgpu_device *adev)
399{
400 WREG32(mmVCE_CGTT_CLK_OVERRIDE, 7);
401}
402
403static void vce_v2_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
404{
405 bool sw_cg = false;
406
407 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG)) {
408 if (sw_cg)
409 vce_v2_0_set_sw_cg(adev, true);
410 else
411 vce_v2_0_set_dyn_cg(adev, true);
412 } else {
413 vce_v2_0_disable_cg(adev);
414
415 if (sw_cg)
416 vce_v2_0_set_sw_cg(adev, false);
417 else
418 vce_v2_0_set_dyn_cg(adev, false);
419 }
420}
421
422static void vce_v2_0_init_cg(struct amdgpu_device *adev)
423{
424 u32 tmp;
425
426 tmp = RREG32(mmVCE_CLOCK_GATING_A);
427 tmp &= ~0xfff;
428 tmp |= ((0 << 0) | (4 << 4));
429 tmp |= 0x40000;
430 WREG32(mmVCE_CLOCK_GATING_A, tmp);
431
432 tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
433 tmp &= ~0xfff;
434 tmp |= ((0 << 0) | (4 << 4));
435 WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
436
437 tmp = RREG32(mmVCE_CLOCK_GATING_B);
438 tmp |= 0x10;
439 tmp &= ~0x100000;
440 WREG32(mmVCE_CLOCK_GATING_B, tmp);
441}
442
443static void vce_v2_0_mc_resume(struct amdgpu_device *adev)
444{
445 uint64_t addr = adev->vce.gpu_addr;
446 uint32_t size;
447
448 WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16));
449 WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
450 WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
451 WREG32(mmVCE_CLOCK_GATING_B, 0xf7);
452
453 WREG32(mmVCE_LMI_CTRL, 0x00398000);
454 WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1);
455 WREG32(mmVCE_LMI_SWAP_CNTL, 0);
456 WREG32(mmVCE_LMI_SWAP_CNTL1, 0);
457 WREG32(mmVCE_LMI_VM_CTRL, 0);
458
459 addr += AMDGPU_VCE_FIRMWARE_OFFSET;
460 size = VCE_V2_0_FW_SIZE;
461 WREG32(mmVCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);
462 WREG32(mmVCE_VCPU_CACHE_SIZE0, size);
463
464 addr += size;
465 size = VCE_V2_0_STACK_SIZE;
466 WREG32(mmVCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff);
467 WREG32(mmVCE_VCPU_CACHE_SIZE1, size);
468
469 addr += size;
470 size = VCE_V2_0_DATA_SIZE;
471 WREG32(mmVCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff);
472 WREG32(mmVCE_VCPU_CACHE_SIZE2, size);
473
474 WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100);
475 WREG32_FIELD(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, 1);
476
477 vce_v2_0_init_cg(adev);
478}
479
480static bool vce_v2_0_is_idle(void *handle)
481{
482 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
483
484 return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK);
485}
486
487static int vce_v2_0_wait_for_idle(void *handle)
488{
489 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
490 unsigned i;
491
492 for (i = 0; i < adev->usec_timeout; i++) {
493 if (vce_v2_0_is_idle(handle))
494 return 0;
495 }
496 return -ETIMEDOUT;
497}
498
499static int vce_v2_0_soft_reset(void *handle) 533static int vce_v2_0_soft_reset(void *handle)
500{ 534{
501 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 535 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -539,33 +573,20 @@ static int vce_v2_0_process_interrupt(struct amdgpu_device *adev,
539 return 0; 573 return 0;
540} 574}
541 575
542static void vce_v2_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)
543{
544 u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
545
546 if (enable)
547 tmp |= GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK;
548 else
549 tmp &= ~GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK;
550
551 WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
552}
553
554
555static int vce_v2_0_set_clockgating_state(void *handle, 576static int vce_v2_0_set_clockgating_state(void *handle,
556 enum amd_clockgating_state state) 577 enum amd_clockgating_state state)
557{ 578{
558 bool gate = false; 579 bool gate = false;
559 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 580 bool sw_cg = false;
560 bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
561
562 581
563 vce_v2_0_set_bypass_mode(adev, enable); 582 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
564 583
565 if (state == AMD_CG_STATE_GATE) 584 if (state == AMD_CG_STATE_GATE) {
566 gate = true; 585 gate = true;
586 sw_cg = true;
587 }
567 588
568 vce_v2_0_enable_mgcg(adev, gate); 589 vce_v2_0_enable_mgcg(adev, gate, sw_cg);
569 590
570 return 0; 591 return 0;
571} 592}
@@ -582,12 +603,8 @@ static int vce_v2_0_set_powergating_state(void *handle,
582 */ 603 */
583 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 604 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
584 605
585 if (!(adev->pg_flags & AMD_PG_SUPPORT_VCE))
586 return 0;
587
588 if (state == AMD_PG_STATE_GATE) 606 if (state == AMD_PG_STATE_GATE)
589 /* XXX do we need a vce_v2_0_stop()? */ 607 return vce_v2_0_stop(adev);
590 return 0;
591 else 608 else
592 return vce_v2_0_start(adev); 609 return vce_v2_0_start(adev);
593} 610}
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index 8db26559fd1b..a8c40eebdd78 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -230,10 +230,6 @@ static int vce_v3_0_start(struct amdgpu_device *adev)
230 struct amdgpu_ring *ring; 230 struct amdgpu_ring *ring;
231 int idx, r; 231 int idx, r;
232 232
233 vce_v3_0_override_vce_clock_gating(adev, true);
234 if (!(adev->flags & AMD_IS_APU))
235 amdgpu_asic_set_vce_clocks(adev, 10000, 10000);
236
237 ring = &adev->vce.ring[0]; 233 ring = &adev->vce.ring[0];
238 WREG32(mmVCE_RB_RPTR, ring->wptr); 234 WREG32(mmVCE_RB_RPTR, ring->wptr);
239 WREG32(mmVCE_RB_WPTR, ring->wptr); 235 WREG32(mmVCE_RB_WPTR, ring->wptr);
@@ -436,9 +432,9 @@ static int vce_v3_0_hw_init(void *handle)
436 int r, i; 432 int r, i;
437 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 433 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
438 434
439 r = vce_v3_0_start(adev); 435 vce_v3_0_override_vce_clock_gating(adev, true);
440 if (r) 436 if (!(adev->flags & AMD_IS_APU))
441 return r; 437 amdgpu_asic_set_vce_clocks(adev, 10000, 10000);
442 438
443 for (i = 0; i < adev->vce.num_rings; i++) 439 for (i = 0; i < adev->vce.num_rings; i++)
444 adev->vce.ring[i].ready = false; 440 adev->vce.ring[i].ready = false;
@@ -766,12 +762,11 @@ static int vce_v3_0_set_powergating_state(void *handle,
766 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 762 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
767 int ret = 0; 763 int ret = 0;
768 764
769 if (!(adev->pg_flags & AMD_PG_SUPPORT_VCE))
770 return 0;
771
772 if (state == AMD_PG_STATE_GATE) { 765 if (state == AMD_PG_STATE_GATE) {
766 ret = vce_v3_0_stop(adev);
767 if (ret)
768 goto out;
773 adev->vce.is_powergated = true; 769 adev->vce.is_powergated = true;
774 /* XXX do we need a vce_v3_0_stop()? */
775 } else { 770 } else {
776 ret = vce_v3_0_start(adev); 771 ret = vce_v3_0_start(adev);
777 if (ret) 772 if (ret)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_d.h
index f9fd2ea4625b..dbc2e723f659 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_d.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_d.h
@@ -1310,5 +1310,6 @@
1310#define ixROM_SW_DATA_62 0xc060012c 1310#define ixROM_SW_DATA_62 0xc060012c
1311#define ixROM_SW_DATA_63 0xc0600130 1311#define ixROM_SW_DATA_63 0xc0600130
1312#define ixROM_SW_DATA_64 0xc0600134 1312#define ixROM_SW_DATA_64 0xc0600134
1313#define ixCURRENT_PG_STATUS 0xc020029c
1313 1314
1314#endif /* SMU_7_0_1_D_H */ 1315#endif /* SMU_7_0_1_D_H */
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
index 3eccac735db3..b33935fcf428 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
@@ -161,28 +161,25 @@ int cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
161{ 161{
162 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); 162 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
163 163
164 if (cz_hwmgr->uvd_power_gated == bgate)
165 return 0;
166
167 cz_hwmgr->uvd_power_gated = bgate; 164 cz_hwmgr->uvd_power_gated = bgate;
168 165
169 if (bgate) { 166 if (bgate) {
170 cgs_set_clockgating_state(hwmgr->device,
171 AMD_IP_BLOCK_TYPE_UVD,
172 AMD_CG_STATE_GATE);
173 cgs_set_powergating_state(hwmgr->device, 167 cgs_set_powergating_state(hwmgr->device,
174 AMD_IP_BLOCK_TYPE_UVD, 168 AMD_IP_BLOCK_TYPE_UVD,
175 AMD_PG_STATE_GATE); 169 AMD_PG_STATE_GATE);
170 cgs_set_clockgating_state(hwmgr->device,
171 AMD_IP_BLOCK_TYPE_UVD,
172 AMD_CG_STATE_GATE);
176 cz_dpm_update_uvd_dpm(hwmgr, true); 173 cz_dpm_update_uvd_dpm(hwmgr, true);
177 cz_dpm_powerdown_uvd(hwmgr); 174 cz_dpm_powerdown_uvd(hwmgr);
178 } else { 175 } else {
179 cz_dpm_powerup_uvd(hwmgr); 176 cz_dpm_powerup_uvd(hwmgr);
180 cgs_set_powergating_state(hwmgr->device,
181 AMD_IP_BLOCK_TYPE_UVD,
182 AMD_CG_STATE_UNGATE);
183 cgs_set_clockgating_state(hwmgr->device, 177 cgs_set_clockgating_state(hwmgr->device,
184 AMD_IP_BLOCK_TYPE_UVD, 178 AMD_IP_BLOCK_TYPE_UVD,
185 AMD_PG_STATE_UNGATE); 179 AMD_PG_STATE_UNGATE);
180 cgs_set_powergating_state(hwmgr->device,
181 AMD_IP_BLOCK_TYPE_UVD,
182 AMD_CG_STATE_UNGATE);
186 cz_dpm_update_uvd_dpm(hwmgr, false); 183 cz_dpm_update_uvd_dpm(hwmgr, false);
187 } 184 }
188 185
@@ -193,47 +190,34 @@ int cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
193{ 190{
194 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); 191 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
195 192
196 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 193 if (bgate) {
197 PHM_PlatformCaps_VCEPowerGating)) { 194 cgs_set_powergating_state(
198 if (cz_hwmgr->vce_power_gated != bgate) { 195 hwmgr->device,
199 if (bgate) { 196 AMD_IP_BLOCK_TYPE_VCE,
200 cgs_set_clockgating_state( 197 AMD_PG_STATE_GATE);
201 hwmgr->device, 198 cgs_set_clockgating_state(
202 AMD_IP_BLOCK_TYPE_VCE, 199 hwmgr->device,
203 AMD_CG_STATE_GATE); 200 AMD_IP_BLOCK_TYPE_VCE,
204 cgs_set_powergating_state( 201 AMD_CG_STATE_GATE);
205 hwmgr->device, 202 cz_enable_disable_vce_dpm(hwmgr, false);
206 AMD_IP_BLOCK_TYPE_VCE, 203 cz_dpm_powerdown_vce(hwmgr);
207 AMD_PG_STATE_GATE); 204 cz_hwmgr->vce_power_gated = true;
208 cz_enable_disable_vce_dpm(hwmgr, false);
209 cz_dpm_powerdown_vce(hwmgr);
210 cz_hwmgr->vce_power_gated = true;
211 } else {
212 cz_dpm_powerup_vce(hwmgr);
213 cz_hwmgr->vce_power_gated = false;
214 cgs_set_powergating_state(
215 hwmgr->device,
216 AMD_IP_BLOCK_TYPE_VCE,
217 AMD_CG_STATE_UNGATE);
218 cgs_set_clockgating_state(
219 hwmgr->device,
220 AMD_IP_BLOCK_TYPE_VCE,
221 AMD_PG_STATE_UNGATE);
222 cz_dpm_update_vce_dpm(hwmgr);
223 cz_enable_disable_vce_dpm(hwmgr, true);
224 return 0;
225 }
226 }
227 } else { 205 } else {
228 cz_hwmgr->vce_power_gated = bgate; 206 cz_dpm_powerup_vce(hwmgr);
207 cz_hwmgr->vce_power_gated = false;
208 cgs_set_clockgating_state(
209 hwmgr->device,
210 AMD_IP_BLOCK_TYPE_VCE,
211 AMD_PG_STATE_UNGATE);
212 cgs_set_powergating_state(
213 hwmgr->device,
214 AMD_IP_BLOCK_TYPE_VCE,
215 AMD_CG_STATE_UNGATE);
229 cz_dpm_update_vce_dpm(hwmgr); 216 cz_dpm_update_vce_dpm(hwmgr);
230 cz_enable_disable_vce_dpm(hwmgr, !bgate); 217 cz_enable_disable_vce_dpm(hwmgr, true);
231 return 0; 218 return 0;
232 } 219 }
233 220
234 if (!cz_hwmgr->vce_power_gated)
235 cz_dpm_update_vce_dpm(hwmgr);
236
237 return 0; 221 return 0;
238} 222}
239 223
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
index a1fc4fcac1e0..8cf71f3c6d0e 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
@@ -147,22 +147,22 @@ int smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
147 data->uvd_power_gated = bgate; 147 data->uvd_power_gated = bgate;
148 148
149 if (bgate) { 149 if (bgate) {
150 cgs_set_clockgating_state(hwmgr->device,
151 AMD_IP_BLOCK_TYPE_UVD,
152 AMD_CG_STATE_GATE);
153 cgs_set_powergating_state(hwmgr->device, 150 cgs_set_powergating_state(hwmgr->device,
154 AMD_IP_BLOCK_TYPE_UVD, 151 AMD_IP_BLOCK_TYPE_UVD,
155 AMD_PG_STATE_GATE); 152 AMD_PG_STATE_GATE);
153 cgs_set_clockgating_state(hwmgr->device,
154 AMD_IP_BLOCK_TYPE_UVD,
155 AMD_CG_STATE_GATE);
156 smu7_update_uvd_dpm(hwmgr, true); 156 smu7_update_uvd_dpm(hwmgr, true);
157 smu7_powerdown_uvd(hwmgr); 157 smu7_powerdown_uvd(hwmgr);
158 } else { 158 } else {
159 smu7_powerup_uvd(hwmgr); 159 smu7_powerup_uvd(hwmgr);
160 cgs_set_powergating_state(hwmgr->device,
161 AMD_IP_BLOCK_TYPE_UVD,
162 AMD_CG_STATE_UNGATE);
163 cgs_set_clockgating_state(hwmgr->device, 160 cgs_set_clockgating_state(hwmgr->device,
164 AMD_IP_BLOCK_TYPE_UVD, 161 AMD_IP_BLOCK_TYPE_UVD,
165 AMD_CG_STATE_UNGATE); 162 AMD_CG_STATE_UNGATE);
163 cgs_set_powergating_state(hwmgr->device,
164 AMD_IP_BLOCK_TYPE_UVD,
165 AMD_CG_STATE_UNGATE);
166 smu7_update_uvd_dpm(hwmgr, false); 166 smu7_update_uvd_dpm(hwmgr, false);
167 } 167 }
168 168
@@ -173,12 +173,12 @@ int smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
173{ 173{
174 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 174 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
175 175
176 if (data->vce_power_gated == bgate)
177 return 0;
178
179 data->vce_power_gated = bgate; 176 data->vce_power_gated = bgate;
180 177
181 if (bgate) { 178 if (bgate) {
179 cgs_set_powergating_state(hwmgr->device,
180 AMD_IP_BLOCK_TYPE_VCE,
181 AMD_PG_STATE_UNGATE);
182 cgs_set_clockgating_state(hwmgr->device, 182 cgs_set_clockgating_state(hwmgr->device,
183 AMD_IP_BLOCK_TYPE_VCE, 183 AMD_IP_BLOCK_TYPE_VCE,
184 AMD_CG_STATE_GATE); 184 AMD_CG_STATE_GATE);
@@ -186,10 +186,13 @@ int smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
186 smu7_powerdown_vce(hwmgr); 186 smu7_powerdown_vce(hwmgr);
187 } else { 187 } else {
188 smu7_powerup_vce(hwmgr); 188 smu7_powerup_vce(hwmgr);
189 smu7_update_vce_dpm(hwmgr, false);
190 cgs_set_clockgating_state(hwmgr->device, 189 cgs_set_clockgating_state(hwmgr->device,
191 AMD_IP_BLOCK_TYPE_VCE, 190 AMD_IP_BLOCK_TYPE_VCE,
192 AMD_CG_STATE_UNGATE); 191 AMD_CG_STATE_UNGATE);
192 cgs_set_powergating_state(hwmgr->device,
193 AMD_IP_BLOCK_TYPE_VCE,
194 AMD_PG_STATE_UNGATE);
195 smu7_update_vce_dpm(hwmgr, false);
193 } 196 }
194 return 0; 197 return 0;
195} 198}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 0a6c833720df..b1de9e8ccdbc 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -2624,6 +2624,7 @@ static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr,
2624 smu7_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask); 2624 smu7_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask);
2625 smu7_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask); 2625 smu7_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask);
2626 smu7_force_clock_level(hwmgr, PP_PCIE, 1<<pcie_mask); 2626 smu7_force_clock_level(hwmgr, PP_PCIE, 1<<pcie_mask);
2627
2627 break; 2628 break;
2628 case AMD_DPM_FORCED_LEVEL_MANUAL: 2629 case AMD_DPM_FORCED_LEVEL_MANUAL:
2629 hwmgr->dpm_level = level; 2630 hwmgr->dpm_level = level;
@@ -2633,9 +2634,9 @@ static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr,
2633 break; 2634 break;
2634 } 2635 }
2635 2636
2636 if (level & (AMD_DPM_FORCED_LEVEL_PROFILE_PEAK | AMD_DPM_FORCED_LEVEL_HIGH)) 2637 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->saved_dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
2637 smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 100); 2638 smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
2638 else 2639 else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->saved_dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
2639 smu7_fan_ctrl_reset_fan_speed_to_default(hwmgr); 2640 smu7_fan_ctrl_reset_fan_speed_to_default(hwmgr);
2640 2641
2641 return 0; 2642 return 0;
@@ -4397,16 +4398,14 @@ static int smu7_get_sclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks)
4397 if (table_info == NULL || table_info->vdd_dep_on_sclk == NULL) 4398 if (table_info == NULL || table_info->vdd_dep_on_sclk == NULL)
4398 return -EINVAL; 4399 return -EINVAL;
4399 dep_sclk_table = table_info->vdd_dep_on_sclk; 4400 dep_sclk_table = table_info->vdd_dep_on_sclk;
4400 for (i = 0; i < dep_sclk_table->count; i++) { 4401 for (i = 0; i < dep_sclk_table->count; i++)
4401 clocks->clock[i] = dep_sclk_table->entries[i].clk; 4402 clocks->clock[i] = dep_sclk_table->entries[i].clk;
4402 clocks->count++; 4403 clocks->count = dep_sclk_table->count;
4403 }
4404 } else if (hwmgr->pp_table_version == PP_TABLE_V0) { 4404 } else if (hwmgr->pp_table_version == PP_TABLE_V0) {
4405 sclk_table = hwmgr->dyn_state.vddc_dependency_on_sclk; 4405 sclk_table = hwmgr->dyn_state.vddc_dependency_on_sclk;
4406 for (i = 0; i < sclk_table->count; i++) { 4406 for (i = 0; i < sclk_table->count; i++)
4407 clocks->clock[i] = sclk_table->entries[i].clk; 4407 clocks->clock[i] = sclk_table->entries[i].clk;
4408 clocks->count++; 4408 clocks->count = sclk_table->count;
4409 }
4410 } 4409 }
4411 4410
4412 return 0; 4411 return 0;
@@ -4440,14 +4439,13 @@ static int smu7_get_mclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks)
4440 clocks->clock[i] = dep_mclk_table->entries[i].clk; 4439 clocks->clock[i] = dep_mclk_table->entries[i].clk;
4441 clocks->latency[i] = smu7_get_mem_latency(hwmgr, 4440 clocks->latency[i] = smu7_get_mem_latency(hwmgr,
4442 dep_mclk_table->entries[i].clk); 4441 dep_mclk_table->entries[i].clk);
4443 clocks->count++;
4444 } 4442 }
4443 clocks->count = dep_mclk_table->count;
4445 } else if (hwmgr->pp_table_version == PP_TABLE_V0) { 4444 } else if (hwmgr->pp_table_version == PP_TABLE_V0) {
4446 mclk_table = hwmgr->dyn_state.vddc_dependency_on_mclk; 4445 mclk_table = hwmgr->dyn_state.vddc_dependency_on_mclk;
4447 for (i = 0; i < mclk_table->count; i++) { 4446 for (i = 0; i < mclk_table->count; i++)
4448 clocks->clock[i] = mclk_table->entries[i].clk; 4447 clocks->clock[i] = mclk_table->entries[i].clk;
4449 clocks->count++; 4448 clocks->count = mclk_table->count;
4450 }
4451 } 4449 }
4452 return 0; 4450 return 0;
4453} 4451}
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
index 60c36928284c..c0956a4207a9 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
@@ -37,8 +37,10 @@ MODULE_FIRMWARE("amdgpu/tonga_k_smc.bin");
37MODULE_FIRMWARE("amdgpu/fiji_smc.bin"); 37MODULE_FIRMWARE("amdgpu/fiji_smc.bin");
38MODULE_FIRMWARE("amdgpu/polaris10_smc.bin"); 38MODULE_FIRMWARE("amdgpu/polaris10_smc.bin");
39MODULE_FIRMWARE("amdgpu/polaris10_smc_sk.bin"); 39MODULE_FIRMWARE("amdgpu/polaris10_smc_sk.bin");
40MODULE_FIRMWARE("amdgpu/polaris10_k_smc.bin");
40MODULE_FIRMWARE("amdgpu/polaris11_smc.bin"); 41MODULE_FIRMWARE("amdgpu/polaris11_smc.bin");
41MODULE_FIRMWARE("amdgpu/polaris11_smc_sk.bin"); 42MODULE_FIRMWARE("amdgpu/polaris11_smc_sk.bin");
43MODULE_FIRMWARE("amdgpu/polaris11_k_smc.bin");
42MODULE_FIRMWARE("amdgpu/polaris12_smc.bin"); 44MODULE_FIRMWARE("amdgpu/polaris12_smc.bin");
43 45
44 46
diff --git a/drivers/gpu/drm/radeon/radeon_bios.c b/drivers/gpu/drm/radeon/radeon_bios.c
index 00cfb5d2875f..04c0ed41374f 100644
--- a/drivers/gpu/drm/radeon/radeon_bios.c
+++ b/drivers/gpu/drm/radeon/radeon_bios.c
@@ -638,10 +638,8 @@ static bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
638 vhdr->ImageLength, 638 vhdr->ImageLength,
639 GFP_KERNEL); 639 GFP_KERNEL);
640 640
641 if (!rdev->bios) { 641 if (!rdev->bios)
642 kfree(rdev->bios);
643 return false; 642 return false;
644 }
645 return true; 643 return true;
646 } 644 }
647 } 645 }
diff --git a/drivers/gpu/drm/radeon/vce_v1_0.c b/drivers/gpu/drm/radeon/vce_v1_0.c
index a01efe39a820..f541a4b5ac51 100644
--- a/drivers/gpu/drm/radeon/vce_v1_0.c
+++ b/drivers/gpu/drm/radeon/vce_v1_0.c
@@ -196,7 +196,7 @@ int vce_v1_0_load_fw(struct radeon_device *rdev, uint32_t *data)
196 memset(&data[5], 0, 44); 196 memset(&data[5], 0, 44);
197 memcpy(&data[16], &sign[1], rdev->vce_fw->size - sizeof(*sign)); 197 memcpy(&data[16], &sign[1], rdev->vce_fw->size - sizeof(*sign));
198 198
199 data += le32_to_cpu(data[4]) / 4; 199 data += (le32_to_cpu(sign->len) + 64) / 4;
200 data[0] = sign->val[i].sigval[0]; 200 data[0] = sign->val[i].sigval[0];
201 data[1] = sign->val[i].sigval[1]; 201 data[1] = sign->val[i].sigval[1];
202 data[2] = sign->val[i].sigval[2]; 202 data[2] = sign->val[i].sigval[2];
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-30 18:19:54 -0400