diff options
author | Evan Quan <evan.quan@amd.com> | 2018-01-02 21:28:10 -0500 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2018-02-19 14:17:09 -0500 |
commit | 10cd19c87736c1354ef7c175729433b73a988fb1 (patch) | |
tree | e5e97bce375f6efe2ae12fccdcc3b43f69c0233a /drivers/gpu/drm | |
parent | 31a47dcab86a09ef52b5fa644f0926afe367cb90 (diff) |
drm/amd/powerplay: use ffs/fls instead of implementing our own
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 27 |
1 files changed, 4 insertions, 23 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c index 455becd16f00..055138f9e1f8 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | |||
@@ -4489,7 +4489,6 @@ static int vega10_force_clock_level(struct pp_hwmgr *hwmgr, | |||
4489 | enum pp_clock_type type, uint32_t mask) | 4489 | enum pp_clock_type type, uint32_t mask) |
4490 | { | 4490 | { |
4491 | struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend); | 4491 | struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend); |
4492 | int i; | ||
4493 | 4492 | ||
4494 | if (hwmgr->request_dpm_level & (AMD_DPM_FORCED_LEVEL_AUTO | | 4493 | if (hwmgr->request_dpm_level & (AMD_DPM_FORCED_LEVEL_AUTO | |
4495 | AMD_DPM_FORCED_LEVEL_LOW | | 4494 | AMD_DPM_FORCED_LEVEL_LOW | |
@@ -4498,17 +4497,8 @@ static int vega10_force_clock_level(struct pp_hwmgr *hwmgr, | |||
4498 | 4497 | ||
4499 | switch (type) { | 4498 | switch (type) { |
4500 | case PP_SCLK: | 4499 | case PP_SCLK: |
4501 | for (i = 0; i < 32; i++) { | 4500 | data->smc_state_table.gfx_boot_level = mask ? (ffs(mask) - 1) : 0; |
4502 | if (mask & (1 << i)) | 4501 | data->smc_state_table.gfx_max_level = mask ? (fls(mask) - 1) : 0; |
4503 | break; | ||
4504 | } | ||
4505 | data->smc_state_table.gfx_boot_level = i; | ||
4506 | |||
4507 | for (i = 31; i >= 0; i--) { | ||
4508 | if (mask & (1 << i)) | ||
4509 | break; | ||
4510 | } | ||
4511 | data->smc_state_table.gfx_max_level = i; | ||
4512 | 4502 | ||
4513 | PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), | 4503 | PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), |
4514 | "Failed to upload boot level to lowest!", | 4504 | "Failed to upload boot level to lowest!", |
@@ -4520,17 +4510,8 @@ static int vega10_force_clock_level(struct pp_hwmgr *hwmgr, | |||
4520 | break; | 4510 | break; |
4521 | 4511 | ||
4522 | case PP_MCLK: | 4512 | case PP_MCLK: |
4523 | for (i = 0; i < 32; i++) { | 4513 | data->smc_state_table.mem_boot_level = mask ? (ffs(mask) - 1) : 0; |
4524 | if (mask & (1 << i)) | 4514 | data->smc_state_table.mem_max_level = mask ? (fls(mask) - 1) : 0; |
4525 | break; | ||
4526 | } | ||
4527 | data->smc_state_table.mem_boot_level = i; | ||
4528 | |||
4529 | for (i = 31; i >= 0; i--) { | ||
4530 | if (mask & (1 << i)) | ||
4531 | break; | ||
4532 | } | ||
4533 | data->smc_state_table.mem_max_level = i; | ||
4534 | 4515 | ||
4535 | PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), | 4516 | PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), |
4536 | "Failed to upload boot level to lowest!", | 4517 | "Failed to upload boot level to lowest!", |