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authorAndrzej Hajda <a.hajda@samsung.com>2015-07-09 02:25:43 -0400
committerInki Dae <inki.dae@samsung.com>2015-08-15 21:23:33 -0400
commit0df5e4acf584ad1b1b5689d283e1e81655eefab1 (patch)
tree5c6546cf023c676517d1f0cd73245f2f6108273f /drivers/gpu/drm
parenta44652e845739b88214adf9f40478f1ed037348d (diff)
drm/exynos/mixer: replace MXR_INT_EN register cache with flag
Driver uses only VSYNC interrupts, so we need to cache VSYNC bit state only. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Reviewed-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/exynos/exynos_mixer.c20
1 files changed, 9 insertions, 11 deletions
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
index e275e36af0ae..c6384feaf2a2 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -71,6 +71,7 @@ enum mixer_version_id {
71 71
72enum mixer_flag_bits { 72enum mixer_flag_bits {
73 MXR_BIT_POWERED, 73 MXR_BIT_POWERED,
74 MXR_BIT_VSYNC,
74}; 75};
75 76
76struct mixer_context { 77struct mixer_context {
@@ -84,7 +85,6 @@ struct mixer_context {
84 bool interlace; 85 bool interlace;
85 bool vp_enabled; 86 bool vp_enabled;
86 bool has_sclk; 87 bool has_sclk;
87 u32 int_en;
88 88
89 struct mixer_resources mixer_res; 89 struct mixer_resources mixer_res;
90 enum mixer_version_id mxr_ver; 90 enum mixer_version_id mxr_ver;
@@ -902,10 +902,9 @@ static int mixer_enable_vblank(struct exynos_drm_crtc *crtc)
902 struct mixer_context *mixer_ctx = crtc->ctx; 902 struct mixer_context *mixer_ctx = crtc->ctx;
903 struct mixer_resources *res = &mixer_ctx->mixer_res; 903 struct mixer_resources *res = &mixer_ctx->mixer_res;
904 904
905 if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags)) { 905 __set_bit(MXR_BIT_VSYNC, &mixer_ctx->flags);
906 mixer_ctx->int_en |= MXR_INT_EN_VSYNC; 906 if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags))
907 return 0; 907 return 0;
908 }
909 908
910 /* enable vsync interrupt */ 909 /* enable vsync interrupt */
911 mixer_reg_writemask(res, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC); 910 mixer_reg_writemask(res, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC);
@@ -919,10 +918,10 @@ static void mixer_disable_vblank(struct exynos_drm_crtc *crtc)
919 struct mixer_context *mixer_ctx = crtc->ctx; 918 struct mixer_context *mixer_ctx = crtc->ctx;
920 struct mixer_resources *res = &mixer_ctx->mixer_res; 919 struct mixer_resources *res = &mixer_ctx->mixer_res;
921 920
922 if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags)) { 921 __clear_bit(MXR_BIT_VSYNC, &mixer_ctx->flags);
923 mixer_ctx->int_en &= MXR_INT_EN_VSYNC; 922
923 if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags))
924 return; 924 return;
925 }
926 925
927 /* disable vsync interrupt */ 926 /* disable vsync interrupt */
928 mixer_reg_writemask(res, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC); 927 mixer_reg_writemask(res, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC);
@@ -1035,9 +1034,10 @@ static void mixer_enable(struct exynos_drm_crtc *crtc)
1035 1034
1036 mixer_reg_writemask(res, MXR_STATUS, ~0, MXR_STATUS_SOFT_RESET); 1035 mixer_reg_writemask(res, MXR_STATUS, ~0, MXR_STATUS_SOFT_RESET);
1037 1036
1038 if (ctx->int_en & MXR_INT_EN_VSYNC) 1037 if (test_bit(MXR_BIT_VSYNC, &ctx->flags)) {
1039 mixer_reg_writemask(res, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC); 1038 mixer_reg_writemask(res, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC);
1040 mixer_reg_write(res, MXR_INT_EN, ctx->int_en); 1039 mixer_reg_writemask(res, MXR_INT_EN, ~0, MXR_INT_EN_VSYNC);
1040 }
1041 mixer_win_reset(ctx); 1041 mixer_win_reset(ctx);
1042} 1042}
1043 1043
@@ -1056,8 +1056,6 @@ static void mixer_disable(struct exynos_drm_crtc *crtc)
1056 for (i = 0; i < MIXER_WIN_NR; i++) 1056 for (i = 0; i < MIXER_WIN_NR; i++)
1057 mixer_win_disable(crtc, i); 1057 mixer_win_disable(crtc, i);
1058 1058
1059 ctx->int_en = mixer_reg_read(res, MXR_INT_EN);
1060
1061 clear_bit(MXR_BIT_POWERED, &ctx->flags); 1059 clear_bit(MXR_BIT_POWERED, &ctx->flags);
1062 1060
1063 clk_disable_unprepare(res->hdmi); 1061 clk_disable_unprepare(res->hdmi);